Tech Center 2800 • Art Units: 2815 2898
This examiner grants 82% of resolved cases
Eugene Lee is an examiner in Art Unit 2815, which is part of Tech Center 2800. He has a high volume of 922 resolved cases, providing a very robust data set for analysis. The allowance rate for this examiner is 81.9 percent, which is a high and favorable figure for patent applicants. The interview lift is 5.8 percent, suggesting that direct communication can provide a modest boost to the probability of allowance. This 5.8 percent lift is a factor for practitioners to consider when planning their interaction strategy.
The median time to allowance is 979 days, which is under the three-year mark and indicates an efficient process. This 979-day timeline, paired with the 81.9 percent allowance rate, offers a clear and predictable path for patent applicants. The 5.8 percent interview lift indicates that while interviews are helpful, they are not the primary driver of the examiner's decisions. With 922 resolved cases, the data reflects a consistent and professional examination style. Practitioners should focus on clear and persuasive written arguments to maintain efficiency. The 979-day median pendency remains a solid benchmark for managing client expectations. Overall, the data indicates that this examiner is both productive and receptive to patent applications.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18805670 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE | Non-Final OA | Samsung Electronics Co., Ltd. |
| 18745694 | SEMICONDUCTOR PACKAGE | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18735313 | SEMICONDUCTOR DEVICE | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18664690 | SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME | Non-Final OA | Samsung Electronics Co., Ltd. |
| 18660677 | SEMICONDUCTOR PACKAGE | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18652312 | INTERPOSER AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD |
| 18382546 | SEMICONDUCTOR DEVICE HAVING THROUGH-VIA STRUCTURE | Final Rejection | SAMSUNG ELECTRONICS CO., LTD. |
| 17951702 | PACKAGE COMPRISING A FLEXIBLE SUBSTRATE | Non-Final OA | QUALCOMM Incorporated |
| 18806198 | WARPAGE CONTROL STRUCTURE FOR METAL BASE PLATE, SEMICONDUCTOR MODULE, AND INVERTER DEVICE | Non-Final OA | Mitsubishi Electric Corporation |
| 18746332 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS | Final Rejection | SONY SEMICONDUCTOR SOLUTIONS CORPORATION |
| 18700127 | SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | Non-Final OA | SONY SEMICONDUCTOR SOLUTIONS CORPORATION |
| 18577167 | LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, AND METHOD OF MANUFACTURING LIGHT-EMITTING ELEMENT | Final Rejection | Sharp Display Technology Corporation |
| 18611804 | STACKED COMPLIMENTARY METAL-OXIDE SEMICONDUCTOR STRUCTURE | Final Rejection | International Business Machines Corporation |
| 18382471 | HYBRID HIGH BANDWIDTH MEMORY STACK | Final Rejection | International Business Machines Corporation |
| 18622547 | SEMICONDUCTOR PACKAGES WITH COMPACT LEAD DESIGN | Non-Final OA | TEXAS INSTRUMENTS INCORPORATED |
| 18459230 | INTEGRATED CIRCUIT WITH INDUCTOR IN MAGNETIC PACKAGE | Final Rejection | TEXAS INSTRUMENTS INCORPORATED |
| 18458193 | INTEGRATED CIRCUIT INCLUDING FLASH MEMORY AND CMOS LOGIC CIRCUITRY | Final Rejection | TEXAS INSTRUMENTS INCORPORATED |
| 18433254 | IMAGE SENSING DEVICE INCLUDING SLOPED ISOLATION STRUCTURE | Non-Final OA | SK hynix Inc. |
| 18772224 | PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18646677 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF | Non-Final OA | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. |
| 18779047 | MOBILITY ENHANCEMENT BY SOURCE AND DRAIN STRESS LAYER OR IMPLANTATION IN THIN FILM TRANSISTORS | Non-Final OA | Taiwan Semiconductor Manufacturing Company Limited |
| 18641473 | BONDING SCHEME TO PROVIDE IMPROVED COPLANARITY AND HIGH JOINT YIELDS WITH REDUCED COSTS AND METHODS FOR FORMING THE SAME | Non-Final OA | Taiwan Semiconductor Manufacturing Company Limited |
| 18401902 | HYBRID SEMICONDUCTOR WAFER AND METHOD OF FORMING | Non-Final OA | Microchip Technology Incorporated |
| 18386383 | Power Semiconductor Module Arrangement | Final Rejection | Infineon Technologies AG |
| 18675527 | LASER TRANSFER STRUCTURE AND LASER TRANSFER METHOD | Non-Final OA | Lextar Electronics Corporation |
| 18666844 | POWER CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF | Non-Final OA | TONG HSING ELECTRONIC INDUSTRIES, LTD. |
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