Prosecution Insights
Last updated: April 19, 2026
Application No. 16/824,298

OPERATION METHOD, APPARATUS AND RELATED PRODUCT

Final Rejection §103
Filed
Mar 19, 2020
Examiner
DOMAN, SHAWN
Art Unit
2183
Tech Center
2100 — Computer Architecture & Software
Assignee
Cambricon Technologies Corporation Limited
OA Round
10 (Final)
66%
Grant Probability
Favorable
11-12
OA Rounds
2y 9m
To Grant
90%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allow Rate
183 granted / 275 resolved
+11.5% vs TC avg
Strong +23% interview lift
Without
With
+23.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
47 currently pending
Career history
322
Total Applications
across all art units

Statute-Specific Performance

§101
2.8%
-37.2% vs TC avg
§103
47.2%
+7.2% vs TC avg
§102
18.0%
-22.0% vs TC avg
§112
26.3%
-13.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 275 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-3, 6-8, and 12 have been amended. Claims 1-3, 5-10, 12, and 13 have been examined. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 5-10, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2017/0161611 by Ito (hereinafter referred to as “Ito”) in view of US Publication No. 2021/0049463 by Ruff (hereinafter referred to as “Ruff”) in view of US Patent 10,354,733 by Zejda et al. (hereinafter referred to as “Zejda”). Regarding claims 1 and 8, taking claim 1 as representative, Ito discloses: a method for processing multi- dimensional data… comprising: receiving input data formatted in …[multiple] dimensions, wherein the input data includes one or more values respectively at each of the …[multiple] dimensions; selecting two dimensions from the … [multiple] dimensions of the input data respectively as a first data dimension and a second data dimension based on at least a count of values at one of the first data dimension and the second data dimension that is smaller than a count of operation circuits of a processor (Ito discloses, at ¶ [0015], receiving an NxM matrix to an array having P processing elements. Ito also discloses, at ¶ [0015], determining that a matrix is “ill fitting,” which discloses selecting a first data dimension N and a second data dimension M based on a count. As disclosed at ¶ [0015], the data dimensions are N and M, which can be any integer, which discloses the case in which at least one of the dimensions is smaller than the count of operation circuits. ); determining a first dimension and a second dimension based on the selected first data dimension, the selected second data dimension and the count of the operation circuits of the processor, wherein a product of the first dimension and the second dimension is a multiple of the count of the operation circuits of the processor… (Ito discloses, at ¶ [0015], determining a new size for the matrix, which discloses a first dimension and second dimension, such that the matrix can be neatly divided into the array. Nnew mod P = 0, which discloses determining based on the count of the operation circuits of the processor and the product of dimensions will be a multiple of P, i.e., the count of the operation units.); wherein the first data dimension is a lowest dimension among dimensions of the input data, and the second data dimension is a second lowest dimension among the dimensions of the input data, and wherein the second lowest dimension is a dimension that is higher than the lowest dimension (Ito discloses, at ¶ [0015], that the dimensions of the input data are NxM, where N and M can be any integer values, which discloses the first data dimension and the second data dimension being the lowest and second lowest dimensions, respectively.); and ...[modifying] at one of the [multiple]…dimensions of the input data according to a relationship between the first dimension and the lowest dimension, and a relationship between the second dimension and the second lowest dimension (Ito discloses, at ¶ [0019], that the new matrix is used to produce a result equivalent to the original, which discloses performing completion processing according to relationships between the dimensions.). Ito does not explicitly disclose a neural network, the aforementioned multiple dimensions include at least three dimensions, one of the first dimension and the second dimension which is smaller than the count of the operation circuits of the processor is a divisor of the count of the operation circuits of the processor, and supplementing additional zero values at one of the at least three dimensions of the input data according to a relationship between the first dimension and the lowest dimension, and a relationship between the second dimension and the second lowest dimension. However, in the same field of endeavor (e.g., multi-dimensional data processing) Ruff discloses: a neural network (Ruff discloses, at ¶ [0009], a neural network); the aforementioned multiple dimensions include at least three dimensions (Ruff discloses, at ¶ [0009], input data having at least three dimensions); and supplementing additional zero values (Ruff discloses, at ¶ [0011], zero padding, which discloses supplementing additional zero values at one of the dimensions of the input data according to a relationship between the first dimension and the lowest dimension, and a relationship between the second dimension and the second lowest dimension.). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Ito to include three dimensional data and zero padding, as disclosed by Ruff, because three dimensional data is commonplace and zero padding allows for same sized input and outputs. Ruff, ¶ [0001]. Also in the same field of endeavor (e.g., multi-dimensional data processing) Zejda discloses: wherein at least a count of values at one of the first data dimension and the second data dimension is smaller than the count of operation circuits of the processor and is a divisor of the count of the operation circuits of the processor (Zejda discloses, at col. 12, lines 23-38, matrices having row and column dimensions of 2 being executed in a compute array having 32 rows and 64 columns. 2 is a divisor of 2048 (32*64).). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Ito to include the particular dimensions disclosed by Zejda because Ito is intended to solve problems of arbitrary size. Ito focuses more closely on scenarios where the input matrix is partitioned into a size where one dimension matches the number of PEs, but the greater the variety of sizes, as disclosed by Zejda, serves to increase the flexibility, and therefore usefulness, of Ito. Regarding claims 2 and 9, taking claim 2 as representative, Ito, as modified, discloses the elements of claim 1, as discussed above. Ito also discloses: wherein the determining of the first dimension and the second dimension based on the selected first data dimension, the selected second data dimension, and the count of the operation units includes: determining the first dimension according to a smaller one of the first data dimension and the second data dimension, and the count of the operation circuits, where the first dimension is a divisor of the count of the operation units, and the first dimension is greater than or equal to the smaller one of the first data dimension and the second data dimension (Ito discloses, at ¶ [0015], that the dimensions of the input data are NxM, where N and M can be any integer values, which discloses the first dimension being based on the smaller dimension and being a divisor of the count P of operation units. See also ¶ [0005], which gives an example where N is smaller than M.), and determining the second dimension according to a larger one of the first data dimension and the second data dimension, and the count of the operation units, where the second dimension is greater than or equal to the larger one of the first data dimension and the second data dimension (Ito discloses, at ¶ [0015], that the dimensions of the input data are NxM, where N and M can be any integer values, which discloses the second dimension being based on the larger dimension. See also ¶ [0005], which gives an example where M is smaller than equal to the second data dimension.). Regarding claims 3 and 10, taking claim 3 as representative, Ito, as modified, discloses the elements of claim 1, as discussed above. Ito also discloses: wherein the determining of the first dimension and the second dimension based on the selected first data dimension, the second data dimension, and the count of the operation units further includes: determining the first dimension according to the lowest dimension and the count of the operation units, wherein the first dimension is greater than or equal to the lowest dimension, and wherein the first dimension is the divisor of the count of the operation units (Ito discloses, at ¶ [0015], that the dimensions of the input data are NxM, which discloses N is greater than or equal to the lowest dimension.); and determining the second dimension according to the first dimension, the count of the operation units, and the second lowest dimension, wherein the second dimension is greater than or equal to the second lowest dimension (Ito discloses, at ¶ [0015], that the dimensions of the input data are NxM, where M is greater than or equal to the second lowest dimension.). Regarding claims 5 and 12, taking claim 5 as representative, Ito, as modified, discloses the elements of claim 3, as discussed above. Ito also discloses: wherein the first dimension is a smallest divisor of the count of the operation units, wherein the smallest divisor is greater than or equal to the lowest dimension; and the second dimension is greater than or equal to the second lowest dimension, and the product of the second dimension and the first dimension is a smallest multiple of the count of the operation units (Ito discloses, at ¶ [0015], that the dimensions of the input data are NxM, where N and M can be any integer values, which discloses the particular example claimed.). Regarding claims 6 and 13, taking claim 6 as representative, Ito, as modified, discloses the elements of claim 1, as discussed above. Ito also discloses: wherein the...[updating] according to the relationship between the first dimension and the lowest dimension, and the relationship between the second dimension and the second lowest dimension includes: when the first dimension is greater than the lowest dimension, completing the input data to the first dimension in a direction of the lowest dimension, and when the second dimension is greater than the second lowest dimension, completing the input data to the second dimension in a direction of the second lowest dimension (Ito discloses, at ¶ [0019], that the new matrix is used to produce a result equivalent to the original, which discloses performing completion processing according to relationships between the dimensions, which discloses processing in the directions of the dimensions.). Ito does not explicitly disclose supplementing additional zero values. However, in the same field of endeavor (e.g., multi-dimensional data processing) Ruff discloses: supplementing additional zero values (Ruff discloses, at ¶ [0011], zero padding.). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Ito to include zero padding, as disclosed by Ruff, because zero padding allows for same sized input and outputs. Ruff, ¶ [0001]. Regarding claims 7, Ito, as modified, discloses the elements of claim 1, as discussed above. Ito also discloses: ...determining the first dimension and the second dimension according to the first data dimension and the second data dimension of the input data, and the count of the operation units, wherein the first dimension is the divisor of the count of the operation units, and the first dimension is greater than or equal to a dimension number of the first data dimension, the product of the first dimension and the second dimension is the multiple of the count of the operation units, and the second dimension is greater than or equal to a dimension number of the second data dimension (Ito discloses, at ¶ [0015], that the dimensions of the input data are NxM, where N and M can be any integer values, which discloses that the product of the dimensions is a multiple of the count of operation units and the particular example claimed.), and ...[updating] according to the first dimension, the second dimension, the first data dimension, and the second data dimension (Ito discloses, at ¶ [0019], that the new matrix is used to produce a result equivalent to the original, which discloses performing completion processing.), wherein the first data dimension is a dimension where the input data is read and written firstly, and the second data dimension is a dimension where the input data is read and written secondly (Ito discloses, at ¶ [0015], an NxM matrix, which discloses writing in a first and second dimension, firstly and secondly, respectively.). Ito does not explicitly disclose when the first data dimension of the input data is smaller than the count of the operation units of the processor and supplementing additional zero values. However, in the same field of endeavor (e.g., multi-dimensional data processing) Ruff discloses: supplementing additional zero values (Ruff discloses, at ¶ [0011], zero padding.). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Ito to include zero padding, as disclosed by Ruff, because zero padding allows for same sized input and outputs. Ruff, ¶ [0001]. Also in the same field of endeavor (e.g., multi-dimensional data processing) Zejda discloses: when the first data dimension of the input data is smaller than the count of the operation units of the first processor (Zejda discloses, at col. 12, lines 23-38, matrices having row and column dimensions of 2 being executed in a compute array having 32 rows and 64 columns.); It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Ito to include the particular dimensions disclosed by Zejda because Ito is intended to solve problems of arbitrary size. Ito focuses more closely on scenarios where the input matrix is partitioned into a size where one dimension matches the number of PEs, but the greater the variety of sizes, as disclosed by Zejda, serves to increase the flexibility, and therefore usefulness, of Ito. Response to Arguments On page 9 of the response filed January 6, 2026 (“response”), the Applicant identifies several paragraph numbers at which support for the amendments is purportedly found. The Examiner thanks the Applicant for pointing to support for amendments. However, the specification as originally filed does not include paragraph numbers. The Examiner interprets the Applicant’s remarks as referring to the printed publication rather than the specification as originally filed. The paragraphs mentioned by the Applicant do not include the language “based on.” Nor does the remainder of the specification. Therefore, the Examiner interprets the term by giving the term the broadest reasonable interpretation not inconsistent with the specification. The specification indicates that the selection is “according to” the count, which is interpreted to mean generally involves the count. On page 11 of the response the Applicant argues “Ito describes refactoring an input matrix to neatly divide the input matrix into an integer number of the size of a systolic array. Hence, Ito merely describes a new matrix NNEwXM, where NNEwmod P=0 and N<NNEw<N+P for neatly dividing the new matrix into the systolic array. However, Ito does not teach or suggest selecting two dimensions from the at least three dimensions of the input data respectively as a first data dimension and a second data dimension based on at least a count of values at one of the first data dimension and the second data dimension that is smaller than a count of operation circuits of the processor.” Though fully considered, the Examiner respectfully disagrees. As previously discussed, selecting the data of the matrix discloses selecting dimensions of the matrix. Furthermore, Ito’s disclosure of an MxN matrix encompasses dimensions having any integer count of values greater than or equal to one. Ito also uses the variable P to represent the number of processing elements, i.e., operation circuits. It is evident that the dimension M, for example, can be one, or two, etc., while P can be 4 or 8, etc. This discloses the case where at least one of the dimensions has fewer values than there are processing elements. Accordingly, the Applicant’s arguments are deemed unpersuasive. On page 12 of the response the Applicant argues, “Zejda describes a computing array containing 32 rows and 64 columns of compute elements, and an alignment unit of 16 along the K dimension. Zejda further describes multiplication of tiling parameters MH=2, NW=3, and KD=5 that results in buffer matrices, where the buffer matrices match the number of compute elements. Hence, Zejda merely describes matrix multiplication operations to form the buffer matrices using the computing array. However, Zejda does not teach or suggest a count of values at one of the first data dimension and the second data dimension is smaller than a count of operation circuits of a processor. Therefore, Zejda can not teach or suggest selecting two dimensions from the at least three dimensions of the input data respectively as a first data dimension and a second data dimension based on at least a count of values at one of the first data dimension and the second data dimension that is smaller than a count of operation circuits of a processor.” Though fully considered, the Examiner respectfully disagrees. As discussed above, Ito teaches these features. Accordingly, the Applicant’s arguments are deemed unpersuasive. On pages 12-13 of the response the Applicant argues, “Further, there is no motivation to combine the teachings of Ito and Zejda. Ito focuses on selection from a two-dimensional array, whereas Zejda deals with matrix multiplication partitioning. There is no teaching or suggestion in the prior art to combine these references to achieve the claimed method of selecting two dimensions from the at least three dimensions of the input data respectively as a first data dimension and a second data dimension based on at least a count of values at one of the first data dimension and the second data dimension is smaller than a count of operation circuits of the processor.” Though fully considered, the Examiner respectfully disagrees. The Examiner submits that Ito, Ruff, and Zejda are directed to efficiency in matrix operations. Ito addresses the performance detriments that result when the size of the matrix doesn’t match the size of the array of PEs. See, e.g, ¶ [0004]. Ruff likewise addresses inefficiencies that result from different dimension sizes. See, e.g., ¶ [0001]. Zejda is also directed to partitioning matrices, which depends on dimension sizes, to improve efficiency. See, e.g., Figure 9 and related description. Accordingly, the Applicant’s arguments are deemed unpersuasive. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAWN DOMAN/ Primary Examiner, Art Unit 2183
Read full office action

Prosecution Timeline

Mar 19, 2020
Application Filed
Mar 12, 2021
Non-Final Rejection — §103
Sep 07, 2021
Response Filed
Sep 27, 2021
Final Rejection — §103
Mar 22, 2022
Request for Continued Examination
Mar 27, 2022
Response after Non-Final Action
Jul 19, 2022
Non-Final Rejection — §103
Jan 16, 2023
Response Filed
Jan 26, 2023
Final Rejection — §103
Jul 31, 2023
Request for Continued Examination
Aug 02, 2023
Response after Non-Final Action
Aug 11, 2023
Non-Final Rejection — §103
Feb 08, 2024
Response Filed
Mar 08, 2024
Final Rejection — §103
Aug 30, 2024
Request for Continued Examination
Sep 04, 2024
Response after Non-Final Action
Sep 18, 2024
Non-Final Rejection — §103
Mar 17, 2025
Response Filed
Apr 18, 2025
Final Rejection — §103
Jun 18, 2025
Response after Non-Final Action
Jun 27, 2025
Request for Continued Examination
Jul 07, 2025
Response after Non-Final Action
Oct 08, 2025
Non-Final Rejection — §103
Jan 06, 2026
Response Filed
Jan 26, 2026
Final Rejection — §103 (current)

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Prosecution Projections

11-12
Expected OA Rounds
66%
Grant Probability
90%
With Interview (+23.4%)
2y 9m
Median Time to Grant
High
PTA Risk
Based on 275 resolved cases by this examiner. Grant probability derived from career allow rate.

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