Prosecution Insights
Prosecution Insights
Tech Center 2100 • Art Units: 2182 2183
This examiner grants 65% of resolved cases
Shawn Doman is an examiner in Tech Center 2100 and Art Unit 2182. He has 285 resolved cases. The allowance rate is 64.9%. This 64.9% rate reflects the frequency of grants among the 285 cases. Practitioners can use this 64.9% figure to estimate the probability of a successful outcome for their applications.
The median days to allowance is 1106. This 1106-day period is the time from filing to the issuance of a patent. A median of 1106 days serves as a timeline for applicants to consider when their cases are assigned to this examiner. The 1106-day duration is a key metric for budgeting and project management during the prosecution process in Tech Center 2100.
The interview lift is 26.6%. This 26.6% lift shows a substantial increase in the allowance rate when an interview is conducted. A 26.6% lift suggests that direct communication with the examiner is an effective tactic. Practitioners should use this 26.6% figure to justify scheduling an interview to resolve pending rejections and improve the 64.9% base allowance rate.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 17686404 | SYSTEMS, METHODS, AND APPARATUS FOR COORDINATING COMPUTATION SYSTEMS | Non-Final OA | Samsung Electronics Co., Ltd. |
| 19097503 | Operation Fusion for Instructions Bridging Execution Unit Types | Non-Final OA | Apple Inc. |
| 18626929 | Hierarchical Trace Cache | Final Rejection | Apple Inc. |
| 18350907 | Combining Multiple Tensors into a Single Tensor Using Multiple Processors | Non-Final OA | Huawei Technologies Co., Ltd. |
| 19211409 | PERFORMING FUSED SHIFT AND LOGICAL OPERATIONS IN PROCESSOR-BASED DEVICES | Non-Final OA | QUALCOMM Incorporated |
| 18761887 | MEMORY PREFETCH MECHANISM BASED ON INSTRUCTION SETS | Final Rejection | QUALCOMM Incorporated |
| 18594899 | FETCHING BEYOND PREDICTED-TAKEN BRANCH INSTRUCTIONS IN FETCH BUNDLES OF PROCESSOR-BASED DEVICES | Final Rejection | QUALCOMM Incorporated |
| 18967172 | ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY | Non-Final OA | Intel Corporation |
| 18091606 | INSTRUCTIONS AND SUPPORT FOR STACK PUSH AND POP | Final Rejection | Intel Corporation |
| 18091599 | PREFIX EXTENSIONS FOR EXTENDED GENERAL PURPOSE REGISTERS WITH OPTIMIZATION FEATURES FOR NON-DESTRUCTIVE DESTINATIONS AND FLAGS SUPPRESSION | Final Rejection | INTEL CORPORATION |
| 18090749 | OPTIMIZING CONCURRENT EXECUTION USING NETWORKED PROCESSING UNITS | Final Rejection | Intel Corporation |
| 17958369 | 8-BIT FLOATING POINT FUSED MULTIPLY INSTRUCTIONS | Final Rejection | Intel Corporation |
| 17712139 | VARIABLE-LENGTH INSTRUCTION STEERING TO INSTRUCTION DECODE CLUSTERS | Final Rejection | Intel Corporation |
| 18210202 | PERFORMING CONCURRENT OPERATIONS IN A PROCESSING ELEMENT | Final Rejection | Amazon Technologies, Inc. |
| 18790951 | INSTRUCTION EXECUTION USING EXPANDED REGISTER CONTENTS | Final Rejection | INTERNATIONAL BUSINESS MACHINES CORPORATION |
| 19089853 | TASK EXECUTION METHOD FOR LARGE MODEL, ELECTRONIC DEVICE, AND STORAGE MEDIUM | Final Rejection | Beijing Baidu Netcom Science Technology Co., Ltd. |
| 19256267 | DATA PROCESSING APPARATUS HAVING STREAMING ENGINE WITH READ AND READ/ADVANCE OPERAND CODING | Non-Final OA | TEXAS INSTRUMENTS INCORPORATED |
| 19224400 | GENERALIZED ACCELERATION OF MATRIX MULTIPLY ACCUMULATE OPERATIONS | Non-Final OA | NVIDIA Corporation |
| 18325806 | CATEGORIZED MEMORY OPERATIONS FOR SELECTIVE MEMORY FLUSHING | Final Rejection | NVIDIA CORPORATION |
| 18414842 | Deep Learning Computation with Heterogeneous Accelerators | Final Rejection | Micron Technology, Inc. |
| 18475507 | SYSTEMS AND METHODS FOR RESYNCHRONIZATION AT EXECUTION TIME | Non-Final OA | Advanced Micro Devices, Inc. |
| 18475918 | METHOD AND APPARATUS FOR ENABLING MIMD-LIKE EXECUTION FLOW ON SIMD PROCESSING ARRAY SYSTEMS | Non-Final OA | Advanced Micro Devices, Inc. |
| 19032192 | RECONFIGURABLE DATAFLOW COMPUTING SYSTEMS WITH EFFICIENT SOFTMAX FUNCTIONS | Non-Final OA | SambaNova Systems, Inc. |
| 19053495 | COMPILER GENERATED HYPERBLOCKS IN A PARALLEL ARCHITECTURE WITH COMPUTE SLICES | Non-Final OA | Ascenium, Inc. |
| 17551276 | HIGHLY PARALLEL PROCESSING ARCHITECTURE USING DUAL BRANCH EXECUTION | Non-Final OA | Ascenium, Inc. |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy