DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
This office action is in response to the amendment filed on 11/21/25. Claims 33-37, 41-43, and 48 are pending.
Response to Amendment
Applicant's request for reconsideration of the finality of the rejection of the last Office action is persuasive and, therefore, the finality of that action is withdrawn.
The indication of allowability set forth in the previous action is withdrawn and prosecution is reopened in view of the following new ground of rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claim(s) 33-37, 41-43, and 48 is/are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by Lu et al. (US PGPub 2017/0047374, hereinafter referred to as “Lu”).
Lu discloses the semiconductor device as claimed. See figures 1-14, with emphasis in figure 12, and corresponding text, where Lu teaches, claim 33, a semiconductor device, comprising:
a semiconductor substrate (101, 102) having a first substrate surface and a second substrate surface;
a dielectric (105, 138, 162) on the semiconductor substrate (101), the dielectric having a first dielectric surface and a second dielectric surface, wherein the second dielectric surface is in contact with the first substrate surface;
a depression (1270) formed in the dielectric, the depression extending from the first dielectric surface to the second dielectric surface;
an aperture (168) extending through the dielectric (105, 138, 162) and at least a portion of the semiconductor substrate; and
a conductive material (164) having a first portion at least partially filling the depression (1270) and forming a trace (164), a second portion at least partially filling the aperture (168), and a third portion (portion between (1270) and (168))positioned within the dielectric (105, 138, 162) and laterally between the first portion and the second portion, wherein a lower surface of the third portion is in contact with the first substrate surface, wherein the first and second portion are electrically coupled by the third portion, and wherein the first, second, and third portions of the conductive material are generally contiguous (figure 12; [0062-0064]).
Lu teaches, claim 34, wherein the aperture has a first open end at the first dielectric surface and a second open end at the second substrate surface, and wherein a first cross-sectional area of the aperture at the first open end is generally the same as a second cross-sectional area of the aperture at the second open end (figure 12; [0062-0064]).
Lu teaches, claim 35, further comprising:
a first passivation layer (222) on the first dielectric surface, wherein the first passivation layer has a first opening generally corresponding to the first open end; and
a second passivation layer (222) on the second substrate surface, wherein the second passivation layer has a second opening generally corresponding to the second open end ([0044]).
Lu teaches, claim 36, further comprising:
a first interconnect component attached to a first surface of the conductive material exposed in the first opening; and
a second interconnect component attached to a second surface of the conductive material exposed in the second opening (figure 12; [0062-0064]).
Lu teaches, claim 37, wherein the first and third portions of the conductive material are in direct contact, and wherein the second and third portions of the conductive material are in direct contact (figure 12; [0062-0064]).
Lu teaches, claim 41, wherein an upper surface of the first portion of the conductive material is coplanar with an upper surface of the second portion of the conductive material (figure 12; [0062-0064]).
Lu teaches, claim 42, wherein a lower surface of the first portion of the conductive material is in contact with the first substrate surface (figure 12; [0062-0064]).
Lu teaches, claim 43, further comprising a passivation material formed over the dielectric, wherein the passivation material covers an upper surface of the first portion and the third portion of the conductive material, and wherein the passivation material includes an opening corresponding to an upper surface of the second portion of the conductive material (figure 12; [0062-0064]).
Lu teaches, claim 48, wherein the conductive material has a planar upper surface across the first portion, the second portion, and the third portion (figure 12; [0062-0064]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 33-37, 41-43, and 48 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 January 6, 2026