DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed January 28, 2025 is acknowledged. New Claim 48 has been added. Claim 47 has been cancelled. Claims 1, 5, 10, 25, 37 and 46 have been amended. Claims 1-2, 5-7, 9-13, 18-19, 25, 29, 31, 34-35, 37, 39-41, 44, 46 and 48 are pending.
Action on merits of claims 1-2, 5-7, 9-13, 18-19, 25, 29, 31, 34-35, 37, 39-41, 44, 46 and 48 follows.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 5 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Amended Claim 5 recites the limitation " wherein the conductive first barrier layer (32/33) is configured to inhibit diffusion of metal therethrough" in lines 3-4. There is insufficient antecedent basis for this limitation in the claim.
Therefore claim 5 is indefinite.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2 and 41 are rejected under 35 U.S.C. 103 as being unpatentable over SAKANISHI et al. (US. Pub. No. 2012/0074472) of record, in view of SUEKAWA et al. (US. Pub. No. 20150243753).
With respect to claim 1, SAKANISHI teaches a semiconductor device substantially as claimed including:
a semiconductor layer structure (1e) comprising an active region and an inactive region, the active region comprising a plurality of unit cells and the inactive region comprising a gate pad (24) on the semiconductor layer structure (1e) and a gate bond pad (6) on and electrically connected to the gate pad (24) at a bottom portion of the gate bond pad (6) via a contact hole;
an isolation layer (32/37) between the gate pad (24) and the gate bond pad (6);
a conductive first barrier layer (25) between the gate pad (24) and the isolation layer (32/37), and between the gate pad (24) and the bottom portion of the gate bond pad (6); and
a conductive second barrier layer (20) directly on the conductive first barrier layer (25) between the gate bond pad (6) and the conductive first barrier layer (25),
wherein the conductive second barrier layer (20) is directly on a portion of the conductive first barrier layer (25) that comprises a metal barrier material. (See FIG. 7).
Thus, SAKANISHI is shown to teach all the features of the claim with the exception of explicitly disclosing the conductive second barrier layer that comprises metal nitride.
However, SUEKAWA teaches a semiconductor device including:
a conductive second barrier layer (9) is directly on a portion of the gate (6) that comprises metal nitride (TiN) material. (See FIG. 2A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the conductive second barrier layer of SAKANISHI that comprising metal nitride material as taught by SUEKAWA for the same intended purpose of suppressing diffusion of metal from gate bonding pad.
Further, it has been held to be within the general skill of a worker in the art to select a known material, i.e., metal nitride material, on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
With respect to claim 2, at least a portion of the isolation layer (32/37) of SAKANISHI is between the conductive first barrier layer (25) and the conductive second barrier layer (20), wherein the conductive second barrier layer (20) is on opposing sidewalls of the contact hole, and
wherein a thickness of the conductive first barrier layer (25) is in a range of 100 nm to 200 nm, which is within the claimed range of 0.5 to 500 nm.
With respect to claim 41, a width of the conductive first barrier layer (25) of SAKANISHI in a direction parallel to a top surface of the semiconductor layer structure is greater than a width of the conductive second barrier layer (20) in the direction.
Claims 5-7 and 46 are rejected under 35 U.S.C. 103 as being unpatentable over SAKANISHI ‘472 and SUEKAWA ‘753, as applied to claim 1 above and further in view of YAMAZAKI et al. (US. Patent No. 7,923,779) of record.
With respect to claim 5, SAKANISHI, in view of SUEKAWA, teaches the semiconductor device as described in claim 1 above including: the conductive first barrier layer (25), wherein the conductive first barrier layer (25) is configured to inhibit diffusion of metal therethrough.
Thus, SAKANISHI and SUEKAWA are shown to teach all the features of the claim with the exception of explicitly disclosing the conductive first barrier layer comprises titanium (Ti) and/or tantalum (Ta).
However, YAMAZAKI ‘779 teaches a semiconductor device including:
a conductive first barrier layer (114) between gate pad (111/112/113) and isolation layer (119), wherein the conductive first barrier layer (114) comprises titanium (Ti) and/or tantalum (Ta), and wherein the conductive first barrier layer (114) is configured to inhibit diffusion of metal therethrough. (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the conductive first barrier layer of SAKANISHI comprising Ti or Ta as taught by YAMAZAKI for the same intended purpose of providing barrier on the gate electrode.
With respect to claim 6, in view of YAMAZAKI, conductive first barrier layer (114) on top surface of gate pad (111/112/113) and wherein the conductive first barrier layer (114) is between isolation layer (119) and sidewall of the gate in direction parallel to a top surface of semiconductor layer structure (101). (See FIG. 1).
With respect to claim 7, the semiconductor device of SAKANISHI further comprises: a gate finger (31) on the active region and electrically connected to the gate bond pad (31); andIn re: Daniel Jenner Lichtenwalner et al.Application No. 16/863,642Filed: April 30, 2020
Page 3 of 10a conductive third barrier layer (32) on the gate finger (31),
wherein the conductive third barrier layer (32) is directly on a top surface of the gate finger (31), and in view of YAMAZAMKI, is between the isolation layer and a sidewall of the gate finger, in a direction parallel to a top surface of the semiconductor layer structure.
With respect to claim 46, in view of YAMAZAKI ‘779, the gate pad (111/112/113) comprises silicide material, and wherein the conductive first barrier layer (114) is directly on the gate pad. (See FIG. 1).
Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over SAKANISHI ‘472 and SUEKAWA ‘753 as applied to claim 1 above, and further in view of KUSUNOKI et al. (US. Pub. No. 2011/0140165) of record.
SAKANISHI teaches the semiconductor device as described in claim 1 above including:
a source contact (8) on the semiconductor layer structure;
a third barrier layer (20) on sidewalls and a bottom surface of the source contact;
and fourth barrier layer (25) between the semiconductor layer structure and the third barrier layer (20). (See FIG. 9).
Thus, NAKANISHI and SAKANISHI are shown to teach all the features of the claim with the exception of explicitly disclosing at least one bond wire on the gate bonding pad.
Note that, wire bonding on the gate bonding pad is well known in the art to provide signal to the semiconductor device.
However, KUSUNOKI teaches a semiconductor device including: at least one bond wire (40W) electrically connected to gate bond pad (40GP). (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of NAKANISHI and/or SAKANISHI further including at least one bond wire electrically connected to gate bond pad as taught by KUSUNOKI to provide signal to the gate bond pad.
Claims 10-13, 18-19, 25, 34, 44 and 48 are rejected under 35 U.S.C. 103 as being unpatentable over SAKANISHI ‘472, in view of MATOCHA et al. (US. Pub. No. 2015/0214164) of record and YAMAZAKI ‘779.
With respect to claim 10, SAKANISHI teaches a semiconductor device substantially as claimed including:
a semiconductor layer structure (1e) comprising an active region and an inactive region;
a gate pad (24) on the inactive region of the semiconductor layer structure;
a gate bond pad (6) on and electrically connected to the gate pad (24);
a conductive first barrier layer (20) between the gate pad (24) and a bottom portion of gate bond pad (6); and
a conductive second barrier layer (25) between the gate pad (24) and the conductive first barrier layer (20), the conductive second barrier layer (25) comprising a metal material,
wherein at least a portion of the conductive second barrier layer (25) extends on a sidewall of the gate pad (24) on the inactive region. (See FIG. 7).
Thus, SAKANISHI is shown to teach all the features of the claim with the exception of explicitly disclosing the conductive second barrier layer comprising a metal nitride material, and a portion the conductive second barrier layer extends along a sidewall of the gate pad toward the inactive region of the semiconductor layer structure.
However, MOTACHA ‘164 teaches a semiconductor device including:
a gate (132) on a semiconductor layer structure, and
a conductive second barrier layer (134) on the gate pad (132) and conductive first barrier layer (144), the conductive second barrier layer (134) comprising a metal nitride (TiN) material. (See FIGs. 6, 12).
Note that, the gate and the gate pad of the semiconductor device are well known in the art being formed at the same time and same process.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the conductive second barrier layer of SAKANISHI comprising the metal nitride material as taught by MATOCHA for the same intended purpose of providing the conductive barrier layer on gate pad.
Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
Moreover, YAMAZAKI ‘779 teaches the semiconductor device including:
a conductive second barrier layer (114) on gate pad (111/112/113),
wherein at least a portion of the conductive second barrier layer (114) extends along a sidewall of the gate pad (111/112/113) toward the inactive region of the semiconductor layer structure. (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the conductive second barrier layer of SAKANISHI extending along a sidewall of the gate pad toward the inactive region of the semiconductor layer structure as taught by YAMAZAKI ‘779 for the same intended purpose of providing the conductive barrier layer on gate pad.
With respect to claim 11, the conductive second barrier layer (25) of SAKANISHI has a width in a second direction that is parallel to a top surface of the semiconductor layer structure that exceeds that of a portion of the conductive first barrier layer (20) that is between the conductive second barrier layer (25) and the bottom portion of the gate bond pad (6), wherein the portion of the conductive first barrier layer (20) comprises a first thickness and a second thickness that is thinner than the first thickness in a first direction perpendicular to a top surface of the semiconductor layer structure, and
in view of YAMAZAKI, the portion of the conductive second barrier layer (114) extends along the sidewall of the gate pad in the first direction toward the inactive region.
With respect to claim 12, in view of YAMAZAKI ‘931, a thickness of the conductive second barrier layer (114) is substantially uniform along the width of the conductive second barrier layer in the second direction.
With respect to claim 13, the gate bond pad (6) of SAKANISHI is coupled to the gate pad (24) via a contact hole having opposing sidewalls,In re: Daniel Jenner Lichtenwalner et al.
Application No. 16/863,642Filed: April 30, 2020Page 4 of 10wherein a portion of the conductive first barrier layer (20) is on the opposing sidewalls of the contact hole, and
wherein a width of the conductive second barrier layer (25) in a direction that is parallel to a top surface of the semiconductor layer structure is greater than a width of the contact hole in the direction.
With respect to claim 18, a material of the conductive second barrier layer (25) of SAKANISHI is different from a material of the conductive first barrier layer (20).
With respect to claim 19, the semiconductor device of SAKANISHI, further comprises:
a gate finger (24) on the active region and electrically connected to the gate pad; and
a conductive third barrier layer (25) on the gate finger (24). (See FIG. 20).
With respect to claim 48, the gate pad (24) of SAKANISHI is on an upper surface of a field insulating layer (23), and wherein, in view of YAMAZAKI ‘931, the conductive second barrier layer (114) extends along the sidewall of the gate pad and is directly on the upper surface of the field insulating layer.
With respect to claim 25, SAKANISHI teaches a semiconductor device substantially as claimed, including:
a semiconductor layer structure;
a plurality of unit cell transistors (MOSFET) that are electrically connected in parallel, each unit cell transistor including a gate finger (24) that extends in a first direction on a top surface of the semiconductor layer structure, the gate fingers (24) spaced apart from each other along a second direction; and
a conductive auxiliary gate electrode barrier layer (25) comprising a first portion directly on an upper surface of each of the gate fingers (24),
wherein the conductive auxiliary gate electrode barrier layer (25) comprises meatal material that is adjacent to a portion of each of the gate fingers (24) comprising polysilicon. (See FIGs. 6 and 9).
Thus, SAKANISHI is shown to teach all the features of the claim with the exception of explicitly disclosing the conductive auxiliary gate electrode barrier layer comprising a second portion extending along opposing sidewalls of each gate fingers and comprising a metal nitride material.
However, YAMAZAKI ‘779 teaches a semiconductor device including:
a conductive auxiliary gate electrode barrier layer (114) comprising a first portion directly on an upper surface of each of the gate fingers (111/112/113) and a second portion extending along opposing sidewalls of each of the gate fingers toward the semiconductor layer structure,
wherein the second portion of the conductive auxiliary gate electrode barrier layer (114) comprises a metal material that is adjacent, in second direction, to a portion of each of the gate finger. (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the conductive auxiliary gate electrode barrier layer of SAKANISHI comprising the first portion directly on the upper surface of each of the gate fingers and a second portion extending along opposing sidewalls of each of the gate fingers toward the semiconductor layer structure as taught by YAMAZAKI ‘779 for the same intended purpose of providing the conductive auxiliary gate electrode barrier layer on gate fingers.
Moreover, given a finite number of materials and their compounds, it is obvious to try without undue experimentation.
Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
Further, MATOCHA teaches the semiconductor device including:
a conductive auxiliary gate electrode barrier layer (getter material) comprising a second portion extending along opposing sidewalls of each of the gate fingers (gate) toward the semiconductor layer structure,
wherein the second portion of the conductive auxiliary gate electrode barrier layer comprises metal nitride material that is adjacent, in second direction, to a portion of each of the gate fingers (gate) comprising polysilicon. (See FIGs. 5, 6).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the portion of the conductive auxiliary gate electrode barrier layer of SAKANISHI comprising the metal nitride material as taught by MATOCHA for the same intended purpose of providing the conductive barrier layer on gate fingers.
Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
With respect to claim 34, the semiconductor device of SAKANISHI and YAMAZAKI ‘931, further comprises:
a source contact (8) on the semiconductor layer structure;
a conductive source barrier layer (20) between the source contact (8) and the semiconductor layer structure; and
an isolation layer (30) on the gate finger (24), wherein the conductive auxiliary gate electrode barrier layer (25) is between the isolation layer (30) and the gate finger (24) in the second direction, and
wherein the isolation layer (30) is between the conductive auxiliary gate electrode barrier layer (25) and the conductive source barrier layer (20).
With respect to claim 44, in view of YAMAZAKI ‘931 or MATOCHA, each of the gate fingers has a respective thickness in a third direction perpendicular to the top surface of the semiconductor layer structure, and wherein the second portion of the conductive auxiliary gate electrode barrier layer (114) extends in the third direction along the opposing sidewalls of at least one of the gate fingers an entirety of the respective thickness thereof.
Claims 29, 31 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over SAKANISHI ‘472, MATOCHA ‘164 and YAMAZAKI ‘779, as applied to claim 25 above and further in view of TAKANO (US. Patent No. 9,093,310).
With respect to claim 29, SAKANISHI ‘472, in view of MATOCHA ‘164 and YAMAZAKI ’779, teaches the semiconductor device as described in claim 25 above including: the semiconductor layer structure comprises an inactive region and an active region,
wherein the active region comprises the plurality of unit cell transistors (MOSFET), and wherein the inactive region comprises:
a gate pad (24) on the semiconductor layer structure;
a gate bond pad (6) on and electrically connected to the gate pad (24);
an isolation layer (32) between the gate pad (24) and the gate bond pad (6); and
a conductive auxiliary gate pad barrier layer (25) between the gate pad (24) and the isolation layer (32), and
wherein a first one of the unit cell transistors is on a first side of the gate pad, and a second one of the unit cell transistors is on a side of the gate pad (24).
Thus, SAKANISHI ‘472, MATOCHA ‘164 and YAMAZAKI ’779 are shown to teach all the features of the claim with the exception of explicitly disclosing the first one of the unit cell transistors is on a first side a first side of the gate pad, and the second one of the unit cell transistors is on a second side of the gate pad opposite the first side.
However, TAKANO teaches a semiconductor device including:
a semiconductor layer structure comprises an inactive region (pad) and an active region (cell),
wherein the active region (cell) comprises the plurality of unit cell transistors, and wherein the inactive region (pad) comprises:
a gate pad (8) on the semiconductor layer structure;
a gate bond pad (11) on and electrically connected to the gate pad (8); and
an isolation layer between the gate pad (8) and the gate bond pad (11),
wherein a first one of the unit cell transistors is on a first side (left) of the gate pad, and a second one of the unit cell transistors is on a second side (right) of the gate pad (8) opposite the first side (left). (See FIG. 2).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first one and second one of the unit cell transistors of SAKANISHI on opposite sides of the gate pad as taught by TAKANO to improve avalanche capacity.
With respect to claim 31, the semiconductor device of SAKANISHI further comprises a conductive gate pad barrier layer (20) between the conductive auxiliary gate pad barrier layer (25) and the gate bond pad (6).
With respect to claim 35, the conductive auxiliary gate electrode barrier layer (25) and the conductive auxiliary gate pad barrier layer (25) of SAKANISHI comprises a same material, and
in view of YAMAZAKI, the second portion of the conductive auxiliary gate electrode barrier layer (114) is directly on the opposing sidewalls of each of the gate finger.
Claims 37 and 39-40 are rejected under 35 U.S.C. 103 as being unpatentable over MATOCHA et al. (US. Pub. No. 2015/0214164) of record, in view of KAMIBABA et al. (US. Pub. No. 2018/0294258) of record.
With respect to claim 37, As best understood by the Examiner, MATOCHA teaches a semiconductor device substantially as claimed including:
a semiconductor layer structure;
a source contact on the semiconductor layer structure;
a conductive first barrier layer (140) on sidewalls and a bottom surface of the source contact;
a conductive second barrier layer (136) between the semiconductor layer structure and the conductive first barrier layer (140), wherein the conductive second barrier layer (136) laterally extends beyond portions of the conductive first barrier layer (140) that are respectively on the sidewalls of the source contact, and wherein the conductive second barrier layer (136) comprises a metal material; and
an isolation layer (138) on the semiconductor layer structure, wherein at least a portion of the isolation layer (138) is on an upper surface of the conductive second barrier layer (136). (See FIG. 12).
Thus, MATOCHA is shown to teach all the features of the claim with the exception of explicitly disclosing the material for the conductive second barrier layer comprises a metal nitride.
However, KAMIBABA teaches a semiconductor device having a barrier layer (12) at an interface with a semiconductor substrate (1) for a purpose of reducing the contact resistance to the n+-type emitter layer (4). The barrier layer metal includes titanium nitride (metal nitride material) titanium carbide, or titanium silicide. (See ¶ [0068]).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the conductive second barrier layer of MATOCHA utilizing the metal nitride material as taught by KAMIBABA for the same intended purpose of reducing the contact resistance.
Moreover, given a finite number of materials and their compounds, it is obvious to try without undue experimentation.
Note that, KAMIBABA teaches that metal nitride material and metal silicide material can be used interchangeably.
Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
With respect to claim 39, the conductive second barrier layer (136) of MATOCHA is in contact with the conductive first barrier layer (140), and
wherein the portion of the isolation layer (138) is between the conductive second barrier layer (136) and the source contact (146).
With respect to claim 40, the portion of the isolation layer (138) of MATOCHI is between the conductive first barrier layer (140) and the conductive second barrier layer (136) in a direction perpendicular to a top surface of the semiconductor layer structure.
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANH D MAI/ Primary Examiner, Art Unit 2893
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