DETAILED ACTION
This Office Action is in response to RCE filed June 17, 2025.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4, 8, 9 and 11-17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention.
(1) Regarding claims 1 and 13, Applicants originally disclosed in paragraph [0028] of current application that “The second GaN layer 30 is provided on a surface of the first GaN layer 20”, that “The second GaN layer 30 is, for example, a P- type GaN single-crystalline layer and is a layer epitaxially grown on the surface of the first GaN layer 20”, that “The second GaN layer 30 is formed by doping of a P type impurity in the process of epitaxial growth”, that “Alternatively, the second GaN layer 30 may be formed by epitaxial growth of an intrinsic or a [sic] N type GaN layer, ion implantation of a P type impurity to a predetermined depth from the surface thereof, and heat treatment”, that “For example, the concentration of Mg in the second GaN layer 30 is 1×1017 cm-3”, that “The P type impurity is Mg (magnesium)”, and that “In the second GaN layer 30, the concentration of Mg as the P type impurity is higher than the concentration of Si as a [sic] N type impurity (emphasis added).” Applicants further originally disclosed in paragraph [0048] of current application that “Next, the manufacturing apparatus epitaxially grows the second GaN layer 30 on the first GaN layer 20 by a MOCVD method”, and that “The manufacturing apparatus dopes the second GaN layer 30 with Mg as a P type impurity in the process of epitaxially growing the second GaN layer 30” describing Fig. 2A of current application. However, Applicants did not originally disclose “a concentration of impurities of the second conductivity type in the second conductivity type second gallium nitride layer being higher than a concentration of impurities of the first conductivity type in the first conductivity type first gallium nitride layer” as recited on lines 11-13 of the amended claims 1 and 12, because (a) paragraph [0028] of current application discloses comparison of the concentrations of impurities of two opposite conductivity types inside the second GaN layer 30 or the second conductivity type second gallium nitride layer rather than comparison of the concentrations of impurities of two opposite conductivity types in the first and second GaN layer 20/30 or the first conductivity type first gallium nitride layer and the second conductivity type second gallium nitride layer, (b) it appears that Applicants misinterpreted the sentence “In the second GaN layer 30, the concentration of Mg as the P type impurity is higher than the concentration of Si as a N type impurity (emphasis added)” in paragraph [0028] of current application as disclosing “a concentration of impurities of the second conductivity type in the second conductivity type second gallium nitride layer being higher than a concentration of impurities of the first conductivity type in the first conductivity type first gallium nitride layer” when “the concentration of Si as a [sic] N type impurity” refers to “the concentration of Si as a [sic] N type impurity” of the second GaN layer 30 rather than of the first GaN layer 20 since the sentence directly follows the sentence “Alternatively, the second GaN layer 30 may be formed by epitaxial growth of an intrinsic or a [sic] N type GaN layer, ion implantation of a P type impurity to a predetermined depth from the surface thereof, and heat treatment (emphasis added)” in paragraph [0028] of current application, and (c) in other words, the term “an intrinsic or a [sic] N type GaN layer” should be an intrinsic or an N type GaN layer “provided on a surface of the first GaN layer 20”, and then the intrinsic or N type GaN layer is implanted with P type impurities, which has nothing to do with the first GaN layer 20.
(2) Further regarding claims 1 and 13, even if arguendo Applicants originally disclosed “a concentration of impurities of the second conductivity type in the second conductivity type second gallium nitride layer being higher than a concentration of impurities of the first conductivity type in the first conductivity type first gallium nitride layer” recited on lines 11-13 of the amended claims 1 and 12 for the impurities of the first conductivity type of Si and the impurities of the second conductivity type of Mg, Applicants did not originally disclose “a concentration of impurities of the second conductivity type in the second conductivity type second gallium nitride layer being higher than a concentration of impurities of the first conductivity type in the first conductivity type first gallium nitride layer” for any other combination(s) of the first and second conductivity type impurities. Therefore, the amended claims 1 and 13 fail to comply with the written description requirement, because the scope of the amended claims 1 and 13 are much broader than the original disclosure in that the amended claims 1 and 13 would read on, for example, impurities of the first conductivity type of Ge and/or Sn and impurities of the second conductivity type of Be and/or Zn, neither of which Applicants originally disclosed.
Claims 2-4, 8, 9, 11, 12, 14 and 16 depend on claim 1, and claims 15 and 17 depend on claim 13, and therefore, claims 2-4, 8, 9, 11, 12 and 14-17 also fail to comply with the written description requirement.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) Regarding claims 16 and 17, it is not clear what the “amorphous intermediate layers” recited on line 3 refer to, because (a) claims 1 and 13 from which claims 16 and 17 respectively depends recites “an intermediate layer” on line 19, (b) therefore, it is not clear whether the “amorphous intermediate layers” recited in claims 16 and 17 refer to “an intermediate layer” recited in claims 1 and 13, or the “amorphous intermediate layers” recited in claims 16 and 17 refer to intermediate layers in addition to “an intermediate layer”.
(2) Further regarding claims 16 and 17, it is not clear how “parts of the intermediate layer” can be “amorphized by ion implantation to be amorphous intermediate layers”, because (a) as discussed above, claims 1 and 13 already recite “an intermediate layer”, (b) therefore, the claimed invention of the nitride semiconductor device already comprises the intermediate layer in the completed device structure, and (c) therefore, the limitation cited above appears to suggest that the claimed invention of the nitride semiconductor device is further processed by the ion implantation, and (d) in this case, it is not clear whether the claimed invention of the nitride semiconductor device is an intermediate product, and the limitation cited above is directed to a further process on the intermediate product by ion implantation, which would be directed to an intended use of the claimed nitride semiconductor device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8, 9 and 11-17 are rejected under 35 U.S.C. 103 as being unpatentable over Sugimoto et al. (US 8,222,675) in view of Iso et al. (US 2017/0338112) and further in view of Kachi et al. (US 7,211,839)
Regarding claims 1, 11 and 12, Sugimoto et al. disclose a nitride semiconductor device (Fig. 3) comprising: a substrate (44) having a first main surface (top surface of 44) and a second main surface (bottom surface of 44) located on an opposite side of the first main surface; a gallium nitride-based semiconductor layer (composite layer of 46 and 48) (col. 12, lines 15-18) provided on a side of the first main surface of the substrate, the gallium nitride-based semiconductor layer includes a first gallium nitride layer (46) and a second conductivity type (p-type) second gallium nitride layer (48) provided on the first gallium nitride layer; the first gallium nitride layer inherently having a low-dislocation density, because (a) Applicants do not specifically claim how low the dislocation density should be for the first gallium nitride layer to be referred to as “a low-dislocation density” first gallium nitride layer, and (b) therefore, the first gallium nitride layer 46 inherently has a low-dislocation density in comparison to or lower than an arbitrarily high dislocation density, and a metal oxide semiconductor field effect transistor (MOSFET) having a channel region (48a) in the gallium nitride-based semiconductor layer, wherein the MOSFET includes: a gate insulating film (54) (col. 12, line 39) including silicon dioxide and provided above the gallium nitride-based semiconductor layer (composite layer of 46 and 48); an intermediate layer (55) (col. 12, line 40) arranged between the gallium nitride-based semiconductor layer and the gate insulating film, inherently having a band gap smaller than a band gap of the gate insulating film since a band gap of the AlN semiconductor 55 is smaller than a band gap of the SiO2 insulator 54, and inherently having a band offset with the gallium nitride-based semiconductor layer, because AlN is the material composition that Applicants originally disclosed for the intermediate layer to generate the claimed band offset; a gate electrode (58) (col. 12, line 38) provided on the gate insulating film; a first conductivity type source region (50a) (col. 12, lines 52-53) provided in the second gallium nitride layer of the gallium nitride-based semiconductor layer; and a source electrode (52) provided on the gallium nitride-based semiconductor layer and being in contact with the source region, and the intermediate layer is arranged at a position opposite to the gate electrode with respect to the gate insulating film, and the source electrode is in direct contact with the source region.
Sugimoto et al. differ from the claimed invention by not showing that the substrate is a gallium nitride-based semiconductor substrate and is a low-dislocation density free-standing substrate having a dislocation density of less than 1×107 cm-2, the gallium nitride-based semiconductor layer includes a first conductivity type first gallium nitride layer, wherein a concentration of impurities of the second conductivity type in the second conductivity type second gallium nitride layer is higher than a concentration of impurities of the first conductivity type in the first conductivity type first gallium nitride layer, and the intermediate layer has a thickness of 0.25 nm or more and 7 nm or less (claim 1), wherein the thickness of the intermediate layer is 0.8 nm (claim 11), and the thickness of the intermediate layer is 0.25 nm or more and 2 nm or less (claim 12).
Sugimoto et al. further disclose a gallium nitride-based semiconductor substrate (26 in Fig. 2) that is a free-standing substrate (col. 10, lines 5-8).
In addition, Iso et al. disclose as semiconductor device ([0135]), comprising a gallium nitride-based semiconductor substrate (Fig. 1) ([0038]) that is a low-dislocation free-standing substrate having a dislocation density of less than 1×107 cm-2 (Abstract), because (a) Applicants do not specifically claim whether or not the claimed low-dislocation free-standing substrate has a uniform dislocation density in the claimed range, and (b) as disclosed in Abstract of Iso et al., the freestanding GaN substrate disclosed by Iso et al. has “a low dislocation part having a dislocation density of less than 1×106 cm−2 on the gallium polar surface.”
Since both Sugimoto et al. and Iso et al. teach a nitride semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the substrate disclosed by Sugimoto et al. can be a gallium nitride-based semiconductor substrate that is a low-dislocation density free-standing substrate as disclosed by Sugimoto et al. and Iso et al., which has a dislocation density of less than 1×107 cm-2 as disclosed by Iso et al., because (a) as disclosed by Sugimoto et al. and Iso et al., a gallium-nitride based semiconductor substrate that is a free-standing substrate has been commonly employed in manufacturing a GaN-based semiconductor device, (b) more specifically, epitaxially growing a gallium-nitride based semiconductor layer on a gallium-nitride based semiconductor substrate has been commonly practiced since this process would reduce the defects in and thus would improve quality of the epitaxially grown gallium-nitride based semiconductor layer, which would improve quality of the semiconductor layers deposited on the epitaxially grown gallium-nitride based semiconductor layer, and (c) a low dislocation gallium nitride-based semiconductor substrate would allow forming a low dislocation gallium nitride-based semiconductor layer on top of it, which would further improve quality of the semiconductor layers deposited on the epitaxially grown gallium-nitride based semiconductor layer.
Further regarding claims 1, 11 and 12, Sugimoto et al. in view of Iso et al. differ from the claimed invention by not showing that the gallium nitride-based semiconductor layer includes a first conductivity type first gallium nitride layer, wherein a concentration of impurities of the second conductivity type in the second conductivity type second gallium nitride layer is higher than a concentration of impurities of the first conductivity type in the first conductivity type first gallium nitride layer, and the intermediate layer has a thickness of 0.25 nm or more and 7 nm or less (claim 1), wherein the thickness of the intermediate layer is 0.8 nm (claim 11), and the thickness of the intermediate layer is 0.25 nm or more and 2 nm or less (claim 12).
Sugimoto et al. further disclose a gallium nitride-based semiconductor layer (28 in Fig. 2) including a first conductivity type (n-type) first gallium nitride layer (GaN) (col. 10, lines 11-12).
In addition, Kachi et al. disclose a semiconductor device (Figs. 1, 5, 7-9 and 11), comprising a gallium nitride-based semiconductor layer (composite layer including 22 in Figs. 1 and 5, 54 in Figs. 7-9, and 154 in Fig. 11) including a first conductivity type (n-type) first gallium nitride layer (GaN).
Since both Sugimoto et al. and Kachi et al. teach a nitride semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the buffer layer 46 in Fig. 3 of Sugimoto et al. can include a first conductivity type or n-type such that the gallium nitride-based semiconductor layer, i.e. the composite layer of 46 and 48 in Fig. 3 of Sugimoto et al., can include a first conductivity type first gallium nitride layer as disclosed by Sugimoto et al. and Kachi et al., because (a) as disclosed by Sugimoto et al. and Kachi et al., an n-type GaN layer has been commonly formed on a sapphire substrate or a GaN substrate, (b) there are only two types of conductivity, i.e. n-type and p-type, and therefore, the buffer layer 46 in Fig. 3 of Sugimoto et al. would be either n-type or p-type unless all the intentionally introduced and unintentionally incorporated impurities present in the buffer layer 46 perfectly cancel each other, which would not be likely without one carefully counting and controlling all the intentionally introduced and unintentionally incorporated impurities present in the buffer layer 46, (c) nitrogen vacancies in a GaN-based semiconductor layer would act as n-type impurities, and thus even without introducing impurities into the buffer layer 46 in Fig. 3 of Sugimoto et al., the buffer layer 46 would be n-type with the creation of nitrogen vacancies to some degree, and (d) n-type impurities for a GaN-based semiconductor layer such as Si have been commonly observed in any reactor chamber for growing GaN-based semiconductor materials, and therefore, a GaN-based semiconductor layer commonly includes unintentionally introduced n-type impurities such as Si, rendering it n-type.
Still further regarding claims 1, 11 and 12, Sugimoto et al. in view of Iso et al. and further in view of Kachi et al. differ from the claimed invention by not showing that a concentration of impurities of the second conductivity type in the second conductivity type second gallium nitride layer is higher than a concentration of impurities of the first conductivity type in the first conductivity type first gallium nitride layer, the intermediate layer has a thickness of 0.25 nm or more and 7 nm or less (claim 1), wherein the thickness of the intermediate layer is 0.8 nm (claim 11), and the thickness of the intermediate layer is 0.25 nm or more and 2 nm or less (claim 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the intermediate layer, which is an AlN layer as Applicants originally disclosed, can have a thickness in the claimed ranges of 0.25 nm or more 7 nm or less, 0.8 nm, and 0.25 nm or more and 2 nm or less, because (a) as the semiconductor technology has advanced over time, the thickness of the intermediate layer, which is an AlN layer, has been shrunk to accommodate the overall shrinkage of the nitride semiconductor devices to reduce the manufacturing cost, (b) the thickness of the intermediate layer should be controlled to optimize the insulating characteristics of the combined layer of the AlN layer and the SiO2 layer disclosed by Sugimoto et al. to optimize the dielectric constant, and to optimize the capacitance of the overall gate dielectric layer, and (c) the claims are prima facie obvious without showing that the claimed ranges of the intermediate layer thickness achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Still further regarding claim 1, Sugimoto et al. in view of Iso et al. and further in view of Kachi et al. differ from the claimed invention by not showing that a concentration of impurities of the second conductivity type in the second conductivity type second gallium nitride layer is higher than a concentration of impurities of the first conductivity type in the first conductivity type first gallium nitride layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a concentration of impurities of the second conductivity type in the second conductivity type second gallium nitride layer 48 of Sugimoto et al. can be higher than a concentration of impurities of the first conductivity type in the first conductivity type first gallium nitride layer 46 of Sugimoto et al., because (a) the first conductivity type first gallium nitride layer 46 of Sugimoto et al. is a buffer layer, and thus the concentration of impurities of the first conductivity type is not that critical for the first conductivity type first gallium nitride layer 46 to function as a buffer layer, and thus can be arbitrarily low, while the concentration of impurities of the second conductivity type in the second gallium nitride layer 48 of Sugimoto et al. should be controlled and optimized to achieve the desired function of the p-GaN layer 48 such as a channel layer, and (b) in addition, this relative concentrations of impurities would have been especially obvious to one of ordinary skill in the art when the impurities of the first conductivity type are introduced into the first gallium nitride layer as unwanted impurities or contaminants, while the impurities of the second conductivity type are introduced as designed or intended into the second gallium nitride layer.
Regarding claim 2, Sugimoto et al. further disclose that, when an electrical capacitance of the intermediate layer (55) is C2 and the band offset between the intermediate layer and the gallium nitride-based semiconductor layer is ΔE2, a relation of 1.6 x 10°/C2[F/cm2] < ΔE2[V] is satisfied, which is inherent because Sugimoto et al. in view of Iso et al. and further in view of Kachi et al. disclose the material compositions of the gallium nitride-based semiconductor layer of GaN and the intermediate layer of AlN disclosed by Applicants.
Regarding claim 3, Sugimoto et al. further disclose for the nitride semiconductor device according to claim 1 that the first conductivity type is a N type.
Sugimoto et al. in view of Iso et al. and further in view of Kachi et al. differ from the claimed invention by not showing that a threshold voltage of the MOSFET transistor is 3.0 V or more.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a threshold voltage of the MOSFET transistor can be in the claimed range, because (a) a threshold voltage of a field effect transistor is one of the most important device parameters, and thus should be controlled and optimized to clearly distinguish between on-state device characteristics and off-state device characteristics, and (b) the claim is prima facie obvious without showing that the claimed range of the threshold voltage achieves unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding claims 4, 8 and 9, Sugimoto et al. further disclose for the nitride semiconductor device according to claim 1 that the gallium nitride-based semiconductor layer (composite layer of 46 and 48) is composed of gallium nitride (claim 4), the intermediate layer (55) forms a heterojunction with the gallium nitride-based semiconductor layer (composite layer of 46 and 48) (claim 8), and the MOSFET further includes a first conductivity type drain region (50b) provided in the gallium nitride-based semiconductor layer (composite layer of 46 and 48), and a drain electrode (60) provided on the gallium nitride-based semiconductor layer and being in contact with the drain region, and the intermediate layer (55) is separated from a drain contact region in which the drain electrode is in contact with the drain region (claim 9).
Please refer to the explanations of the corresponding limitations above.
Regarding claim 13, Sugimoto et al. disclose a nitride semiconductor device (Fig. 3) comprising: a substrate (44) having a first main surface (top surface of 44) and a second main surface (bottom surface of 44) located on an opposite side of the first main surface; a gallium nitride-based semiconductor layer (composite layer of 46 and 48) provided on a side of the first main surface of the substrate, the gallium nitride-based semiconductor layer includes a first gallium nitride layer (46) and a second conductivity type (p-type) second gallium nitride layer (48) provided on the first gallium nitride layer, the first gallium nitride layer inherently having a low-dislocation density; and a metal oxide semiconductor field effect transistor (MOSFET) having a channel region (48a) in the gallium nitride-based semiconductor layer, wherein the MOSFET includes: a gate insulating film (54) including silicon dioxide and provided above the gallium nitride-based semiconductor layer; an intermediate layer (55) arranged between the gallium nitride-based semiconductor layer and the gate insulating film, inherently having a band gap smaller than a band gap of the gate insulating film, and inherently having a band offset with the gallium nitride-based semiconductor layer; a gate electrode (58) provided on the gate insulating film; a first conductivity type source region (50a) provided in the second gallium nitride layer of the gallium nitride-based semiconductor layer; and a source electrode (52) provided on the gallium nitride-based semiconductor layer and being in contact with the source region, and the intermediate layer is arranged at a position opposite to the gate electrode with respect to the gate insulating film and the source electrode is in direct contact with the source region.
Sugimoto et al. differ from the claimed invention by not showing that the substrate is a gallium nitride-based semiconductor substrate and is a low-dislocation density free-standing substrate having a dislocation density of less than 1×107 cm-2, the first gallium nitride layer is a first conductivity type first gallium nitride layer, a concentration of impurities of the second conductivity type in the second conductivity type second gallium nitride layer is higher than a concentration of impurities of the first conductivity type in the first conductivity type first gallium nitride layer, and the intermediate layer has a thickness of 0.25 nm or more and 2 nm or less.
Sugimoto et al. further disclose a gallium nitride-based semiconductor substrate (26 in Fig. 2) that is a free-standing substrate.
In addition, Iso et al. disclose as semiconductor device ([0135]), comprising a gallium nitride-based semiconductor substrate (Fig. 1) ([0038]) that is a low-dislocation free-standing substrate having a dislocation density of less than 1×107 cm-2 (Abstract), because (a) Applicants do not specifically claim whether or not the claimed low-dislocation free-standing substrate has a uniform dislocation density in the claimed range, and (b) as disclosed in Abstract of Iso et al., the freestanding GaN substrate disclosed by Iso et al. has “a low dislocation part having a dislocation density of less than 1×106 cm−2 on the gallium polar surface.”
Since both Sugimoto et al. and Iso et al. teach a nitride semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the substrate disclosed by Sugimoto et al. can be a gallium nitride-based semiconductor substrate that is a low-dislocation density free-standing substrate as disclosed by Sugimoto et al. and Iso et al., which has a dislocation density of less than 1×107 cm-2 as disclosed by Iso et al., because (a) as disclosed by Sugimoto et al. and Iso et al., a gallium-nitride based semiconductor substrate that is a free-standing substrate has been commonly employed in manufacturing a GaN-based semiconductor device, (b) more specifically, epitaxially growing a gallium-nitride based semiconductor layer on a gallium-nitride based semiconductor substrate has been commonly practiced since this process would reduce the defects in and thus would improve quality of the epitaxially grown gallium-nitride based semiconductor layer, which would improve quality of the semiconductor layers deposited on the epitaxially grown gallium-nitride based semiconductor layer, and (c) a low dislocation gallium nitride-based semiconductor substrate would allow forming a low dislocation gallium nitride-based semiconductor layer on top of it, which would further improve quality of the semiconductor layers deposited on the epitaxially grown gallium-nitride based semiconductor layer.
Further regarding claim 13, Sugimoto et al. in view of Iso et al. differ from the claimed invention by not showing that the gallium nitride-based semiconductor layer includes a first conductivity type first gallium nitride layer, a concentration of impurities of the second conductivity type in the second conductivity type second gallium nitride layer is higher than a concentration of impurities of the first conductivity type in the first conductivity type first gallium nitride layer, and the intermediate layer has a thickness of 0.25 nm or more and 2 nm or less.
Sugimoto et al. further disclose a gallium nitride-based semiconductor layer (28 in Fig. 2) including a first conductivity type (n-type) first gallium nitride layer (GaN) (col. 10, lines 11-12).
In addition, Kachi et al. disclose a semiconductor device (Figs. 1, 5, 7-9 and 11), comprising a gallium nitride-based semiconductor layer (composite layer including 22 in Figs. 1 and 5, 54 in Figs. 7-9 and 154 in Fig. 11) including a first conductivity type (n-type) first gallium nitride layer (GaN).
Since both Sugimoto et al. and Kachi et al. teach a nitride semiconductor device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the buffer layer 46 in Fig. 3 of Sugimoto et al. can include a first conductivity type or n-type such that the gallium nitride-based semiconductor layer, i.e. the composite layer of 46 and 48 of Sugimoto et al., can include a first conductivity type first gallium nitride layer as disclosed by Sugimoto et al. and Kachi et al., because (a) as disclosed by Sugimoto et al. and Kachi et al., an n-type GaN layer has been commonly formed on a sapphire substrate or a GaN substrate, (b) there are only two types of conductivity, i.e. n-type and p-type, and therefore, the buffer layer 46 in Fig. 3 of Sugimoto et al. would be either n-type or p-type unless all the intentionally introduced and unintentionally incorporated impurities present in the buffer layer 46 perfectly cancel each other, which would not be likely without one carefully counting and controlling all the intentionally introduced and unintentionally incorporated impurities present in the buffer layer 46, (c) nitrogen vacancies in a GaN-based semiconductor layer would act as n-type impurities, and thus even without introducing impurities into the buffer layer 46 in Fig. 3 of Sugimoto et al., the buffer layer 46 would be n-type with the generation of nitrogen vacancies, and (d) n-type impurities for a GaN-based semiconductor layer such as Si have been commonly observed in any reactor chamber for growing GaN-based semiconductor materials, and therefore, a GaN-based semiconductor layer commonly includes unintentionally introduced n-type impurities such as Si.
Still further regarding claim 13, Sugimoto et al. in view of Iso et al. and further in view of Kachi et al. differ from the claimed invention by not showing that a concentration of impurities of the second conductivity type in the second conductivity type second gallium nitride layer is higher than a concentration of impurities of the first conductivity type in the first conductivity type first gallium nitride layer, and the intermediate layer has a thickness of 0.25 nm or more and 2 nm or less.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the intermediate layer, which is an AlN layer as Applicants originally disclosed, can have a thickness in the claimed range of 0.25 nm or more and 2 nm or less, because (a) as the semiconductor technology has advanced over time, the thickness of the intermediate layer, which is an AlN layer, has been shrunk to accommodate the overall shrinkage of the nitride semiconductor devices to reduce the manufacturing cost, (b) the thickness of the intermediate layer should be controlled to optimize the insulating characteristics of the combined layer of the AlN layer and the SiO2 layer disclosed by Sugimoto et al. to optimize the dielectric constant, and to optimize the capacitance of the overall gate dielectric layer, and (c) the claim is prima facie obvious without showing that the claimed range of the intermediate layer thickness achieves unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Still further regarding claim 13, Sugimoto et al. in view of Iso et al. and further in view of Kachi et al. differ from the claimed invention by not showing that a concentration of impurities of the second conductivity type in the second conductivity type second gallium nitride layer is higher than a concentration of impurities of the first conductivity type in the first conductivity type first gallium nitride layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a concentration of impurities of the second conductivity type in the second conductivity type second gallium nitride layer 48 of Sugimoto et al. can be higher than a concentration of impurities of the first conductivity type in the first conductivity type first gallium nitride layer 46 of Sugimoto et al., because (a) the first conductivity type in the first conductivity type first gallium nitride layer 46 of Sugimoto et al. is a buffer layer, and thus the concentration of impurities of the first conductivity type is not that critical for the first conductivity type in the first conductivity type first gallium nitride layer 46 to function as a buffer layer, and thus can be arbitrarily low, while the concentration of impurities of the second conductivity type in the second conductivity type second gallium nitride layer 48 of Sugimoto et al. should be controlled and optimized to achieve the desired function of the p-GaN layer 48 such as a channel layer, and (b) in addition, this relative concentrations of impurities would have been especially obvious to one of ordinary skill in the art when the impurities of the first conductivity type are introduced into the first gallium nitride layer as unwanted impurities or contaminants, while the impurities of the second conductivity type are introduced as designed or intended into the second gallium nitride layer.
Regarding claims 14 and 15, Sugimoto et al. further disclose for the nitride semiconductor device according to claims 1 and 13 that a bottom surface of a part of the intermediate layer (55) is in direct contact with a top surface of the source region (50a) (claims 14 and 15).
Regarding claims 16 and 17, Sugimoto et al. in view of Iso et al. and further in view of Kachi et al. differ from the claimed invention by not showing that the part is amorphous structure, and wherein parts of the intermediate layer, which is a single crystalline layer, are amorphized by ion implantation to be amorphous intermediate layers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the part can be amorphous structure, because (a) Sugimoto et al. further disclose that “The high impurity concentration regions 50a and 50b are formed by injecting Si into the relevant parts of the nitride semiconductor layer 48” on lines 23-27 of column 12, which is (substantially) identical to what Applicants originally disclosed for forming the part 41 in Fig. 1 of current application, and (b) therefore, the part of the intermediate layer 55 in Fig. 3 of Sugimoto et al. whose bottom surface is in direct contact with the top surface of the source region 50a can also be amorphous structure since Sugimoto et al. disclose ion implantation for forming the source and drain region (substantially) identical to that disclosed by Applicants. The Examiner notes that the limitation “parts of the intermediate layer, which is a single crystalline layer, are amorphized by ion implantation to be amorphous intermediate layers” recited in claims 16 and 17 is not considered due to its indefiniteness as discussed above under 35 USC 112(b) rejection.
Response to Arguments
Applicants’ arguments with respect to claims 1 and 13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument, especially because of the new matter issues for the amended claims 1 and 13 discussed above under 35 USC 112(a) rejections.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sugimoto et al. (US 9,865,723)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached on (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 December 1, 2025