DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on Jul. 1st 2026 has been entered. Claims 1-20 remain pending in the application.
Claim Objections
Claim10 is objected to because of the following informalities:
In claim 10, line 2, “a vertical arrangement of horizontal semiconductor nanowires " should read “a first vertical arrangement of horizontal semiconductor nanowires”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bae et al. (US 20170179299) in view of Kong et al. (US 10714569), COQUAND et al. (US 20190198616) and Cheng et al. (US 20200027959).
Regarding claim 1, Bae teaches an integrated circuit structure (Abstract), comprising:
an insulator layer (fig. 3 and 7, planar insulating layer 110 as 210 without residual sacrificial layer 155; para. 0033, 0059) above a substrate (substrate 101; para. 0031);
a first vertical arrangement of horizontal semiconductor nanowires (nanosheets 120 with first and second nanosheets 121 and 122; para. 0038) over the insulator layer (110), and a second vertical arrangement of horizontal semiconductor nanowires (next 120 with 121, 122) over the insulator layer (110);
a first pair of epitaxial source or drain structures (source/ drain regions 104 and 105 using a selective epitaxial growth (SEG); para. 0055, 0077) at first and second ends of the first vertical arrangement of horizontal semiconductor nanowires (fig. 3, 104 and 105 at the left and right ends of 121 and 122) and on the insulator layer (110), and a second pair of epitaxial source or drain structures (next 104 and 105) at first and second ends of the second vertical arrangement of horizontal semiconductor nanowires (left and right ends of 121 and 122) and on the insulator layer (110); and
a first gate stack (gate electrode 130, gate insulating layer 135; para. 0026) surrounding a channel region (120 provide channel regions CH; para. 0038) of the first vertical arrangement of horizontal semiconductor nanowires (120), and a second gate stack (next 130, 135) surrounding a channel region (120 provide channel regions CH; para. 0038) of the second vertical arrangement of horizontal semiconductor nanowires (next 120), the first gate stack (130, 135) and the second gate (next 130, 135) comprising a high-k dielectric layer (gate insulating layer 135; para. 0026) continuous with and having a same composition as the insulator layer (planar insulating layer 110 may include a high dielectric constant material and the planar insulating layer 110 and the gate insulating layer 135 may be formed through a single manufacturing process; para. 0032, 0046);
a first gate spacer (spacers 140; para. 0026) along sides of the first gate stack (130, 135), and a second gate spacer (next 140) along sides of the second gate stack (next 130, 135).
Bae fails to explicitly teach the second vertical arrangement of horizontal semiconductor nanowires is next to the first vertical arrangement of horizontal semiconductor nanowires; the second pair of epitaxial source or drain structures having a conductivity type opposite the first pair of epitaxial source or drain structures.
However, Kong teaches the second vertical arrangement of horizontal semiconductor nanowires (Kong: fig. 17, nFET region 212; col. 10, lin. 3, similar to next 120 of Bae) is next to the first vertical arrangement of horizontal semiconductor nanowires (Kong: pFET region 210; col. 10, lin. 44, similar to 120 of Bae);
the second pair of epitaxial source or drain structures (Kong: fig. 17, source and drain 1006; col. 10, lin. 2, similar to next 104/105 of Bae) having a conductivity type (Kong: 1106 in pFET region 210 opposite to 1006 in the nFET region 212; col. 10, lin. 2-3, 43-44) opposite the first pair of epitaxial source or drain structures (Kong: source and drain 1106; col. 10, lin. 43, similar to 104/105 of Bae).
Kong and Bae are considered to be analogous to the claimed invention because they are in the same field of nanosheet devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the second pair of epitaxial source or drain structures having a conductivity type opposite the first pair of epitaxial source or drain structures as taught by Kong.
Doing so would realize a further scale down CMOS device with both NFET and PFET together for more function (Kong: col. 3, lin. 39-42). Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. (MPEP § 2144.04 VI. B.).
Bae in view of Kong fails to teach the first gate spacer vertically overlapping with the first pair of epitaxial source or drain structures, the second gate spacer vertically overlapping with the second pair of epitaxial source or drain structures.
However, COQUAND teaches the first gate spacer (COQUAND: fig. 12, external dielectric spacers 110; para. 0062, similar to top 140 of Bae) vertically overlapping with the first pair of epitaxial source or drain structures (COQUAND: electrically conductive portions 120 form part of the source and drain regions; para. 0070, similar to 104, 105 of Bae), the second gate spacer (COQUAND: next 110) vertically overlapping with the second pair of epitaxial source or drain structures (COQUAND: next 120).
COQUAND, Kong and Bae are considered to be analogous to the claimed invention because they are in the same field of nanosheet devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the gate spacer vertically overlapping with the pair of epitaxial source or drain structures as taught by COQUAND.
Doing so would realize contact surface area between the source and drain regions and the channel is greater to reduce the contact electrical resistance between the source and drain regions and the transistor channel (COQUAND: para. 0010).
In addition, Bae in view of Kong and COQUAND fails to teach the insulator layer extends laterally beyond outermost sides of the first pair of epitaxial source or drain structures and the second pair of epitaxial source or drain structures;
an isolation structure on a top surface of the insulator layer and laterally between and in direct contact with one of the first pair of epitaxial source or drain structures and one of the second pair of epitaxial source or drain structures, wherein the isolation structure is a single continuous isolation structure.
However, Cheng teaches the insulator layer (Cheng: fig. 14, buried oxide (BOX) layer 14 as insulator; para. 0047, similar to 210/110 of Bae) extends laterally beyond outermost sides of the first pair of epitaxial source or drain structures (Cheng: beyond outermost sides of source or drain region 28; para. 0055, similar to 104/105 of Bae) and the second pair of epitaxial source or drain structures (Cheng: next 28);
an isolation structure (Cheng: interlevel dielectric (ILD) 30; para. 0055) on a top surface of the insulator layer (Cheng: top surface of 14) and laterally between and in direct contact with one of the first pair of epitaxial source or drain structures (Cheng: 28) and one of the second pair of epitaxial source or drain structures (Cheng: next 28), wherein the isolation structure (Cheng: 30) is a single continuous isolation structure (Cheng: 30 is a single continuous isolation structure).
Cheng, COQUAND, Kong and Bae are considered to be analogous to the claimed invention because they are in the same field of nanosheet devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the detail of the insulator layer extends laterally beyond outermost sides of the pair of epitaxial source or drain structures and an isolation structure on the insulator layer as taught by Cheng.
Doing so would realize an interlevel dielectric structure to improve electrical isolation between S/D and substrate and improve lateral electrically isolate of adjacent S/D structures (Cheng: para. 0035).
Regarding claim 2, Bae in view of Kong, COQUAND and Cheng further teaches the integrated circuit structure of claim 1, wherein each of the first pair of epitaxial source or drain structures (Kong: fig. 17, 1106 in 210) has a compressed lattice (Kong: pFET region has a compressive strain; col. 4, lin. 16-17).
Regarding claim 3, Bae in view of Kong, COQUAND and Cheng further teaches the integrated circuit structure of claim 1, wherein each of the second pair of epitaxial source or drain structures (Kong: fig. 17, 1006 in 212) has an expanded lattice (Kong: nFET region has a tensile strain; col. 4, lin. 18-19).
Regarding claim 4, Bae in view of Kong, COQUAND and Cheng further teaches the integrated circuit structure of claim 1, wherein the insulator layer (Bae: fig. 5, 110) is on a sub-fin (Bae: sub-fin of 101), the sub-fin above or on the substrate (Bae: 101).
Regarding claim 5, Bae in view of Kong, COQUAND and Cheng further teaches the integrated circuit structure of claim 1, wherein each of the first vertical arrangement of horizontal semiconductor nanowires (Bae: fig. 3, 120) and second vertical arrangement of horizontal semiconductor nanowires (Bae: next 120) comprises silicon (Bae: nanosheets 120 may include Si; para. 0079).
Regarding claim 6, Bae in view of Kong, COQUAND and Cheng further teaches the integrated circuit structure of claim 1, wherein each of the first pair of epitaxial source or drain structures (Bae: fig. 3, 104, 105) and the second pair of epitaxial source or drain structures (Bae: next 104, 105) is a pair of non-discrete epitaxial source or drain structures (Bae: 104, 105 are non-discrete epitaxial source or drain continuous from the ends of each nanowires 120).
Regarding claim 7, Bae in view of Kong, COQUAND and Cheng further teaches the integrated circuit structure of claim 1, wherein each of the first gate stack (Bae: fig. 3, 130) and the second gate stack (Bae: next 130) comprises a metal gate electrode (Bae: gate electrode 130 may be formed of a metal; para. 0026).
Regarding claim 8, Bae in view of Kong, COQUAND and Cheng further teaches the integrated circuit structure of claim 1, wherein the semiconductor material of the second pair of epitaxial source or drain structures (Kong: fig. 17, 1006 in 212) is silicon (Kong: silicon; col. 10, lin. 23-24).
Regarding claim 9, Bae in view of Kong, COQUAND and Cheng further teaches the integrated circuit structure of claim 1, wherein the semiconductor material of the first pair of epitaxial source or drain structures (Kong: fig. 17, 1106 in 210) is silicon germanium (Kong: silicon germanium; col. 11, lin. 7-8).
Regarding claim 10, Bae teaches an integrated circuit structure (Abstract), comprising:
a vertical arrangement of horizontal semiconductor nanowires (fig. 3, nanosheets 120 with first and second nanosheets 121 and 122; para. 0038) and a second vertical arrangement of horizontal semiconductor nanowires (next 120 with 121, 122) above a substrate (substrate 101; para. 0031);
a first gate stack (gate electrode 130, gate insulating layer 135 and planar insulating layer 110; para. 0026, 0031) surrounding a channel region (120 provide channel regions CH; para. 0038) of the first vertical arrangement of horizontal semiconductor nanowires, and a second gate stack (next 130, 135) surrounding a channel region (120 provide channel regions CH; para. 0038) of the second vertical arrangement of horizontal semiconductor nanowires (next 120), the first gate stack (130, 135) and the second gate (next 130, 135) comprising a high-k dielectric layer (gate insulating layer 135 and planar insulating layer 110, planar insulating layer 110 may include a high dielectric constant material and the planar insulating layer 110 and the gate insulating layer 135 may be formed through a single manufacturing process; para. 0032, 0046; para. 0026) having a lowermost portion (fig. 3 and 7, planar insulating layer 110 or 210; para. 0059) extending laterally beyond first and second ends of the first vertical arrangement of horizontal semiconductor nanowires (fig. 3, 110 laterally beyond left and right ends of 120) and the second vertical arrangement of horizontal semiconductor nanowires (next 120); and
a first pair of epitaxial source or drain structures (source/ drain regions 104 and 105 using a selective epitaxial growth (SEG); para. 0055, 0077) at the first and second ends of the first vertical arrangement of horizontal semiconductor nanowires (fig. 3, 104 and 105 at the left and right ends of 121 and 122), and a second pair of epitaxial source or drain structures (next 104 and 105) at first and second ends of the second vertical arrangement of horizontal semiconductor nanowires (left and right ends of 121 and 122), the first pair of epitaxial source or drain structures (104/105) and the second pair of epitaxial source or drain structures (next 104/105) on the lowermost portion of the high-k dielectric layer (110) of the first gate stack (130, 135) and the second gate (next 130, 135);
a first gate spacer (spacers 140; para. 0026) along sides of the first gate stack (130, 135) and a second gate spacer (next 140) along sides of the second gate stack (next 130, 135).
Bae fails to explicitly teach the second vertical arrangement of horizontal semiconductor nanowires is next to the first vertical arrangement of horizontal semiconductor nanowires; the second pair of epitaxial source or drain structures having a conductivity type opposite the first pair of epitaxial source or drain structures.
However, Kong teaches the second vertical arrangement of horizontal semiconductor nanowires (Kong: fig. 17, nFET region 212; col. 10, lin. 3, similar to next 120 of Bae) is next to the first vertical arrangement of horizontal semiconductor nanowires (Kong: pFET region 210; col. 10, lin. 44, similar to 120 of Bae);
the second pair of epitaxial source or drain structures (Kong: fig. 17, source and drain 1006; col. 10, lin. 2, similar to next 104/105 of Bae) having a conductivity type (Kong: 1106 in pFET region 210 opposite to 1006 in the nFET region 212; col. 10, lin. 2-3, 43-44) opposite the first pair of epitaxial source or drain structures (Kong: source and drain 1106; col. 10, lin. 43, similar to 104/105 of Bae).
Kong and Bae are considered to be analogous to the claimed invention because they are in the same field of nanosheet devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the second pair of epitaxial source or drain structures having a conductivity type opposite the first pair of epitaxial source or drain structures as taught by Kong.
Doing so would realize a further scale down CMOS device with both NFET and PFET together for more function (Kong: col. 3, lin. 39-42). Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. (MPEP § 2144.04 VI. B.).
Bae in view of Kong fails to teach the first gate spacer vertically overlapping with the first pair of epitaxial source or drain structures, the second gate spacer vertically overlapping with the second pair of epitaxial source or drain structures.
However, COQUAND teaches the first gate spacer (COQUAND: fig. 12, external dielectric spacers 110; para. 0062, similar to top 140 of Bae) vertically overlapping with the first pair of epitaxial source or drain structures (COQUAND: electrically conductive portions 120 form part of the source and drain regions; para. 0070, similar to 104, 105 of Bae), the second gate spacer (COQUAND: next 110) vertically overlapping with the second pair of epitaxial source or drain structures (COQUAND: next 120).
COQUAND, Kong and Bae are considered to be analogous to the claimed invention because they are in the same field of nanosheet devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the gate spacer vertically overlapping with the pair of epitaxial source or drain structures as taught by COQUAND.
Doing so would realize contact surface area between the source and drain regions and the channel is greater to reduce the contact electrical resistance between the source and drain regions and the transistor channel (COQUAND: para. 0010).
In addition, Bae in view of Kong and COQUAND fails to teach the lowermost portion of the high-k dielectric layer of the first gate stack and the second gate stack extends laterally beyond outermost sides of the first pair of epitaxial source or drain structures and the second pair of epitaxial source or drain structures;
an isolation structure on a top surface of the high-k dielectric layer and laterally between and in direct contact with one of the first pair of epitaxial source or drain structures and one of the second pair of epitaxial source or drain structures, wherein the isolation structure is a single continuous isolation structure.
However, Cheng teaches the lowermost portion of the high-k dielectric layer of the first gate stack and the second gate stack (Cheng: fig. 14, buried oxide (BOX) layer 14 as insulator; para. 0047, similar to 210/110 of Bae) extends laterally beyond outermost sides of the first pair of epitaxial source or drain structures (Cheng: beyond outermost sides of source or drain region 28; para. 0055, similar to 104/105 of Bae) and the second pair of epitaxial source or drain structures (Cheng: next 28);
an isolation structure (Cheng: interlevel dielectric (ILD) 30; para. 0055) on a top surface of the high-k dielectric layer (Cheng: top surface of 14) and laterally between and in direct contact with one of the first pair of epitaxial source or drain structures (Cheng: 28) and one of the second pair of epitaxial source or drain structures (Cheng: next 28), wherein the isolation structure (Cheng: 30) is a single continuous isolation structure (Cheng: 30 is a single continuous isolation structure).
Cheng, COQUAND, Kong and Bae are considered to be analogous to the claimed invention because they are in the same field of nanosheet devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the detail of the insulator layer extends laterally beyond outermost sides of the pair of epitaxial source or drain structures and an isolation structure on the insulator layer as taught by Cheng.
Doing so would realize an interlevel dielectric structure to improve electrical isolation between S/D and substrate and improve lateral electrically isolate of adjacent S/D structures (Cheng: para. 0035).
Regarding claim 11, Bae in view of Kong, COQUAND and Cheng further teaches the integrated circuit structure of claim 10, wherein each of the first pair of epitaxial source or drain structures (Kong: fig. 17, 1106 in 210) has a compressed lattice (Kong: pFET region has a compressive strain; col. 4, lin. 16-17).
Regarding claim 12, Bae in view of Kong, COQUAND and Cheng further teaches the integrated circuit structure of claim 10, wherein each of the second pair of epitaxial source or drain structures (Kong: fig. 17, 1006 in 212) has an expanded lattice (Kong: nFET region has a tensile strain; col. 4, lin. 18-19).
Regarding claim 13, Bae in view of Kong, COQUAND and Cheng further teaches the integrated circuit structure of claim 10, wherein the insulator layer (Bae: fig. 5, 110) is on a sub-fin (Bae: sub-fin of 101), the sub-fin above or on the substrate (Bae: 101).
Regarding claim 14, Bae in view of Kong, COQUAND and Cheng further teaches the integrated circuit structure of claim 10, wherein each of the first vertical arrangement of horizontal semiconductor nanowires (Bae: fig. 3, 120) and the second vertical arrangement of horizontal semiconductor nanowires (Bae: next 120) comprises silicon (Bae: nanosheets 120 may include Si; para. 0079).
Regarding claim 15, Bae in view of Kong, COQUAND and Cheng further teaches the integrated circuit structure of claim 10, wherein each of the first pair of epitaxial source or drain structures (Bae: fig. 3, 104, 105) and the second pair of epitaxial source or drain structures (Bae: next 104, 105) is a pair of non-discrete epitaxial source or drain structures (Bae: 104, 105 are non-discrete epitaxial source or drain continuous from the ends of each nanowires 120).
Regarding claim 16, Bae teaches a computing device (fig. 56, electronic device 2000; para. 0102), comprising:
a board (fig. 56, dash lines indicate a board for units of electronic device 2000; para. 0102); and
a component (memory 2040 and processor 2050 may include one or more semiconductor devices; para. 0105) coupled to the board (2000), the component including an integrated circuit structure (semiconductor devices; Abstract), comprising:
an insulator layer (fig. 3 and 7, planar insulating layer 110 or 210 without residual sacrificial layer 155; para. 0033, 0059) above a substrate (substrate 100; para. 0067);
a first vertical arrangement of horizontal semiconductor nanowires (fig. 3, nanosheets 120 with first and second nanosheets 121 and 122; para. 0038) over the insulator layer (110), and a second vertical arrangement of horizontal semiconductor nanowires (next 120 with 121, 122) over the insulator layer (110);
a first pair of epitaxial source or drain structures (source/ drain regions 104 and 105 using a selective epitaxial growth (SEG); para. 0055, 0077) at first and second ends of the first vertical arrangement of horizontal semiconductor nanowires (fig. 3, 104 and 105 at the left and right ends of 121 and 122) and on the insulator layer (110), and a second pair of epitaxial source or drain structures (next 104 and 105) at first and second ends of the second vertical arrangement of horizontal semiconductor nanowires (left and right ends of 121 and 122) and on the insulator layer (110); and
a first gate stack (gate electrode 130, gate insulating layer 135; para. 0026) surrounding a channel region (120 provide channel regions CH; para. 0038) of the first vertical arrangement of horizontal semiconductor nanowires, and a second gate stack (next 130, 135) surrounding a channel region (120 provide channel regions CH; para. 0038) of the second vertical arrangement of horizontal semiconductor nanowires (next 120), the first gate stack (130, 135) and the second gate stack (next 130, 135) comprising a high-k dielectric layer (gate insulating layer 135; para. 0026) continuous with and having a same composition as the insulator layer (planar insulating layer 110 may include a high dielectric constant material and the planar insulating layer 110 and the gate insulating layer 135 may be formed through a single manufacturing process; para. 0032, 0046);
a first gate spacer (spacers 140; para. 0026) along sides of the first gate stack (130, 135), and a second gate spacer (next 140) along sides of the second gate stack (next 130, 135).
Bae fails to explicitly teach the second vertical arrangement of horizontal semiconductor nanowires is next to the first vertical arrangement of horizontal semiconductor nanowires; the second pair of epitaxial source or drain structures having a conductivity type opposite the first pair of epitaxial source or drain structures.
However, Kong teaches the second vertical arrangement of horizontal semiconductor nanowires (Kong: fig. 17, nFET region 212; col. 10, lin. 3, similar to next 120 of Bae) is next to the first vertical arrangement of horizontal semiconductor nanowires (Kong: pFET region 210; col. 10, lin. 44, similar to 120 of Bae);
the second pair of epitaxial source or drain structures (Kong: fig. 17, source and drain 1006; col. 10, lin. 2, similar to next 104/105 of Bae) having a conductivity type (Kong: 1106 in pFET region 210 opposite to 1006 in the nFET region 212; col. 10, lin. 2-3, 43-44) opposite the first pair of epitaxial source or drain structures (Kong: source and drain 1106; col. 10, lin. 43, similar to 104/105 of Bae).
Kong and Bae are considered to be analogous to the claimed invention because they are in the same field of nanosheet devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the second pair of epitaxial source or drain structures having a conductivity type opposite the first pair of epitaxial source or drain structures as taught by Kong.
Doing so would realize a further scale down CMOS device with both NFET and PFET together for more function (Kong: col. 3, lin. 39-42). Furthermore, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. (MPEP § 2144.04 VI. B.).
Bae in view of Kong fails to teach the first gate spacer vertically overlapping with the first pair of epitaxial source or drain structures, the second gate spacer vertically overlapping with the second pair of epitaxial source or drain structures.
However, COQUAND teaches the first gate spacer (COQUAND: fig. 12, external dielectric spacers 110; para. 0062, similar to top 140 of Bae) vertically overlapping with the first pair of epitaxial source or drain structures (COQUAND: electrically conductive portions 120 form part of the source and drain regions; para. 0070, similar to 104, 105 of Bae), the second gate spacer (COQUAND: next 110) vertically overlapping with the second pair of epitaxial source or drain structures (COQUAND: next 120).
COQUAND, Kong and Bae are considered to be analogous to the claimed invention because they are in the same field of nanosheet devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the gate spacer vertically overlapping with the pair of epitaxial source or drain structures as taught by COQUAND.
Doing so would realize contact surface area between the source and drain regions and the channel is greater to reduce the contact electrical resistance between the source and drain regions and the transistor channel (COQUAND: para. 0010).
In addition, Bae in view of Kong and COQUAND fails to teach the insulator layer extends laterally beyond outermost sides of the first pair of epitaxial source or drain structures and the second pair of epitaxial source or drain structures;
an isolation structure on a top surface of the insulator layer and laterally between and in direct contact with one of the first pair of epitaxial source or drain structures and one of the second pair of epitaxial source or drain structures, wherein the isolation structure is a single continuous isolation structure.
However, Cheng teaches the insulator layer (Cheng: fig. 14, buried oxide (BOX) layer 14 as insulator; para. 0047, similar to 210/110 of Bae) extends laterally beyond outermost sides of the first pair of epitaxial source or drain structures (Cheng: beyond outermost sides of source or drain region 28; para. 0055, similar to 104/105 of Bae) and the second pair of epitaxial source or drain structures (Cheng: next 28);
an isolation structure (Cheng: interlevel dielectric (ILD) 30; para. 0055) on a top surface of the insulator layer (Cheng: top surface of 14) and laterally between and in direct contact with one of the first pair of epitaxial source or drain structures (Cheng: 28) and one of the second pair of epitaxial source or drain structures (Cheng: next 28), wherein the isolation structure (Cheng: 30) is a single continuous isolation structure (Cheng: 30 is a single continuous isolation structure).
Cheng, COQUAND, Kong and Bae are considered to be analogous to the claimed invention because they are in the same field of nanosheet devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the detail of the insulator layer extends laterally beyond outermost sides of the pair of epitaxial source or drain structures and an isolation structure on the insulator layer as taught by Cheng.
Doing so would realize an interlevel dielectric structure to improve electrical isolation between S/D and substrate and improve lateral electrically isolate of adjacent S/D structures (Cheng: para. 0035).
Regarding claim 17, Bae in view of Kong, COQUAND and Cheng further teaches the computing device of claim 16, further comprising: a memory (Bae: fig. 56, memory 2040; para. 0102) coupled to the board (Bae: 2000).
Regarding claim 18, Bae in view of Kong, COQUAND and Cheng further teaches the computing device of claim 16, further comprising: a communication chip (Bae: fig. 56, communications unit 2010; para. 0102) coupled to the board (Bae: 2000).
Regarding claim 20, Bae in view of Kong, COQUAND and Cheng further teaches the computing device of claim 16, wherein the component (Bae: fig. 56, memory 2040 and processor 2050 may include one or more semiconductor devices; para. 0105) is selected from the group consisting of a processor (Bae: processor 2050; para. 0102), a communications chip (Bae: 2010), and a digital signal processor (Bae: output unit 2030 may output information in a form of audio or video; para. 0102).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Bae in view of Kong, COQUAND and Cheng as applied to claim 16 above, and further in view of Suh et al. (US 20170222006).
Regarding claim 19, Bae in view of Kong, COQUAND and Cheng teaches the computing device of claim 16 including the component (Bae: fig. 56, memory 2040 and processor 2050 may include one or more semiconductor devices; para. 0105).
Bae in view of Kong, COQUAND and Cheng fails to explicitly teach the component is a packaged integrated circuit die.
However, Suh teaches the component (Suh: fig. 34, DRAM 1060 and the application processor 1001; para. 0213, similar to 2040 and 2050 of Bae) is a packaged integrated circuit die (Suh: DRAM 1060 and the application processor 1001 may be packaged together in the form of a Package-on-Package; para. 0213).
Suh, Cheng, COQUAND, Kong, and Bae are considered to be analogous to the claimed invention because they are in the same field of nanosheet devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the detail of the component as a packaged integrated circuit die as taught by Suh.
Doing so would realize memory and processor be packaged together in the form of a Package-on-Package (POP), which allows higher component density in devices (Suh: para. 0213).
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
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