DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210057570 (Lin et al) in view of US 20200006545 (Liu et al), US 20210091078 (Lu et al), and US 20080230845 (Okonogi et al).
Concerning claim 1, Lin discloses an integrated circuit structure (Figs. 1 and 15B), comprising: a fin having a lower fin portion (52) and an upper fin portion (58); a gate stack (108) over the upper fin portion of the fin, the gate stack having a first side opposite a second side (Fig. 1); first and second dielectric gate sidewall spacers (76 +78) along the first and second sides of the gate stack, respectively ([0058]), a first source or drain structure (80, a combination of 80A+80B+80C) comprising an epitaxial structure embedded in the fin at the first side of the gate stack; a second source or drain structure (80) comprising an epitaxial structure embedded in the fin at the second side of the gate stack (Fig. 8), each of the epitaxial structures of the first and second source or drain structures comprising silicon, germanium and boron, the germanium having an atomic concentration of . . . 55% at a top surface of each of the epitaxial structures of the first and second source or drain structures ([0044]);. . . and a metal silicide layer (118) on and in direct contact with the top surface of each of the epitaxial structures of the first and second source or drain structures ([0065]).
Lin does not disclose that the epitaxial structure has a germanium having an atomic concentration of greater than 55% or a metal silicide layer in a recess in the top surface of each of the epitaxial structures of the first and second source or drain structures, a first trench contact structure over the first source or drain structure and a second trench contact structure over the second source or drain structure, each of the first and second trench contact structures comprising a respective U-shaped metal layer and a respective T-shaped metal layer on and over the entirety of the respective U-shaped metal layer , wherein all surfaces of the metal silicide layer are lower than corresponding upper surfaces of the first and second source or drain structures along lengths of the first and second source and drain structures. However, Liu discloses provide a high surface dopant concentration for epitaxial source/drain structures and thus improve device performance. Having a high concentration of germanium (e.g., 20 at. % or more) in the SiGe can introduce strain into the transistor channel, thereby increasing mobility of holes and channel drive current. In some embodiments, the epitaxial source/drain structures 292 can have at least a high Ge concentration region and a low Ge concentration region. In an embodiment shown in FIG. 3, the epitaxial source/drain structures 292 for p-type devices have a first region 213 at or proximate the top surface 215 of the epitaxial source/drain structures 292, and have a second region 217 disposed outward of and/or below the first region 213. In some examples, the first region 213 is Si.sub.1-xGe.sub.x and may have a concentration of Ge in a range from about 20 at. % to about 100 at. %, for example about 25 at. % to about 80 at. %, for example about 40 at. % to about 60 at. % ([0021]). Therefore one of ordinary skill in the art before the effective filing date of the invention would have found it obvious to have a germanium atomic concentration of greater than 55% in order to improve device performance as taught by Liu.
Additionally, Lu discloses a epitaxial source and drain configuration (Fig. 19B)
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in which an epitaxial source and drain region (20 +50P) ([0031] and [0065]) are formed in a substrate and embedded in a fin (14+12) ([0031]) structure with a silicide layer (55P) ([0076]-[0077]) formed such that all surfaces of the metal silicide layer are lower than corresponding upper surfaces of the first and second source or drain structures along lengths of the first and second source and drain structures. (Fig. 19B annotated above, note that the line shows the height of the epitaxial structure and that the height of the silicide layer is below the height of the line). Lu discloses that the lower S/D epitaxial layer and the upper S/D epitaxial layer contain Ge, and a concentration of Ge in the upper S/D epitaxial layer is higher than a concentration of Ge in the lower S/D epitaxial layer the lower S/D epitaxial layer 20P includes Si.sub.1-xGe.sub.x, where 0.15≤x≤0.8, and the upper S/D epitaxial layer 50P includes Si.sub.1-yGe.sub.y, where 0.2≤y≤1.0 and x<y. Further, at least one of the lower S/D epitaxial layer and the upper S/D epitaxial layer further contains B (boron), and a concentration of B is in a range from about 1.0×10.sup.20 cm.sup.−3 to about 6.0×10.sup.21 cm.sup.−3 in some embodiments, and is in a range from about 5.0×10.sup.20 cm.sup.−3 to about 1.0×10.sup.21 cm.sup.−3 in other embodiments ([0066]). Lu also discloses that such configuration provides a semiconductor device having reduced source/drain (S/D) contact resistance ([0002]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of Lin in view of Lu such that all surfaces of the metal silicide layer are lower than corresponding upper surfaces of the first and second source or drain structures along lengths of the first and second source and drain structures in order to provide a semiconductor device having reduced source/drain (S/D) contact resistance.
Also, Okonogi discloses an integrated circuit structure (Fig. 1) that includes trench contact structure (12A and 12B) formed over a source (9A) and drain (10). The first and second trench contact structures comprising a respective U-shaped layer (12a) and a respective T-shaped layer (12A) on and over the entirety of the respective U-shaped metal layer ([0093]). Lu discloses a trench contact structure that utilizes a barrier layer (62) and a plug layer (64) where the materials of these layers are disclosed as being metal (Fig. 1a and [0077]). In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.) See MPEP 2144.04 IV B. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of the trench contact structure of Lin with the configuration as disclosed by Okonogi utilizing the known suitable metal materials of Lu absent evidence that the claimed configuration was significant.
Concerning claim 7, Lin in view of Liu, Lu, and Okonogi discloses further comprising: a first conductive contact (Lin 116 left) on a first portion of the metal silicide layer on the epitaxial structure of the first source or drain structure (Lin Fig. 15B); and a second conductive contact (Lin 116) on a second portion of the metal silicide layer on the epitaxial structure of the second source or drain structure (Lin Fig. 15B).
Claim(s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210057570 (Lin et al) in view of US 20200006545 (Liu et al), US 20210091078 (Lu et al), and US 20080230845 (Okonogi et al) as applied to claim 1 above and further in view of US 20080067609 (Kim et al) and US 201300334693 (Alptekin et al).
Referring to claim 2, Lin in view of Liu, Lu, and Okonogi discloses the metal silicide layer is a silicide of a silicon germanium layer (Lin [0065]).
Lin in view of Liu, Lu, and Okonogi does not disclose the exact composition of the silicide layer and therefore does not disclose wherein the metal silicide layer is a silicide of a silicon germanium layer having a composition substantially the same as the composition of the each of the epitaxial structures at the top surface of each of the epitaxial structures.
Kim discloses a transistor structure that includes a raised source/drain region that includes a lower SiGe layer (117) and a capping SiGe layer (120) and a silicide layer (125) formed from a reaction with a metal layer and the capping SiGe layer (Fig. 9). Kim discloses that the germanium atomic content in the lower SiGe layer (117) is in the range of about 15%-90% ([0023]) and that the germanium content in the capping SiGe layer is about 5%-10% ([0041]). Additionally, Kim discloses that the germanium content of the silicide (germanosilicide) is equal or lower than that of the capping layer (120) ([0043]). Lin discloses a lower semiconductor layer (80B) with a high Ge content (about 55%) with a capping layer (80C) with a lower Ge content ([0050], note that the Ge content is 20%-22%) formed over it and a silicide formed from the capping layer. Alptekin discloses forming silicides with lower Ge concentration produce a more robust and thermally stable silicide contact ([0078]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the capping layer (120) of Kim with the lower Ge content (about 5% to about 10%) for the capping layer (80C) of Lin to form a silicide (germanosilicide as disclosed by Kim) that has a content equal to or lower than about 5% to about 10% in order to form a silicide with a lower germanium content that will be more robust and thermally stable as disclosed by Alptekin.
Referring to claim 3, Lin in view of Liu, Lu, and Okonogi discloses the metal silicide layer is a silicide of a silicon germanium layer (Lin [0065]).
Lin in view of Liu, Lu, and Okonogi does not disclose the exact composition of the silicide layer and therefore does not disclose wherein the metal silicide layer is a silicide of a silicon germanium layer having a composition with an atomic concentration of germanium of less than 10%.
Kim discloses a transistor structure that includes a raised source/drain region that includes a lower SiGe layer (117) and a capping SiGe layer (120) and a silicide layer (125) formed from a reaction with a metal layer and the capping SiGe layer (Fig. 9). Kim discloses that the germanium atomic content in the lower SiGe layer (117) is in the range of about 15%-90% ([0023]) and that the germanium content in the capping SiGe layer is about 5%-10% ([0041]). Additionally, Kim discloses that the germanium content of the silicide (germanosilicide) is equal or lower than that of the capping layer (120) ([0043]). Lin discloses a lower semiconductor layer (80B) with a high Ge content (about 55%) with a capping layer (80C) with a lower Ge content ([0050], note that the Ge content is 20%-22%) formed over it and a silicide formed from the capping layer. Alptekin discloses forming silicides with lower Ge concentration produce a more robust and thermally stable silicide contact ([0078]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the capping layer (120) of Kim with the lower Ge content (about 5%) for the capping layer (80C) of Lin to form a silicide (germanosilicide as disclosed by Kim) that has a content equal to or lower than about 5% to about 10% in order to form a silicide with a lower germanium content that will be more robust and thermally stable as disclosed by Alptekin.
Pertaining to claim 4, Lin in view of Liu, Lu, Okonogi, Kim, and Alptekin discloses wherein the metal silicide layer is a silicide of a silicon germanium layer having a composition with an atomic concentration of germanium of less than 5%. (Kim [0041], note that the range of Ge content is disclose to include about 5% which the examiner is interpreting to include Ge content slightly below 5% and the formed silicide layer will have a Ge content equal to or lower than that of the capping layer. For purposes of examination the examiner is interpreting that the silicide will have the lower Ge content and therefore the examiner believes that this limitation is met).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210057570 (Lin et al) in view of US 20200006545 (Liu et al), US 20210091078 (Lu et al), and US 20080230845 (Okonogi et al) as applied to claim 1 above, and further in view of US 20200168703 (Rachmady et al).
As to claim 5, Lin in view of Liu, Lu, and Okonogi discloses the lower fin portion includes a portion of an underlying bulk . . . . silicon substrate (Lin [0015]).
Lin in view of Liu, Lu, and Okonogi does not disclose that the substrate is a bulk single crystalline silicon substrate.
However, Rachmady discloses a transistor for use in an integrated circuit structure that has SiGe source drain features ([0048]) is formed on a bulk single crystalline silicon substrate ([0025]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a substrate (from which the lower portion of the fin is formed) that is made of a bulk single crystalline silicon substrate as the substrate in the invention of Lin because bulk single crystalline silicon substrates are known in the art to be suitable materials for the purpose of forming transistors with SiGe source drain regions as disclosed by Rachmady.
Claim(s) 8-12 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210057570 (Lin et al) in view of US 20200006545 (Liu et al), US 20080067609 (Kim et al), US 201300334693 (Alptekin et al), US 20210091078 (Lu et al), and US 20080230845 (Okonogi et al).
As to claim 8, Lin discloses an integrated circuit structure, comprising: : a fin having a lower fin portion (52) and an upper fin portion (58); a gate stack (108) over the upper fin portion of the fin, the gate stack having a first side opposite a second side (Fig. 1); first and second dielectric gate sidewall spacers (76 +78) along the first and second sides of the gate stack, respectively ([0058]), a first source or drain structure (80, a combination of 80A+80B+80C) comprising an epitaxial structure embedded in the fin at the first side of the gate stack; the epitaxial structure comprising a lower semiconductor layer (80B) and a capping semiconductor layer (80C) on the lower semiconductor layer (Fig. 15B); a second source or drain structure (80) comprising an epitaxial structure embedded in the fin at the second side of the gate stack (Fig. 15B and Fig.1), the epitaxial structure comprising a lower semiconductor layer (80B) and a capping semiconductor layer (80C) on the lower semiconductor layer, wherein the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprises silicon, germanium and boron ([0044]), the germanium having an atomic concentration of . . . 55% at a top surface of the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures ([0044]), and wherein the capping semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprises silicon, germanium and boron ([0050]) . . . . and a metal silicide layer (118) . . . the capping semiconductor layer ([0064]), the metal silicide layer in direct contact with the top surface of the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures ([0065] note that the capping layer 80C that is formed in the area of the opening is removed prior and therefore the silicide is formed directly on the lower semiconductor layer).
Lin does not disclose that the epitaxial structure has germanium having an atomic concentration of greater than 55%, the capping semiconductor has the germanium having an atomic concentration of less than 10%, or the metal silicide layer in a recess in . . . all surfaces of the metal silicide layer are lower than corresponding upper surfaces of the first and second source or drain structures along lengths of the first and second source and drain structures ,or a first trench contact structure over the first source or drain structure and a second trench contact structure over the second source or drain structure, each of the first and second trench contact structures comprising a respective U-shaped metal layer and a respective T-shaped metal layer on and over the entirety of the respective U-shaped metal layer . However, Liu discloses provide a high surface dopant concentration for epitaxial source/drain structures and thus improve device performance. Having a high concentration of germanium (e.g., 20 at. % or more) in the SiGe can introduce strain into the transistor channel, thereby increasing mobility of holes and channel drive current. In some embodiments, the epitaxial source/drain structures 292 can have at least a high Ge concentration region and a low Ge concentration region. In an embodiment shown in FIG. 3, the epitaxial source/drain structures 292 for p-type devices have a first region 213 at or proximate the top surface 215 of the epitaxial source/drain structures 292, and have a second region 217 disposed outward of and/or below the first region 213. In some examples, the first region 213 is Si.sub.1-xGe.sub.x and may have a concentration of Ge in a range from about 20 at. % to about 100 at. %, for example about 25 at. % to about 80 at. %, for example about 40 at. % to about 60 at. % ([0021]). Therefore one of ordinary skill in the art before the effective filing date of the invention would have found it obvious to have a germanium atomic concentration of greater than 55% in order to improve device performance as taught by Liu.
Additionally, Kim discloses a transistor structure that includes a raised source/drain region that includes a lower SiGe layer (117) and a capping SiGe layer (120) and a silicide layer (125) formed from a reaction with a metal layer and the capping SiGe layer (Fig. 9). Kim discloses that the germanium atomic content in the lower SiGe layer (117) is in the range of about 15%-90% ([0023]) and that the germanium content in the capping SiGe layer is about 5%-10% ([0041]). Kim discloses that the germanium content of the silicide (germanosilicide) is equal or lower than that of the capping layer which is used to form the silicide ([0043]). Lin discloses a lower semiconductor layer (80B) with a high Ge content (about 55%) with a capping layer (80C) with a lower Ge content ([0050], note that the Ge content is 20%-22%) formed over it and a silicide formed from the capping layer. Alptekin discloses forming silicides with lower Ge concentration produce a more robust and thermally stable silicide contact ([0078]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate a capping layer with a lower Ge content (about 5%) as disclosed by Kim with the capping layer of Lin to form a silicide (germanosilicide as disclosed by Kim) that has a content equal to or lower than about 5% to about 10% in order to form a silicide with a lower germanium content that will be more robust and thermally stable as disclosed by Alptekin.
Additionally, Lu discloses a epitaxial source and drain configuration (Fig. 19B)
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in which an epitaxial source and drain region (20 +50P) ([0031] and [0065]) are formed in a substrate and embedded in a fin (14+12) ([0031]) structure with a silicide layer (55P) ([0076]-[0077]) formed such that all surfaces of the metal silicide layer are lower than corresponding upper surfaces of the first and second source or drain structures along lengths of the first and second source and drain structures. (Fig. 19B annotated above, note that the line shows the height of the epitaxial structure and that the height of the silicide layer is below the height of the line). Lu discloses that the lower S/D epitaxial layer and the upper S/D epitaxial layer contain Ge, and a concentration of Ge in the upper S/D epitaxial layer is higher than a concentration of Ge in the lower S/D epitaxial layer the lower S/D epitaxial layer 20P includes Si.sub.1-xGe.sub.x, where 0.15≤x≤0.8, and the upper S/D epitaxial layer 50P includes Si.sub.1-yGe.sub.y, where 0.2≤y≤1.0 and x<y. Further, at least one of the lower S/D epitaxial layer and the upper S/D epitaxial layer further contains B (boron), and a concentration of B is in a range from about 1.0×10.sup.20 cm.sup.−3 to about 6.0×10.sup.21 cm.sup.−3 in some embodiments, and is in a range from about 5.0×10.sup.20 cm.sup.−3 to about 1.0×10.sup.21 cm.sup.−3 in other embodiments ([0066]). Lu also discloses that such configuration provides a semiconductor device having reduced source/drain (S/D) contact resistance ([0002]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of Lin in view of Lu such that all surfaces of the metal silicide layer are lower than corresponding upper surfaces of the first and second source or drain structures along lengths of the first and second source and drain structures in order to provide a semiconductor device having reduced source/drain (S/D) contact resistance.
Also, Okonogi discloses an integrated circuit structure (Fig. 1) that includes trench contact structure (12A and 12B) formed over a source (9A) and drain (10). The first and second trench contact structures comprising a respective U-shaped layer (12a) and a respective T-shaped layer (12A) on and over the entirety of the respective U-shaped metal layer ([0093]). Lu discloses a trench contact structure that utilizes a barrier layer (62) and a plug layer (64) where the materials of these layers are disclosed as being metal (Fig. 1a and [0077]). In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.) See MPEP 2144.04 IV B. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of the trench contact structure of Lin with the configuration as disclosed by Okonogi utilizing the known suitable metal materials of Lu absent evidence that the claimed configuration was significant.
Concerning claim 9, Lin in view of Liu, Kim, Lu and Okonogi discloses wherein the capping semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprises the germanium having an atomic concentration of less than 5% (Kim [0041], note that the range of Ge content is disclose to include about 5% which the examiner is interpreting to include Ge content slightly below 5% and thus the examiner believes that this limitation is met).
Continuing to claim 10, Lin in view of Liu, Kim, Lu and Okonogi discloses wherein the capping semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprises boron having an atomic concentration of greater than 5E20cm-3 (Lu [0066]).
Considering claim 11, Lin in view of Liu, Kim, Lu and Okonogi discloses wherein the metal silicide layer is a silicide of a silicon germanium layer having a composition substantially the same as the composition of the lower semiconductor layer at the top surface of the lower semiconductor layer (Kim ([0043], note that the germanium content of the silicide (germanosilicide) is equal or lower than that of the SiGe layer which is used to form the silicide and that portions of the capping layer 80C are removed such that the metal layer is formed to contact the lower semiconductor layer).
Referring to claim 12, Lin in view of Liu, Kim, Lu and Okonogi discloses wherein the metal silicide layer is a silicide of a silicon germanium layer having a composition substantially the same as the composition of the capping semiconductor layer (Kim ([0043], note that the germanium content of the silicide (germanosilicide) is equal or lower than that of the SiGe layer which is used to form the silicide and that only portions of the capping layer 80C are removed such that the metal layer is formed to contact the lower semiconductor layer and portions of the capping layer 80C thus the examiner is interpreting that a silicide having both germanium compositions will be formed).
Pertaining to claim 15, Lin in view of Liu, Kim, Lu and Okonogi discloses further comprising: a first conductive contact (Lin 116 left) on a first portion of the metal silicide layer on the epitaxial structure of the first source or drain structure (Lin Fig. 15B); and a second conductive contact (Lin 116) on a second portion of the metal silicide layer on the epitaxial structure of the second source or drain structure (Lin Fig. 15B).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210057570 (Lin et al) in view of US 20200006545 (Liu et al), US 20080067609 (Kim et al), US 201300334693 (Alptekin et al), US 20210091078 (Lu et al), and US 20080230845 (Okonogi et al) as applied to claim 8 above, and further in view of US 20200168703 (Rachmady et al).
Concerning claim 13, Lin in view of Liu, Kim, Lu and Okonogi discloses the lower fin portion includes a portion of an underlying bulk . . . . silicon substrate ( Lin [0015]).
Lin in view of Liu, Kim, Lu and Okonogi does not disclose that the substrate is a bulk single crystalline silicon substrate.
However, Rachmady discloses a transistor for use in an integrated circuit structure that has SiGe source drain features ([0048]) is formed on a bulk single crystalline silicon substrate ([0025]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a substrate (from which the lower portion of the fin is formed) that is made of a bulk single crystalline silicon substrate as the substrate in the invention of Lin in view of Liu, Kim, and Lu because bulk single crystalline silicon substrates are known in the art to be suitable materials for the purpose of forming transistors with SiGe source drain regions as disclosed by Rachmady.
Claim(s) 16-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210057570 (Lin et al) in view of US 20200006545 (Liu et al), US 20200168703 (Rachmady et al), US 20210091078 (Lu et al), and US 20080230845 (Okonogi et al).
Concerning claim 16, Lin discloses . . . .an integrated circuit structure (Figs. 1 and 15B), comprising: a fin having a lower fin portion (52) and an upper fin portion (58); a gate stack (108) over the upper fin portion of the fin, the gate stack having a first side opposite a second side (Fig. 1); first and second dielectric gate sidewall spacers (76 +78) along the first and second sides of the gate stack, respectively ([0058]), a first source or drain structure (80, a combination of 80A+80B+80C) comprising an epitaxial structure embedded in the fin at the first side of the gate stack; a second source or drain structure (80) comprising an epitaxial structure embedded in the fin at the second side of the gate stack (Fig. 8), each of the epitaxial structures of the first and second source or drain structures comprising silicon, germanium and boron, the germanium having an atomic concentration of . . . 55% at a top surface of each of the epitaxial structures of the first and second source or drain structures ([0044]); and a metal silicide layer (118) . . . the top surface of each of the epitaxial structures of the first and second source or drain structures ([0065]).
Lin does not explicitly disclose that the epitaxial structure germanium having an atomic concentration of greater than 55%, the integrated circuit structure is included as a component coupled to a board of a computing device, a first trench contact structure over the first source or drain structure and a second trench contact structure over the second source or drain structure, each of the first and second trench contact structures comprising a respective U-shaped metal layer and a respective T-shaped metal layer on and over the entirety of the respective U-shaped metal layer , or a metal silicide layer in a recess in the top surface of each of the epitaxial structures of the first and second source or drain structures, all surfaces of the metal silicide layer are lower than corresponding upper surfaces of the first and second source or drain structures along lengths of the first and second source and drain structures. Lin discloses that the integrated circuit structure can be used in a variety of electronic applications such as personal computers, cell phones, and other electronic equipment ([0001]).
However, Liu discloses provide a high surface dopant concentration for epitaxial source/drain structures and thus improve device performance. Having a high concentration of germanium (e.g., 20 at. % or more) in the SiGe can introduce strain into the transistor channel, thereby increasing mobility of holes and channel drive current. In some embodiments, the epitaxial source/drain structures 292 can have at least a high Ge concentration region and a low Ge concentration region. In an embodiment shown in FIG. 3, the epitaxial source/drain structures 292 for p-type devices have a first region 213 at or proximate the top surface 215 of the epitaxial source/drain structures 292, and have a second region 217 disposed outward of and/or below the first region 213. In some examples, the first region 213 is Si.sub.1-xGe.sub.x and may have a concentration of Ge in a range from about 20 at. % to about 100 at. %, for example about 25 at. % to about 80 at. %, for example about 40 at. % to about 60 at. % ([0021]). Therefore one of ordinary skill in the art before the effective filing date of the invention would have found it obvious to have a germanium atomic concentration of greater than 55% in order to improve device performance as taught by Liu.
Additionally, Rachmady discloses a transistor with SiGe source and drain regions are used in mobile computing devices (computers, cell phones, etc.) and that the components of computing device include a motherboard (1402) which the transistor is coupled ([0052]). Additionally this computing device can include a communication chip, memory, camera, battery, a packaged die, and antenna ([0055]-[0056]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to include the aforementioned components in the various computing devices disclosed by Lin because these are known components that are used in the manufacture of a computing device.
Also, Lu discloses a epitaxial source and drain configuration (Fig. 19B)
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in which an epitaxial source and drain region (20 +50P) ([0031] and [0065]) are formed in a substrate and embedded in a fin (14+12) ([0031]) structure with a silicide layer (55P) ([0076]-[0077]) formed such that all surfaces of the metal silicide layer are lower than corresponding upper surfaces of the first and second source or drain structures along lengths of the first and second source and drain structures. (Fig. 19B annotated above, note that the line shows the height of the epitaxial structure and that the height of the silicide layer is below the height of the line). Lu discloses that the lower S/D epitaxial layer and the upper S/D epitaxial layer contain Ge, and a concentration of Ge in the upper S/D epitaxial layer is higher than a concentration of Ge in the lower S/D epitaxial layer the lower S/D epitaxial layer 20P includes Si.sub.1-xGe.sub.x, where 0.15≤x≤0.8, and the upper S/D epitaxial layer 50P includes Si.sub.1-yGe.sub.y, where 0.2≤y≤1.0 and x<y. Further, at least one of the lower S/D epitaxial layer and the upper S/D epitaxial layer further contains B (boron), and a concentration of B is in a range from about 1.0×10.sup.20 cm.sup.−3 to about 6.0×10.sup.21 cm.sup.−3 in some embodiments, and is in a range from about 5.0×10.sup.20 cm.sup.−3 to about 1.0×10.sup.21 cm.sup.−3 in other embodiments ([0066]). Lu also discloses that such configuration provides a semiconductor device having reduced source/drain (S/D) contact resistance ([0002]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of Lin in view of Lu such that all surfaces of the metal silicide layer are lower than corresponding upper surfaces of the first and second source or drain structures along lengths of the first and second source and drain structures in order to provide a semiconductor device having reduced source/drain (S/D) contact resistance.
Also, Okonogi discloses an integrated circuit structure (Fig. 1) that includes trench contact structure (12A and 12B) formed over a source (9A) and drain (10). The first and second trench contact structures comprising a respective U-shaped layer (12a) and a respective T-shaped layer (12A) on and over the entirety of the respective U-shaped metal layer ([0093]). Lu discloses a trench contact structure that utilizes a barrier layer (62) and a plug layer (64) where the materials of these layers are disclosed as being metal (Fig. 1a and [0077]). In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.) See MPEP 2144.04 IV B. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of the trench contact structure of Lin with the configuration as disclosed by Okonogi utilizing the known suitable metal materials of Lu absent evidence that the claimed configuration was significant.
Continuing to claim 17, Lin in view of Liu, Rachmady, Lu, and Okonogi discloses further comprising: a memory coupled to the board (Rachmady [0056]).
Considering claim 18, Lin in view of Liu, Rachmady, Lu, and Okonogi discloses further comprising: a communication chip coupled to the board (Rachmady [0056]).
Referring to claim 19, Lin in view of Liu, Rachmady, Lu, and Okonogi discloses further comprising: a camera coupled to the board (Rachmady [0056]).
Regarding claim 20, Lin in view of Liu, Rachmady, Lu, and Okonogi discloses further comprising: a battery coupled to the board (Rachmady [0056]).
Pertaining to claim 21, Lin in view of Liu, Rachmady, Lu, and Okonogi discloses further comprising: an antenna coupled to the board (Rachmady [0056]).
As to claim 22, Lin in view of Liu, Rachmady, Lu, and Okonogi discloses wherein the component is a packaged integrated circuit die (Rachmady [0055]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8, and 16 have been considered but are moot because the new ground of rejection does not rely the same combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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/VALERIE N NEWTON/Examiner, Art Unit 2897 05/28/26
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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