Prosecution Insights
Last updated: April 19, 2026
Application No. 16/934,919

METHODS OF MANUFACTURING A LIGHT-EMITTING DEVICE WITH METAL INLAY AND TOP CONTACTS

Non-Final OA §103
Filed
Jul 21, 2020
Examiner
CULBERT, CHRISTOPHER A
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Lumileds LLC
OA Round
7 (Non-Final)
41%
Grant Probability
Moderate
7-8
OA Rounds
3y 8m
To Grant
46%
With Interview

Examiner Intelligence

Grants 41% of resolved cases
41%
Career Allow Rate
137 granted / 333 resolved
-26.9% vs TC avg
Minimal +4% lift
Without
With
+4.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
81 currently pending
Career history
414
Total Applications
across all art units

Statute-Specific Performance

§103
55.8%
+15.8% vs TC avg
§102
20.9%
-19.1% vs TC avg
§112
22.1%
-17.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 333 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 1-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/14/2025. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 11-17 is/are rejected under 35 U.S.C. 103 as being unpatentable Steudel et al. (US 2020/0185566 A1; hereinafter Steudel) in view of Liu et al. (US 2017/0194533 A1; hereinafter Liu). Regarding claim 11, Steudel discloses a method comprising: obtaining a light-emitting package (Fig. 6) comprising a hybridized die (“The two semiconductor parts 30a and 30b are particularly bonded together . . . . by using the W2W hybrid bonding”; ¶ 0075); wherein the hybridized die comprises a light-emitting diode array (30a in Fig. 6; “30a comprises an array 31 including a plurality of compound semiconductor LEDs”, ¶ 0073) mounted on a silicon backplane, wherein the silicon backplane is a complimentary metal-oxide-semiconductor (CMOS) backplane (30b in Fig. 6; “30b . . . comprises a CMOS IC 33”; Steudel discloses that the CMOS components can be silicon based: “a Si-CMOS (active matrix readout) IC” in ¶ 0004). With regards to the CMOS backplane comprising either the same number of drivers as the integer number of light-emitting elements in the LED array or a number of drivers equal to a sub-set of the integer number of light-emitting elements in the LED array, the Examiner notes that Applicant has not put any limitations as to how the “sub-set” may be chosen. As such, the sub-set can be chosen to be 1 (i.e., a single light-emitting element is a subset of a number of light-emitting elements greater than 1). Further, since the CMOS backplane needs to only comprise a number of drivers equal to said sub-set (as opposed to the exact number of drivers within the CMOS backplane being equal to the sub-set), the claim language does not preclude the CMOS backplane from having a number of drivers greater than the number of light-emitting elements within the sub-set. Steudel discloses that the CMOS backplane comprises some amount of drivers (“the CMOS IC can drive and/or readout the array 31” and “The CMOS IC 33 is thus configured to drive/readout each LED” in ¶ 0082). Therefore, the CMOS backplane comprises one driver. As such, the CMOS backplane of Steudel comprises a number of drivers (one) equal to a sub-set (one) of the integer number of light-emitting elements in the LED array. Steudel does not disclose a packaging substrate or a control board (or connecting the hybridized device to such compoennts) as claimed. However, it was known in the art before the Application’s effective filing date to obtain a packaging substrate (“support 30” in Fig. 5 of Liu; ¶ 0032) comprising a plurality of conductive contacts (unlabeled in Fig. 5, corresponding to “top contact pads 38 and 39” in Fig. 2; ¶ 0032) on a top surface of the packaging substrate (see Figs. 2 and 5). Liu further discloses obtaining a control board (70 in Fig. 5; “the structure 70, which may be, for example, a metal-core printed circuit board”, ¶ 0037) defining an opening formed completely through a thickness of the control board (“In a metal-core printed circuit board, the exposed thermal pad may also be the metal core itself with an opening for direct access.”, ¶ 0037 of Liu). There was a benefit to mounting a hybridized device on the packaging substrate and control board of Liu in that the packaging substrate and control board combination of Liu contains a metal inlay (corresponding to “thermally conductive slug 32” of Liu) to conduct away excess heat (“thermally conductive slug 32 form[s] a thermal path that may conduct heat away from” the light-emitting device, ¶ 0034 of Liu). It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to attach a bottom surface of the silicon backplane of the hybridized device of Steudel to a top surface of the metal inlay of the device of Liu for this benefit. In the resulting configuration, the overall structure (including the hybridized device and the control board in the method of the combination) is mouned on a top surface of a heat sink (“metal core” in ¶ 0037 of Liu) with the hybridized device at least partially in the opening in the control board (the hybridized device being within the opening in plan view) and thermally coupled to the top surface of the heat sink (¶ 0037 of Liu). Further, in the resulting configuration there will be conductive contacts (unlabeled contacts directly contacting wires 46 and 48 in Fig. 3 of Liu) which will be on a top surface of the control board (although they will not be directly on said top surface). Liu discloses directly wirebonding the plurality of conductive contacts on the top surface of the packaging substrate to these conductive contacts (compare Figs. 2 and 3 of Liu). Regarding claim 12, the combination of Steudel and Liu discloses the method of claim 11, as discussed above. Liu further discloses that the packaging substrate comprises a metal inlay (“highly thermally conductive slug 32 . . . . The slug may be any suitable material, including, for example, metal”, ¶ 0027; Fig. 5) embedded in the packaging substrate (see Fig. 5), the heat sink comprises a second embedded metal inlay (“metal core” within the control board, ¶ 0037 of Liu), and mounting the light-emitting package on the top surface of the heat sink comprises placing the packaging substrate over the heat sink with the first embedded metal inlay adjacent to the second embedded metal inlay (¶ 0037 of Liu). Regarding claim 13, the combination of Steudel and Liu discloses the method of claim 12, as discussed above. Liu further discloses that mounting the light-emitting package and the control board on the top surface of the heat sink comprises: applying a layer of a thermal interface material (TIM) (37 in Fig. 5 of Liu) on the top surface of the heat sink; and placing the light-emitting package and the control board on the TIM (see Fig. 5 of Liu). Regarding claim 14, Steudel discloses a method comprising: obtaining a light-emitting diode (LED) array comprising an integer number greater than 1 of light-emitting elements (30a in Fig. 6; “30a comprises an array 31 including a plurality of compound semiconductor LEDs”, ¶ 0073); a silicon backplane, wherein the silicon backplane is a complimentary metal-oxide-semiconductor (CMOS) backplane (30b in Fig. 6; “30b . . . comprises a CMOS IC 33”; Steudel discloses that the CMOS components can be silicon based: “a Si-CMOS (active matrix readout) IC” in ¶ 0004). With regards to the CMOS backplane comprising either the same number of drivers as the integer number of light-emitting elements in the LED array or a number of drivers equal to a sub-set of the integer number of light-emitting elements in the LED array, the Examiner notes that Applicant has not put any limitations as to how the “sub-set” may be chosen. As such, the sub-set can be chosen to be 1 (i.e., a single light-emitting element is a subset of a number of light-emitting elements greater than 1). Further, since the CMOS backplane needs to only comprise a number of drivers equal to said sub-set (as opposed to the exact number of drivers within the CMOS backplane being equal to the sub-set), the claim language does not preclude the CMOS backplane from having a number of drivers greater than the number of light-emitting elements within the sub-set. Steudel discloses that the CMOS backplane comprises some amount of drivers (“the CMOS IC can drive and/or readout the array 31” and “The CMOS IC 33 is thus configured to drive/readout each LED” in ¶ 0082). Therefore, the CMOS backplane comprises one driver. As such, the CMOS backplane of Steudel comprises a number of drivers (one) equal to a sub-set (one) of the integer number of light-emitting elements in the LED array. Steudel further discloses forming a hybridized device by attaching a bottom surface of the LED array to a top surface of the silicon backplane (“The two semiconductor parts 30a and 30b are particularly bonded together . . . . by using the W2W hybrid bonding”; ¶ 0075). Steudel does not disclose a packaging substrate with a first metal inlay or a control board (or connecting the hybridized device to such compoennts) as claimed. However, it was known in the art before the Application’s effective filing date to obtain a packaging substrate (“support 30” in Fig. 5 of Liu; ¶ 0032), a first metal inlay (“highly thermally conductive slug 32 . . . . The slug may be any suitable material, including, for example, metal”, ¶ 0027; Fig. 5) embedded in the packaging substrate (see Fig. 5), and a plurality of conductive contacts (unlabeled in Fig. 5, corresponding to “top contact pads 38 and 39” in Fig. 2; ¶ 0032) on a top surface of the packaging substrate (see Figs. 2 and 5). Liu further discloses obtaining a control board (70 in Fig. 5; “the structure 70, which may be, for example, a metal-core printed circuit board”, ¶ 0037) defining an opening formed completely through a thickness of the control board (“In a metal-core printed circuit board, the exposed thermal pad may also be the metal core itself with an opening for direct access.”, ¶ 0037 of Liu) having an embedded second metal inlay (“metal-core”, ¶ 0037). There was a benefit to mounting a hybridized device on the packaging substrate and control board of Liu in that the packaging substrate and control board combination of Liu contains metal inlays (corresponding to “thermally conductive slug 32” of Liu) to conduct away excess heat (“thermally conductive slug 32 form[s] a thermal path that may conduct heat away from” the light-emitting device, ¶ 0034 of Liu). It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to attach a bottom surface of the silicon backplane of the hybridized device of Steudel with a packaging substrate and control board as taught by Liu such that a bottom surface of the silicon backplane of the hybridized device is on a top surface of the control board of Liu with the first metal inlay adjacent the embedded second metal inlay for this benefit. Further, in the resulting configuration there will be conductive contacts (unlabeled contacts directly contacting wires 46 and 48 in Fig. 3 of Liu) which will be on a top surface of the control board (although they will not be directly on said top surface). Liu discloses directly wirebonding the plurality of conductive contacts on the top surface of the packaging substrate to these conductive contacts (compare Figs. 2 and 3 of Liu). Regarding claim 15, the combination of Steudel and Liu discloses the method of claim 14, as discussed above. Liu further discloses that mounting the light-emitting package and the control board on the top surface of the heat sink comprises: applying a layer of a thermal interface material (TIM) (37 in Fig. 5 of Liu) on the top surface of the heat sink; and placing the light-emitting package and the control board on the TIM (see Fig. 5 of Liu). Alternatively regarding claim 11, Steudel discloses a method comprising: obtaining a light-emitting package (Fig. 6) comprising a hybridized die (“The two semiconductor parts 30a and 30b are particularly bonded together . . . . by using the W2W hybrid bonding”; ¶ 0075); wherein the hybridized die comprises a light-emitting diode array (30a in Fig. 6; “30a comprises an array 31 including a plurality of compound semiconductor LEDs”, ¶ 0073) mounted on a silicon backplane, wherein the silicon backplane is a complimentary metal-oxide-semiconductor (CMOS) backplane (30b in Fig. 6; “30b . . . comprises a CMOS IC 33”; Steudel discloses that the CMOS components can be silicon based: “a Si-CMOS (active matrix readout) IC” in ¶ 0004). With regards to the CMOS backplane comprising either the same number of drivers as the integer number of light-emitting elements in the LED array or a number of drivers equal to a sub-set of the integer number of light-emitting elements in the LED array, the Examiner notes that Applicant has not put any limitations as to how the “sub-set” may be chosen. As such, the sub-set can be chosen to be 1 (i.e., a single light-emitting element is a subset of a number of light-emitting elements greater than 1). Further, since the CMOS backplane needs to only comprise a number of drivers equal to said sub-set (as opposed to the exact number of drivers within the CMOS backplane being equal to the sub-set), the claim language does not preclude the CMOS backplane from having a number of drivers greater than the number of light-emitting elements within the sub-set. Steudel discloses that the CMOS backplane comprises some amount of drivers (“the CMOS IC can drive and/or readout the array 31” and “The CMOS IC 33 is thus configured to drive/readout each LED” in ¶ 0082). Therefore, the CMOS backplane comprises one driver. As such, the CMOS backplane of Steudel comprises a number of drivers (one) equal to a sub-set (one) of the integer number of light-emitting elements in the LED array. Steudel does not disclose a packaging substrate or a control board (or connecting the hybridized device to such compoennts) as claimed. However, it was known in the art before the Application’s effective filing date to obtain a packaging substrate (“support 30” in Fig. 5 of Liu; ¶ 0032) comprising a plurality of conductive contacts (unlabeled in Fig. 5, corresponding to “top contact pads 38 and 39” in Fig. 2; ¶ 0032) on a top surface of the packaging substrate (see Figs. 2 and 5). Liu further discloses obtaining a control board (combination of 70 and 72 in Fig. 5; “the structure 70, which may be, for example, a metal-core printed circuit board”, ¶ 0037) defining an opening formed completely through a thickness of the control board (“In a metal-core printed circuit board, the exposed thermal pad may also be the metal core itself with an opening for direct access.”, ¶ 0037 of Liu). There was a benefit to mounting a hybridized device on the packaging substrate and control board of Liu in that the packaging substrate and control board combination of Liu contains a metal inlay (corresponding to “thermally conductive slug 32” of Liu) to conduct away excess heat (“thermally conductive slug 32 form[s] a thermal path that may conduct heat away from” the light-emitting device, ¶ 0034 of Liu). It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to attach a bottom surface of the silicon backplane of the hybridized device of Steudel to a top surface of the metal inlay of the device of Liu for this benefit. In the resulting configuration, the overall structure (including the hybridized device and the control board in the method of the combination) is mounted on a top surface of a heat sink (“metal core” in ¶ 0037 of Liu) with the hybridized device at least partially in the opening in the control board (the hybridized device being within the opening in plan view) and thermally coupled to the top surface of the heat sink (¶ 0037 of Liu). Further, in the resulting configuration there will be conductive contacts (74 and 76 in Fig. 5) which will be on a top surface of the control board (although they will not be directly on said top surface). Liu differs from the claimed invention by the substitution of wire bonds between the plurality of conductive contacts on the top surface of the packaging substrate to the conductive contacts on the top surface of the control board with electrical via connection. However, wire bonds and the corresponding function was known in the art (set wire bonds in Fig. 5 of Liu). As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have substituted the electrical via connection with wire bonds and the results of the substitution would have been predictable. (see MPEP § 2143(I)(B)). In the resulting configuration, the plurality of conductive contacts on the top surface of the packaging substrate are directly wirebonded to the conductive contacts on the top surface of the control board. Regarding claim 16, the conductive contacts on the top surface of the control board are disposed directly on the top surface of the control board (see Fig. 5). Alternatively regarding claim 14, Steudel discloses a method comprising: obtaining a light-emitting diode (LED) array comprising an integer number greater than 1 of light-emitting elements (30a in Fig. 6; “30a comprises an array 31 including a plurality of compound semiconductor LEDs”, ¶ 0073); a silicon backplane, wherein the silicon backplane is a complimentary metal-oxide-semiconductor (CMOS) backplane (30b in Fig. 6; “30b . . . comprises a CMOS IC 33”; Steudel discloses that the CMOS components can be silicon based: “a Si-CMOS (active matrix readout) IC” in ¶ 0004). With regards to the CMOS backplane comprising either the same number of drivers as the integer number of light-emitting elements in the LED array or a number of drivers equal to a sub-set of the integer number of light-emitting elements in the LED array, the Examiner notes that Applicant has not put any limitations as to how the “sub-set” may be chosen. As such, the sub-set can be chosen to be 1 (i.e., a single light-emitting element is a subset of a number of light-emitting elements greater than 1). Further, since the CMOS backplane needs to only comprise a number of drivers equal to said sub-set (as opposed to the exact number of drivers within the CMOS backplane being equal to the sub-set), the claim language does not preclude the CMOS backplane from having a number of drivers greater than the number of light-emitting elements within the sub-set. Steudel discloses that the CMOS backplane comprises some amount of drivers (“the CMOS IC can drive and/or readout the array 31” and “The CMOS IC 33 is thus configured to drive/readout each LED” in ¶ 0082). Therefore, the CMOS backplane comprises one driver. As such, the CMOS backplane of Steudel comprises a number of drivers (one) equal to a sub-set (one) of the integer number of light-emitting elements in the LED array. Steudel further discloses forming a hybridized device by attaching a bottom surface of the LED array to a top surface of the silicon backplane (“The two semiconductor parts 30a and 30b are particularly bonded together . . . . by using the W2W hybrid bonding”; ¶ 0075). Steudel does not disclose a packaging substrate with a first metal inlay or a control board (or connecting the hybridized device to such compoennts) as claimed. However, it was known in the art before the Application’s effective filing date to obtain a packaging substrate (“support 30” in Fig. 5 of Liu; ¶ 0032), a first metal inlay (“highly thermally conductive slug 32 . . . . The slug may be any suitable material, including, for example, metal”, ¶ 0027; Fig. 5) embedded in the packaging substrate (see Fig. 5), and a plurality of conductive contacts (unlabeled in Fig. 5, corresponding to “top contact pads 38 and 39” in Fig. 2; ¶ 0032) on a top surface of the packaging substrate (see Figs. 2 and 5). Liu further discloses obtaining a control board (combination of 70 and 72 in Fig. 5; “the structure 70, which may be, for example, a metal-core printed circuit board”, ¶ 0037) defining an opening formed completely through a thickness of the control board (“In a metal-core printed circuit board, the exposed thermal pad may also be the metal core itself with an opening for direct access.”, ¶ 0037 of Liu) having an embedded second metal inlay (“metal-core”, ¶ 0037). There was a benefit to mounting a hybridized device on the packaging substrate and control board of Liu in that the packaging substrate and control board combination of Liu contains metal inlays (corresponding to “thermally conductive slug 32” of Liu) to conduct away excess heat (“thermally conductive slug 32 form[s] a thermal path that may conduct heat away from” the light-emitting device, ¶ 0034 of Liu). It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to attach a bottom surface of the silicon backplane of the hybridized device of Steudel with a packaging substrate and control board as taught by Liu such that a bottom surface of the silicon backplane of the hybridized device is on a top surface of the control board of Liu with the first metal inlay adjacent the embedded second metal inlay for this benefit. Further, in the resulting configuration there will be conductive contacts (74 and 76 in Fig. 5) which will be on a top surface of the control board (although they will not be directly on said top surface). Liu differs from the claimed invention by the substitution of wire bonds between the plurality of conductive contacts on the top surface of the packaging substrate to the conductive contacts on the top surface of the control board with electrical via connection. However, wire bonds and the corresponding function was known in the art (set wire bonds in Fig. 5 of Liu). As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have substituted the electrical via connection with wire bonds and the results of the substitution would have been predictable. (see MPEP § 2143(I)(B)). In the resulting configuration, the plurality of conductive contacts on the top surface of the packaging substrate are directly wirebonded to the conductive contacts on the top surface of the control board. Regarding claim 17, the conductive contacts on the top surface of the control board are disposed directly on the top surface of the control board (see Fig. 5). Response to Arguments Applicant's arguments filed 6/30/2025 have been fully considered but they are not persuasive. Regarding claims 11 and 14, Applicant argues that conductive contacts are not on the top surface of the control board of Liu. This argument is not persuasive as Applicant did not require direct contact in either claims 11 or 14. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER A CULBERT/Examiner, Art Unit 2815
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Prosecution Timeline

Jul 21, 2020
Application Filed
Jan 13, 2023
Non-Final Rejection — §103
Apr 19, 2023
Response Filed
May 06, 2023
Final Rejection — §103
Jul 12, 2023
Response after Non-Final Action
Aug 14, 2023
Request for Continued Examination
Aug 16, 2023
Response after Non-Final Action
Oct 02, 2023
Non-Final Rejection — §103
Jan 05, 2024
Applicant Interview (Telephonic)
Jan 05, 2024
Examiner Interview Summary
Jan 08, 2024
Response Filed
Feb 06, 2024
Final Rejection — §103
Apr 12, 2024
Request for Continued Examination
Apr 17, 2024
Response after Non-Final Action
Jul 13, 2024
Non-Final Rejection — §103
Dec 11, 2024
Response Filed
Mar 31, 2025
Final Rejection — §103
Jun 04, 2025
Response after Non-Final Action
Jun 30, 2025
Request for Continued Examination
Jul 01, 2025
Response after Non-Final Action
Feb 21, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

7-8
Expected OA Rounds
41%
Grant Probability
46%
With Interview (+4.4%)
3y 8m
Median Time to Grant
High
PTA Risk
Based on 333 resolved cases by this examiner. Grant probability derived from career allow rate.

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