DETAILED ACTION
This office action is in response to amendment filed 6/30/2025.
Claims 1-7, 9, and 11-24 are pending. Claims 8 and 10 have been canceled. Claims 6-7, 13-18, and 20-21 have been withdrawn. Claims 1 and 19 have been amended.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 3 reciting “the thermal buffer structure comprises an underfill material, a non-conductive film, or a die attach film” renders the claim indefinite. Independent claim 1 recites the thermal buffer structure comprises an epoxy molding compound. It is unclear how does “an underfill material, a non-conductive film, or a die attach film” further limit the epoxy molding compound of claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9, 12, 19, and 22-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. US 2015/0364445 A1 (Choi) in view of Kim et al. US 2022/0013501 A1 (Kim).
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In re claim 1, Choi discloses (e.g. FIGs. 4A-4E, 6, 7) a semiconductor device, comprising:
a first die assembly 30+10+70+80+90 (see FIG. 6 annotated above showing two interpretations) including—
a semiconductor die including a semiconductor substrate 10 (Si, ¶ 53) having a first (top) surface and a second (bottom) surface opposite the first surface and a plurality of active circuit elements 15 at the first (top) surface of the semiconductor substrate 10,
an intermediate structure 6 (between 70 and 80) including a third (bottom) surface facing the semiconductor die 10+15 and a fourth (top) surface opposite the third (bottom) surface and facing away from the semiconductor die 10+15, the third (bottom) surface facing the plurality active circuit elements 15, wherein the plurality of active circuit elements 15 are positioned between the third (bottom) surface of the intermediate structure 6 and the first (top) surface of the semiconductor substrate 10, and
a routing structure 80 coupled to the fourth (top) surface of the intermediate structure 6, wherein the intermediate structure 6 (between 70 and 80) is positioned between the plurality of active circuit elements 15 and the routing structure 80;
a second die assembly 40+60 including—
a carrier substrate 60 including a first (bottom) surface and a second (top) surface opposite the first surface, and
a redistribution structure 40 on or over the first (bottom) surface of the carrier substrate 60;
a thermal buffer structure 20 between the first and second die assemblies, wherein the thermal buffer structure 20 is coupled to the second (bottom) surface of the semiconductor substrate 10 of the semiconductor die 10+15 and to the second (top) surface of the carrier substrate 60, wherein a first distance from the intermediate structure 6 (between 70 and 80) to the thermal buffer 20 is less than a second distance from the routing structure 80 to the thermal buffer structure 20,
wherein the first die assembly 30+10+70+80+90 has a first component threshold temperature, wherein the second die assembly 40+60 has a second component operating temperature that is greater than the first component threshold temperature (devices 35 consuming high power (¶ 84) and devices 15 are protected from heat generated from the third devices (¶ 88)), and wherein the thermal buffer structure 20 is configured to reduce transfer of heat from the second die assembly 40+60 to the first die assembly 30+10+70+80+90 (¶ 88); and
a plurality of interconnections 11,21,31,61,71,81 extending through at least the semiconductor substrate 10, the carrier substrate 60, and the thermal buffer structure 20, wherein the interconnections 11,21,31,61,71,81 electrically couple the active circuit elements 15 to the redistribution structure 40 via the routing structure 80 (devices 15 electrically connected to wirings in 40 through vias 11,21,31,61,71,81 and conductive patterns 1,12,13,14 (see FIG. 4B)).
Choi discloses the thermal buffer structure (see annotated figure above) having a low thermal conductivity value (¶ 88) and comprises an underfill material 6 (FIG. 4B). Choi does not explicitly disclose the thermal buffer structure comprises an epoxy molding compound.
However, Kim discloses (e.g. FIG. 4A) a chip stack comprising an underfill layer 420 having a low thermal conductivity (¶ 55) and may be formed of an epoxy molding compound (¶ 50).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Choi’s underfill material 6 using low thermal conductivity epoxy molding compound as taught by Kim to improve thermal insulation effect as desired by Choi. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
In re claim 2, Choi discloses (e.g. FIGs. 4, 6 & 7) wherein the thermal buffer structure 20 (2-3 W/mK for LTCC, ¶ 48,54) is less thermally conductive than the semiconductor substrate 30,10 (about 150 W/mK for Si, ¶ 49, 53,73,86). Kim discloses (e.g. FIGs. 4A-4B) wherein the thermal buffer structure 420 (e.g. EMC, ¶ 50, low thermal conductivity, ¶ 55) is less thermally conductive than the semiconductor substrate 110 (e.g. silicon, ¶ 28).
In re claim 3, as best understood, Choi discloses (e.g. see FIG. 6 annotated above) wherein the thermal buffer structure (including 6,20) comprises an underfill material 6, a non-conductive film 20,5 (see FIG. 4C), or a die attach film.
In re claim 4, Choi discloses (e.g. FIGs. 4,6,7) wherein the redistribution structure 40 is configured to route signals between the active circuit elements 15 and an external device 35 (35 is external to 15 and 90).
In re claim 5, Choi discloses (e.g. FIGs. 4,6,7) wherein the redistribution structure (including 6,1,40, see annotations in FIG. 6 above) is directly coupled to the carrier substrate 60.
In re claim 9, Choi discloses (e.g. FIG. 7) wherein the routing structure (only 80) is thinner than the redistribution structure (including 1,6 and 40).
In re claim 12, Choi discloses (e.g. FIGs. 4,6,7) wherein the interconnections 11,21,31,61,71,81 include: (a) a plurality of first vias 11 extending through the semiconductor substrate 10, (b) a plurality of second vias 61 extending through the carrier substrate 60, and (c) a plurality of interconnect structures 21 extending through the thermal buffer structure 20.
In re claim 19, Choi discloses (e.g. FIG. 4, 6, 7) a semiconductor device, comprising:
a semiconductor substrate 10 (Si, ¶ 53) including a first (top) surface and a second (bottom) surface opposite the first surface;
a plurality of active circuit elements 15 at the first (top) surface of the semiconductor substrate 10;
an intermediate structure 6 (between 70 and 80) including a third (bottom) surface and a fourth (top) surface opposite the third (bottom) surface, the third (bottom) surface facing the plurality active circuit elements 15, wherein the plurality of active circuit elements 15 are positioned between the third (bottom) surface of the intermediate structure 6 and the first (top) surface of the semiconductor substrate 10;
a routing structure 80 coupled to the fourth (top) surface of the intermediate structure 6 (between 70 and 80), wherein the intermediate structure 6 is positioned between the plurality of active circuit elements 15 and the routing structure 80;
a thermal buffer structure (including 6 and 20, see FIG. 6 annotated above) including a first (bottom) surface and a second (top) surface opposite the first surface, the second (top) surface of the thermal buffer structure being coupled to the second (bottom) surface of the semiconductor substrate 10;
a redistribution structure 40 on or over the first (bottom) surface of the thermal buffer structure; and
a plurality of interconnections 11,21,31,61,71,81 extending through at least the semiconductor substrate 10 and the thermal buffer structure 20, wherein the interconnections 11,21,31,61,71,81 electrically couple the active circuit elements 15 to the redistribution structure 40 via the routing structure 80 (devices 15 electrically connected to wirings in 40 through vias 11,21,31,61,71,81 and conductive patterns 1,12,13,14 (see FIG. 4B)).
wherein a first die assembly 30+10+70+80+90 of the semiconductor device including the plurality of active circuit elements 15 has a first component threshold temperature, wherein a second die assembly 40+60 of the semiconductor device including the redistribution structure 40 is spaced apart from the first die assembly 30+10+70+80+90 (spaced by the thermal buffer structure 20) and has a second component operating temperature that is greater than the first component threshold temperature (devices 35 consuming high power (¶ 84) and devices 15 are protected from heat generated from the third devices (¶ 88)), and wherein the thermal buffer structure (comprising 20) is configured to reduce transfer of heat from the second die assembly 40+60 to the first die assembly 30+10+70+80+90 (¶ 88).
Choi discloses the thermal buffer structure (see annotated figure above) having a low thermal conductivity value (¶ 88) and comprises an underfill material 6 (FIG. 4B). Choi does not explicitly disclose the thermal buffer structure comprises an epoxy molding compound.
However, Kim discloses (e.g. FIG. 4A) a chip stack comprising an underfill layer 420 having a low thermal conductivity (¶ 55) and may be formed of an epoxy molding compound (¶ 50).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Choi’s underfill material 6 using low thermal conductivity epoxy molding compound as taught by Kim to improve thermal insulation effect as desired by Choi. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
In re claim 22, Choi discloses (e.g. FIGs. 4, 6 & 7) wherein the thermal buffer structure 20 (2-3 W/mK for LTCC, ¶ 48,54) is less thermally conductive than the semiconductor substrate 30,10 (about 150 W/mK for Si, ¶ 49,53,73,86). Kim discloses (e.g. FIGs. 4A-4B) wherein the thermal buffer structure 420 (e.g. EMC, ¶ 50, low thermal conductivity, ¶ 55) is less thermally conductive than the semiconductor substrate 110 (e.g. silicon, ¶ 28).
In re claim 23, Choi discloses (e.g. FIG. 4B) further comprising a passivation layer 4 (between 80 and 90) formed on the routing structure 80 (FIG. 6).
Claims 1-5, 9, 11-12, 19, and 22-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Groothuis et al. US 2014/0015598 A1 (Groothuis) in view of Kim et al. US 2022/0013501 A1 (Kim).
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In re claim 1, Groothuis discloses (e.g. FIG. 1, see annotated above) a semiconductor device, comprising:
a first die assembly 14,18 including—
a semiconductor die 14+18A including semiconductor substrate 14 having a first (top) surface and a second (bottom) surface opposite the first surface and a plurality of active circuit elements 18A at the first (top) surface of the semiconductor substrate 14,
an intermediate structure 18B including a third (bottom) surface facing the semiconductor die 14+18A and a fourth (top) surface opposite the third (bottom) surface and facing away from the semiconductor die 14+18B, the third (bottom) surface facing the plurality of active circuit elements 18A, wherein the plurality of active circuit elements 18A are positioned between the third (bottom) surface of the intermediate structure 18B and the first (top) surface of the semiconductor substrate 14, and
a routing structure (e.g. 16,22 above 18B) coupled to the fourth (top) surface of the intermediate structure 18B, wherein the intermediate structure 18B is positioned between the plurality of active circuit elements 18A and the routing structure (16,22 above 18B);
a second die assembly 12,34 including—
a carrier substrate 12 including a first (bottom) surface and a second (top) surface opposite the first surface, and
a redistribution structure 34 (¶ 19) on or over the first (bottom) surface of the carrier substrate 12;
a thermal buffer structure 22 (between 12 and 14) between the first and second die assemblies, wherein the thermal buffer structure 22 (between 12 and 14) is coupled to the second (bottom) surface of the semiconductor substrate 14 of the semiconductor die 14+18A and to the second (top) surface of the carrier substrate 12, wherein a first distance from the intermediate structure 18B to the thermal buffer structure (22 between 12 and 14) is less than a second distance from the routing structure (22 above 18B) to the thermal buffer structure (see FIG. 1 annotated above, since the routing structure is further away from the thermal buffer than the intermediate structure),
wherein the first die assembly 14,18 has a first component threshold temperature (¶ 23), wherein the second die assembly 12,34 has a second component operating temperature that is greater than the first component threshold temperature (¶ 23), and wherein the thermal buffer structure 22 is configured to reduce transfer of heat from the second die assembly 12,34 to the first die assembly 14,18 (22 has low thermal conductivity (¶ 24,31), thus functions to reduce heat transfer from heat generating device 12 to 14,18); and
a plurality of interconnections 16,20 extending through at least the semiconductor substrate 14, the carrier substrate 12, and the thermal buffer structure 22, wherein the interconnections 16,20 electrically couple the active circuit elements 18A to the redistribution structure 34 via the routing structure (16,20 above 18B) (¶ 19).
Groothuis discloses the thermal buffer structure comprises an underfill 22 formed of a polymer having a low thermal conductivity (¶ 24,31). Groothuis does not explicitly disclose the thermal buffer structure comprises an epoxy molding compound.
However, Kim discloses (e.g. FIG. 4A) a chip stack comprising an underfill layer 420 having a low thermal conductivity (¶ 55) and may be formed of an epoxy molding compound (¶ 50).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Groothuis’s underfill material 22 using low thermal conductivity epoxy molding compound as taught by Kim to improve thermal insulation effect as desired by Groothuis. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
In re claim 2, Groothuis discloses (e.g. FIG. 1) wherein the thermal buffer structure 22 (e.g. 0.4 W/mK, ¶ 31) is less thermally conductive than the semiconductor substrate 14 (148 W/mK, ¶ 31). Kim discloses (e.g. FIGs. 4A-4B) wherein the thermal buffer structure 420 (e.g. EMC, ¶ 50, low thermal conductivity, ¶ 55) is less thermally conductive than the semiconductor substrate 110 (e.g. silicon, ¶ 28).
In re claim 3, as best understood, Groothuis discloses (e.g. FIG. 1) wherein the thermal buffer structure 22 (¶ 24, 31) comprises an underfill material, a non-conductive film, or a die attach film.
In re claim 4, Groothuis discloses (e.g. FIG. 1) wherein the redistribution structure 34 is configured to route signals between the active circuit elements 18B,18C and an external device (e.g. higher level packaging, ¶ 19).
In re claim 5, Groothuis discloses (e.g. FIG. 1) wherein the redistribution structure (structure under 12 including 34 and elements in between) is directly coupled to the carrier substrate 12.
In re claim 9, Groothuis discloses (e.g. FIG. 1) wherein the routing structure (e.g. 16 between 18A and 14) is thinner than the redistribution structure 34.
In re claim 11, Groothuis discloses (e.g. FIG. 1) wherein the intermediate structure 18B comprises a memory array (¶ 18).
In re claim 12, Groothuis discloses (e.g. FIG. 1) wherein the interconnections 16,20 include: (a) a plurality of first vias 20 extending through the semiconductor substrate 14, (b) a plurality of second vias 20 extending through the carrier substrate 12, and (c) a plurality of interconnect structures 16 extending through the thermal buffer structure 22 (between 12 and 14).
In re claim 19, Groothuis discloses (e.g. FIG. 1) a semiconductor device, comprising:
a semiconductor substrate 14 including a first (top) surface and a second (bottom) surface opposite the first surface;
a plurality of active circuit elements 18A at the first (top) surface of the semiconductor substrate 14;
an intermediate structure 18B including a third (bottom) surface and a fourth (top) surface opposite the third (bottom) surface, the third (bottom) surface facing the plurality of active circuit elements 18A, wherein the plurality of active circuit elements 18A are positioned between the third (bottom) surface of the intermediate structure 18B and the first (top) surface of the semiconductor substrate 14;
a routing structure (e.g. 16,22 above 18B) coupled to the fourth (top) surface of the intermediate structure 18B, wherein the intermediate structure 18B is positioned between the plurality of active circuit elements 18A and the routing structure (16,22 above 18B);
a thermal buffer structure 22 (between 12 and 14) including a first (bottom) surface and a second (top) surface opposite the first surface, the second (top) surface of the thermal buffer structure being coupled to the second (bottom) surface of the semiconductor substrate 14;
a redistribution structure 34 on or over the first (bottom) surface of the thermal buffer structure 22 (between 12 and 14),; and
a plurality of interconnections 16,20 extending through at least the semiconductor substrate 14 and the thermal buffer structure 22 (between 12 and 14), wherein the interconnections 16,20 electrically couple the active circuit elements 18A to the redistribution structure 34 via the routing structure (16,20 above 18B) (¶ 19),
wherein a first die assembly 14,18 of the semiconductor device including the plurality of active circuit elements 18A has a first component threshold temperature (¶ 23), wherein a second die assembly 12,34 of the semiconductor device including the redistribution structure 34 is spaced apart from the first die assembly 14,18 (spaced by a layer of 22 between 12 and 14) and has a second component operating temperature that is greater than the first component threshold temperature (¶ 23), and wherein the thermal buffer structure 22 (between 12 and 14) is configured to reduce transfer of heat from the second die assembly 12,34 to the first die assembly 14,18 (22 has low thermal conductivity (¶ 24,31), thus functions to reduce heat transfer from heat generating device 12 to 14,18).
Groothuis discloses the thermal buffer structure comprises an underfill 22 formed of a polymer having a low thermal conductivity (¶ 24,31). Groothuis does not explicitly disclose the thermal buffer structure comprises an epoxy molding compound.
However, Kim discloses (e.g. FIG. 4A) a chip stack comprising an underfill layer 420 having a low thermal conductivity (¶ 55) and may be formed of an epoxy molding compound (¶ 50).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Groothuis’s underfill material 22 using low thermal conductivity epoxy molding compound as taught by Kim to improve thermal insulation effect as desired by Groothuis. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
In re claim 22, Groothuis discloses (e.g. FIG. 1) wherein the thermal buffer structure 22 (e.g. 0.4 W/mK, ¶ 31) is less thermally conductive than the semiconductor substrate 14 (148 W/mK, ¶ 31). Kim discloses (e.g. FIGs. 4A-4B) wherein the thermal buffer structure 420 (e.g. EMC, ¶ 50, low thermal conductivity, ¶ 55) is less thermally conductive than the semiconductor substrate 110 (e.g. silicon, ¶ 28).
In re claim 23, Groothuis discloses (e.g. FIG. 1) further comprising a passivation layer 32 formed on the routing structure (16,20 above 18B).
In re claim 24, Groothuis discloses (e.g. FIG. 1) wherein the plurality of interconnections 16,20 extend through the active circuit elements 18A, and wherein the routing structure (16+22 above 18B) is configured to route signals from the active circuit elements 18A through the routing structure (16+22 above 18B) to the plurality of interconnections (e.g. 20 in 18C, here, the plurality of interconnections as broadly understood, is not limited to the interconnections within the active circuit elements, but could refer to interconnections above the routing structure, e.g. 20 in 18C above the “routing structure” as annotated in FIG. 1 above).
Claims 1-5, 9, 12, 19, and 22-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 2022/0013501 A1 (Kim) in view of Groothuis et al. US 2014/0015598 A1 (Groothuis).
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In re claim 1, Kim discloses (e.g. FIGs. 4A-4B, see annotated above) a semiconductor device, comprising:
a first die assembly 100 including—
a semiconductor die 110+123 including a semiconductor substrate 110 (¶ 28) having a first (bottom) surface 110b and a second (top) surface 110a opposite the first surface and a plurality of active circuit elements 123 (¶ 29) at the first (bottom) surface 110b of the semiconductor substrate 110,
an intermediate structure (e.g. an upper portion of circuit layer 120 including upper layers of insulating material 121 and metal 125, ¶ 29, see annotated figure above) including a third (top) surface facing the semiconductor die 110+123 and a fourth (bottom) surface opposite the third (top) surface and facing away from the semiconductor die 110+123, wherein the plurality of active circuit elements 123 are positioned between the third (top) surface of the intermediate structure (upper portion of 120) and the first (bottom) surface 110b of the semiconductor substrate 110, and
a routing structure (e.g. a lower portion of circuit layer 120 including lower layers of insulating material 121 and metal 125, ¶ 29) coupled to the fourth (bottom) surface of the intermediate structure (upper portion of 120), wherein the intermediate structure (upper portion of 120) is positioned between the plurality of active circuit elements 123 and the routing structure (lower portion of 120);
a second die assembly 200 including—
a carrier substrate 210 including a first (top) surface and a second (bottom) surface 210b opposite the first surface, and
a redistribution structure 260,270,280 on or over the first (top) surface of the carrier substrate 210;
a thermal buffer structure 420 (no specific “thermal buffer structure” claimed that would structurally distinguish over structure 420 having low thermal conductivity, ¶ 55) between the first and second die assemblies 100,200, wherein the thermal buffer structure 420 is coupled to the second (top) surface 110a of the semiconductor substrate 110 of the semiconductor die 110+123 and to the second (bottom) surface 210b of the carrier substrate 210, wherein a first distance from the intermediate structure (upper portion of 120) to the thermal buffer structure 420 is less than a second distance from the routing structure (lower portion of 120) to the thermal buffer structure 420 (since 420 is closer to the upper portion of 120), and wherein the thermal buffer structure 420 comprises an epoxy mold compound (¶ 50),
wherein the first die assembly 100 (e.g. memory circuit, ¶ 29) has a first component threshold temperature, wherein the second die assembly 200 (e.g. logic circuit 223, ¶ 40) has a second component operating temperature, and wherein the thermal buffer structure 420 is configured to reduce transfer of heat from the second die assembly 200 to the first die assembly 100 (structure 420 having low thermal conductivity reduces heat transfer by being physically spacing between the die assemblies 100,200); and
a plurality of interconnections 140,240,300 extending through at least the semiconductor substrate 110, the carrier substrate 210, and the thermal buffer structure 420, wherein the interconnections 140,240,300 electrically couple the active circuit elements 123 to the redistribution structure 260 via the routing structure (lower portion of 120, ¶ 33).
Kim discloses the first die assembly 100 can include memory circuit (¶ 29) and the second die assembly 200 can include logic circuit 223 (¶ 40). Kim does not explicitly disclose the second component operating temperature of the second die assembly 200 is greater than the first component threshold temperature of the first die assembly 100.
Groothius disclose (e.g. FIG. 1) a die stack comprising logic chip 12 and memory chips 14,18 (¶ 18), wherein the memory chips 14,18 has a first component threshold temperature (e.g. about 94°, ¶ 23), and the logic chip 12 has a second component operating temperature (e.g. about 101° C, ¶ 23) that is greater than the first component threshold temperature, and wherein the thermal buffer structure 22 (having low thermal conductivity, ¶ 24,31) is configured to reduce transfer of heat from the logic chip 12 to the memory chips 14,18.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Kim’s device as a stack of first die assembly 100 including memory circuit and a second die assembly 200 including logic chip to form a highly integrated memory device, such that the second die assembly 200 having the logic circuit has a second component operating temperature that is greater than a first component threshold temperature of the first die assembly 200 having memory circuit as taught by Groothius.
In re claim 2, Kim discloses (e.g. FIGs. 4A-4B) wherein the thermal buffer structure 420 (e.g. EMC, ¶ 50, low thermal conductivity, ¶ 55) is less thermally conductive than the semiconductor substrate 110 (e.g. silicon, ¶ 28). Groothuis discloses (e.g. FIG. 1) wherein the thermal buffer underfill 22 (e.g. 0.4 W/mK, ¶ 31) is less thermally conductive than the semiconductor substrate 14 (148 W/mK, ¶ 31).
In re claim 3, as best understood, Kim discloses (e.g. FIGs. 4A-4B) wherein the thermal buffer structure 420 (e.g. polymer underfill, e.g. EMC, ¶ 50) comprises an underfill material, a non-conductive film, or a die attach film. Groothuis discloses (e.g. FIG. 1) wherein the thermal buffer structure 22 (¶ 24, 31) comprises an underfill material, a non-conductive film, or a die attach film.
In re claim 4, Kim discloses (e.g. FIGs. 4A-4B) wherein the redistribution structure 260,270,280 is configured to route signals between the active circuit elements 123 and an external device (another die 200 above 430).
In re claim 5, Kim discloses (e.g. FIGs. 4A-4B) wherein the redistribution structure 260,270,280 is directly coupled to the carrier substrate 210.
In re claim 9, Kim discloses (e.g. FIGs. 4A-4B) wherein the routing structure (e.g. corresponding to one metal layer that connects the TSV 140 and the remainder of metal features to the device 123, which is a single metal layer thick) is thinner than the redistribution structure 260.
In re claim 12, Kim discloses (e.g. FIGs. 4A-4B) wherein the interconnections 140,240,300 include: (a) a plurality of first vias 140 extending through the semiconductor substrate 110, (b) a plurality of second vias 240 extending through the carrier substrate 210, and (c) a plurality of interconnect structures 300 extending through the thermal buffer structure 420.
In re claim 19, Kim discloses (e.g. FIGs. 4A-4B, see annotated above) a semiconductor device, comprising:
a semiconductor substrate 110 (¶ 19) having a first (bottom) surface 110b and a second (top) surface 110a opposite the first surface;
a plurality of active circuit elements 123 (¶ 20) at the first (bottom) surface 110b of the semiconductor substrate 110;
an intermediate structure (e.g. an upper portion of circuit layer 120 including upper layers of insulating material 121 and metal 125, ¶ 290, see annotated figure above) including a third (top) surface and a fourth (bottom) surface opposite the third surface, the third (top) surface facing the plurality of active circuit elements 123, wherein the plurality of active circuit elements 123 are positioned between the third (top) surface of the intermediate structure (upper portion of 120) and the first (bottom) surface 110b of the semiconductor substrate 110, and
a routing structure (e.g. a lower portion of circuit layer 120 including lower layers of insulating material 121 and metal 125, ¶ 29) coupled to the fourth (bottom) surface of the intermediate structure (upper portion of 120), wherein the intermediate structure (upper portion of 120) is positioned between the plurality of active circuit elements 123 and the routing structure (lower portion of 120);
a thermal buffer structure 420 (no specific “thermal buffer structure” claimed that would structurally distinguish over structure 420 having low thermal conductivity , ¶ 55) including a first (top) surface and a second (bottom) surface opposite the first (top) surface, the second (bottom) surface of the thermal buffer structure 420 being coupled to the second (top) surface of the semiconductor substrate 110, wherein the thermal buffer structure 420 comprises an epoxy mold compound (¶ 50);
a redistribution structure 260,270,280 on or over the first (top) surface of the thermal buffer structure 420; and
a plurality of interconnections 140,240,300 extending through at least the semiconductor substrate 110 and the thermal buffer structure 420, wherein the interconnections 140,240,300 electrically couple the active circuit elements 123 to the redistribution structure 260 via the routing structure (lower portion of 120, ¶ 33),
wherein a first die assembly 100 of the semiconductor device including the plurality of active circuit elements 123 (e.g. memory circuit, ¶ 29) has a first component threshold temperature, wherein a second die assembly 200 (e.g. logic circuit, ¶ 40) of the semiconductor device including the redistribution structure 260,270,280 is spaced apart from the first die assembly 100 (spaced by structure 420) and has a second component operating temperature, and wherein the thermal buffer structure 420 is configured to reduce transfer of heat from the second die assembly 200 to the first die assembly 100 (structure 420 having low thermal conductivity reduces heat transfer by being physically spacing between the die assemblies 100,200).
Kim discloses the first die assembly 100 can include memory circuit (¶ 29) and the second die assembly 200 can include logic circuit (¶ 40). Kim does not explicitly disclose the second component operating temperature of the second die assembly 200 is greater than the first component threshold temperature of the first die assembly 100.
Groothius disclose (e.g. FIG. 1) a die stack comprising logic chip 12 and memory chips 14,18 (¶ 18), wherein the memory chips 14,18 has a first component threshold temperature (e.g. about 94°, ¶ 23), and the logic chip 12 has a second component operating temperature (e.g. about 101° C, ¶ 23) that is greater than the first component threshold temperature, and wherein the thermal buffer structure 22 (having low thermal conductivity, ¶ 24,31) is configured to reduce transfer of heat from the logic chip 12 to the memory chips 14,18.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Kim’s device as a stack of first die assembly 100 including memory circuit and a second die assembly 200 including logic circuit to form a highly integrated memory device, such that the second die assembly 200 having the logic circuit has a second component operating temperature that is greater than a first component threshold temperature of the first die assembly 200 having memory chip as taught by Groothius.
In re claim 22, Kim discloses (e.g. FIGs. 4A-4B) wherein the thermal buffer structure 420 (e.g. EMC, ¶ 50, low thermal conductivity, ¶ 55) is less thermally conductive than the semiconductor substrate 110 (e.g. silicon, ¶ 28). Groothuis discloses (e.g. FIG. 1) wherein the thermal buffer underfill 22 (e.g. 0.4 W/mK, ¶ 31) is less thermally conductive than the semiconductor substrate 14 (148 W/mK, ¶ 31).
In re claim 23, Kim discloses (e.g. see FIGs. 1B & 4A) further comprising a passivation layer 130 formed on the routing structure (lower portion of 120).
In re claim 24, Kim discloses (e.g. see FIGs. 4A-4B, see annotated above) wherein the plurality of interconnections 140,240,300 extend through the active circuit elements 123, and wherein the routing structure (lower portion of 120) is configured to route signals from the active circuit elements 123 through the routing structure (lower portion of interconnection 120) to the plurality of interconnections 140,240,300 (¶ 33).
Response to Arguments
Applicant's arguments filed 6/30/2025 have been fully considered but they are not persuasive.
Regarding claims rejected over Choi, Applicant argues the combination of elements 15 and interposer substrate 10 does not teach “a semiconductor die” (Remark, page 9).
This is not persuasive. No specific “semiconductor die” has been claimed that would structurally distinguish over Choi teaching the die 10+15 including a semiconductor substrate 10 and a plurality of active circuit elements 15 at the first (top) surface of the semiconductor substrate 10 as recited in the claim. The term “semiconductor die” as generally understood, refer to a block of semiconductor material. The interposer 10 teaches a block of semiconductor substrate on which circuit elements 15 are disposed. Thus, the combination of 10 and 15 teaches the claimed “semiconductor die”.
Regarding claims rejected over Groothuis, Applicant argues the interconnections 16,20 do not electrically couple the active circuit element of die 18A to the package substrate 34 via the interconnects between 18B and 18C (Remark, page 10).
This is not persuasive. Groothuis teaches interconnections 16,20 is formed throughout the die stack including in 18C. The interconnections 16,20 collectively electrically couple the active circuit elements 18A to the redistribution structure 34. The routing structure (16,20 above 18B) is in the electrical path of all the interconnections 16,20 connecting 18A and 34. The term “via” is broadly understood to refer having electrical path through. However, the path does not need to be direct. There exists an electrical path from the active circuit elements 18A to the redistribution structure 34 through or via the routing structure 16,20 between 18B and 18C. E.g. one such path start from 18A routing up to interconnect 16,20 above 18A, passing through (i.e. via) routing structure between 18B and 18C, then routing back down to the redistribution structure 34. Therefore, Groothuis teaches the broadly claimed electrical path.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/YU CHEN/Primary Examiner, Art Unit 2815