DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is responsive to the amendment filed on 02/17/2026 Claims 1-30 are pending. The amendments have overcome the rejection under 35 U.S.C. 102 as set forth in previous office action.
Response to Arguments
In respond to Applicant’s argument regarding rejection 35 U.S.C. 101 on Remarks page 8, "claims 1, 11, and 21 are amended in a manner that Applicant respectfully submits renders the rejection moot. Moreover, the claims as amended are not directed to an abstract idea and would nevertheless integrate any alleged abstract idea into a practical application.”
Examiner respectfully disagrees because the amended claims 1, 11, and 21 recites one or more processors comprising circuitry to cause one or more threads to perform operations, such additional elements are recited at a high level of generality, e.g., computer components performing computer functions to process data, which amount to no more than mere instructions to apply the judicial exception using computer components (see MPEP 2106.05(f)). Such recitation fails to integrate the judicial exception into a practical application under step 2A prong two. See rejection below for details.
Applicant further asserted on page 8-9, “Claim therefore recites a particular technique for performing matrix multiplication that is significantly more than matrix multiplication itself, and that has the practical application of improving the performance of circuitry that performs matrix multiplication using the recited technique.”
Examiner respectfully disagrees because assuming the particular technique being referring to is “to perform a matrix multiplication and reduction operation of two or more matrices by at least by performing a plurality of hierarchical operations … order of a respective one of the plurality of hierarchical operations” as recited in the independent claims, but such technique is characterized as the abstract idea under step 2A prong two and MPEP 2106.05(a) “It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements.” and “it is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology”. Furthermore, as recognized by the applicant, that the improving the performance of circuitry that perform matrix multiplication using the recited technique. Thus, any arguably improvement, such as improving performance of circuitry, is a direct consequence of performing the abstract idea (e.g., the recited technique of performing matrix multiplication and reduction operation of two or more matrices), and according to the MPEP recited above, the recited technique (e.g., abstract idea) alone cannot provide the improvement. Accordingly, claims 1, 11, and 21 do not recite additional elements that integrates the judicial exception into a practical application or provide significantly more.
Applicant’s arguments, see page 9-10 on Remarks, filed 02/17/2026, with respect to claims 1, 11, and 21 have been fully considered and are persuasive. The rejection under 35 U.S.C. 102 has been withdrawn because Dakkak figure 4 illustrates a reduction algorithm having a plurality of hierarchical operations, such as warp level, block level, and grid level, and each level performs matrix multiplication to reduce the portions by multiplying matrix A by matrix P, see section 4 and figure 7, but Dakkak does not teach performing a matrix multiplication and reduction operation of two or more matrices by performing hierarchical operations that each comprising reduction of results of a matrix multiplication of respective sub-portions of two or more matrices.
Claim Objections
Claims 1-30 are objected to because of the following informalities:
Claim 1 line 6; claim 11 line 6; claim 21 line 6 “two or more matrices” should be “the two or more matrices” as antecedently recited.
Claim 2 line 9; claim 12 line 9; claim 22 line 8“one of the first plurality of sub-portions” should be “one of the first plurality of the sub-portions” as antecedently recited.
Claim 24 line 2-3 “the first plurality of sub-portions … the second plurality of sub-portions” should be “the first plurality of the sub-portions … the plurality of second sub-portions” as antecedently recited.
dependent claims are also objected for inheriting the same deficiencies in which claims they depend on.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2-10, 12-20, and 22-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 line 2-6; claim 12 line 2-6; claim 22 line 2-5 recite “performing a reduction operation of the MM of a first matrix of one or more matrices and a second matrix of the one or more matrices … represent,…the first matrix via a plurality of the sub-portions”. it is unclear whether the one or more matrices is part of the two or more matrices as antecedently recited in the independent claims or different matrices because the first matrix is part of the one or more matrices, but the first matrix is represented by a plurality of the sub-portions, which are the sub-portions of the two or more matrices. For examination purposes, Examiner interprets such limitation as “performing a reduction operation of the MM of a first matrix of the two or more matrices and a second matrix of the two or more matrices … represent,…the first matrix via a plurality of the sub-portions”. (support is found in figure 6 illustrates matrix A and matrix B). Note that if amending as interpreted, applicant must also amend Claim 1 line 6; claim 11 line 6; claim 21 line 6 to recite “the two or more matrices” to avoid potential 112(b) issue.
Claim 7 line 3; 17 line 3; claim 27 line 3 recite “the reduction operation”. it is unclear whether “the reduction operation” is referring to the reduction operation of two or more matrices as recited in claim 1 line 3, or the reduction of results of a matrix multiplication (MM) of respective sub-portions as recited in claim 1 line 5, or the reduction operation of the MM of a first matrix of one or more matrices and a second matrix of the one or more matrices as recited in claim 2 line 3-4, or the reduction operation of a result of a portion of the MM that involves one of the first plurality of sub-portions as recited in claim 2 line 9. Figure 6 illustrates step 645 to perform matrix element redistribution prior to reduction operation at higher hierarchical levels. For examination purposes, Examiner interprets such the reduction operation as a reduction operation at a higher hierarchical level. Claims 17 and 27 are rejected for the same reasons.
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-30 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract without significantly more.
Claim 1 recites an apparatus for performing a matrix multiplication and reduction operation of two or more matrices.
Under Prong One of Step 2A of the USPTO current eligibility guidance (MPEP 2106), the claim recites perform a matrix multiplication and reduction operation of two or more matrices by at least performing a plurality of hierarchical operations each comprising reduction of results of a matrix multiplication (MM) of respective sub-portions of two or more matrices, wherein sizes of the sub-portions in each of the plurality of hierarchical operations correspond to an order of a respective one of the plurality of hierarchical operations. such limitation covers mathematical calculations, relationship, and/or formula (e.g., performing multiplication and reduction operation on matrices, see at least figures 2-3, and 6 describing the concept of performing such mathematical operation in a plurality of hierarchical operations level). Therefore, the claim include limitations that fall within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim additionally recites one or more processors comprising circuitry to cause one or more threads. However, the additional elements are recited at a high level of generality, i.e., as a generic system having generic computer components to perform generic computer functions of processing data. Such element fails to provide a meaningful limitation on the judicial exception, and amount to no more than mere instructions to apply the exception using generic computer elements. Thus, the claim is directed to an abstract idea.
Under Step 2B, as discussed with respect to Prong Two of Step 2A, the additional elements in the claim amount no more than mere instructions to apply the exception using a generic component. The same conclusion is reached in step 2B, i.e., mere instruction to apply an exception on a generic element cannot integrate a judicial exception into a practical application at step 2A or provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception. Thus, the additional elements fail to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 2 further recites the plurality of hierarchical operations perform a reduction operation of the MM of a first matrix of one or more matrices and a second matrix of the one or more matrices, and represent, at each hierarchical operation of the plurality of hierarchical operations, the first matrix via a first plurality of the sub-portions; and apply, at the respective hierarchical operation, a reduction operation to a result of a portion of the MM that involves one of the first plurality of sub-portions, to generate a corresponding vector of two or more vectors. Such limitation covers mathematical calculations, relationship, and/or formula (e.g., performing matrix multiplication and reduction at a plurality of hierarchical levels, see at least figures 5-6). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 3 further recites represent the second matrix via a plurality of second sub-portions. Such limitation covers mathematical calculations, relationship, and/or formula (merely describes the second matrix for performing matrix multiplication operation). The claim does not recite additional elements that would integrate the judicial exception into a practical application under step 2A prong two, and provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 4 further recites in the respective hierarchical operation, a number of matrix elements in each of the first plurality of sub-portions is equal to a number of matrix elements in each of the second plurality of sub-portions. Such limitation covers mathematical calculations, relationship, and/or formula (e.g., performing matrices operation having similar dimension). The claim does not recite additional elements that would integrate the judicial exception into a practical application under step 2A prong two, and provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 5 further recites wherein to perform a hierarchical operation of a lowest hierarchical order, the MM operation of matrices of predetermined dimension. Such limitation covers mathematical calculations, relationship, and/or formula (e.g., performing matrices operation having a predetermined dimension).The claim further recites the one or more circuits are to use one or more instances of a hardware instruction, such additional element is recited at a high level of generality, i.e., as a computer component for performing computer function of executing an instruction, which amounts to no more than mere instructions to apply the judicial exception using computer component. Thus, The claim does not recite additional elements that would integrate the judicial exception into a practical application under step 2A prong two, and provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 6 further recite wherein the one or more circuits are to perform the hardware instruction using a plurality of the one or more threads, each thread of the one or more threads being associated with: a plurality of input matrix elements of each of matrices input into the hardware instruction; and a plurality of output matrix elements of a matrix output by the hardware instruction. Such additional element of performing hardware instruction using a plurality of threads, each thread being associated with input matrix elements and output matrix element of matrices are recited at a high level of generality and are at most considered as insignificant extra solution activity under step 2A prong two and are determined to be well-understood, routine and conventional under step 2B, see at least Dakkak, section 2.2 page 2 illustrates threads within a warp utilize multiple tensor cores concurrently to perform the mma_sync instruction. Mukunoki – NPL Automatic Thread-Block Size Adjustment for Memory-Bound BLAS Kernels on GPUs, section II page 378 describes execution model of CUDA is referred as to single instruction multiple thread (SIMT) model, a multiprocessor executes threads in a unit of 32 threads, the unit of 32 threads is called a warp, and all 32 threads in a warp perform the same instruction concurrently. Also see Gonzalo – NPL Automatic Generation of Warp-level primitives and Atomic Instructions for Fast and Portable Parallel Reduction on GPUs, figure 2 page 76 describes a CUDA block is broken down to 2 warps with 32 threads to perform operation in parallel. Thus, the additional element fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 7 further recites wherein the one or more circuits are to redistribute at least some of the plurality of output matrix elements to different threads of the one or more threads prior to an application of the reduction operation. Such additional element of redistribute data between different threads is recited at high level of generality and is at most considered as insignificant extra solution activity under step 2A prong two and is determined to be well-understood, routine and conventional under step 2B, see at least Gonzalo page 74 describes warp shuffle instructions, these instructions allow threads in the same warp to exchange private register values via execution unit data path, Mukunoki page 381 describes the use of warp shuffle instruction, Dakkak page 4 section 3 also describes warp level implemented using shuffle instruction that allow threads within a warp to share value via registers without using share memory. Thus, the additional element fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 8 further recites wherein the one or more circuits are to store the plurality of input matrix elements and the plurality of output matrix elements, associated with each thread of the one or more threads, in registers accessible by a respective thread of the one or more threads. Such additional element of storing the input matrix elements and output matrix elements associated with each threads in registers is considered as insignificant extra activity under step 2A prong two and is determined to be well-understood, routine and conventional under step 2B, see at least Hennessy, John L. et al. Computer Architecture : A Quantitative Approach, Elsevier Science & Technology., 2014. ProQuest Ebook Central, chapter 6 section 6.9 Multithreading: Exploiting Thread-Level Parallelism within a Processor page 609, describes multithreading, wherein the processor must duplicate the independent state of each thread. For example, a separate cope of the register file … are required for each thread. Thus, the additional element fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 9 further recites wherein to apply the reduction operation to the result of the portion of the MM operation, the one or more circuits are to multiply the result of the portion of the MM operation by an auxiliary matrix that comprises at least one of a row of zero elements or a column of zero elements. Such limitation covers mathematical calculations, relationship, and/or formula (e.g., performing reduction on matrix multiplication). The claim does not recite additional elements that would integrate the judicial exception into a practical application under step 2A prong two, and provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 10 further recites wherein the one or more circuits are to perform a hierarchical operation of a highest order using a kernel that is different from one or more kernels that are used to perform other hierarchical operations. Such additional element of using different kernel at different hierarchical operation is at most insignificant extra solution activity under step 2A prong two and is determined to be well-understood, routine and conventional under step 2B, see at least Dakkak page 2 section 2 listing 1 illustrates a kernel within a warp level, and section 4.3 page 6 describes grid level reduction involves two kernel launches, thus different kernel is used for different hierarchical. Gonzalo, page 76 right column describes Tangram generates a second kernel launch, at the grid level, or another device function call at the block level, thus at different level or hierarchical, different kernel is used. Mukunoki page 381 describes the use of kernels GEM-V, GEMV-T, and TRMV-LNN for different levels or hierarchical operations. Thus, the additional element fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 11-20 recite system claims having limitations similar to claims 1-10. Thus, they are rejected for the same reasons.
Claims 21-30 recites method claims that would practice on the apparatus claims 1-10. Thus, they are rejected for the same reasons.
Allowable Subject Matter
Claims 1-30 would be allowable if rewritten or amended to overcome the claim objections and rejections under 35 U.S.C. 101 and 112(b) set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 1, 11, and 21, the prior art of record does not teach or suggest a combination of limitations, including to perform a matrix multiplication and reduction operation of two or more matrices by performing a plurality of hierarchical operations each comprising reduction of results of a matrix multiplication (MM) of respective sub-portions of two or more matrices, wherein sizes of the sub-portions in each of the plurality of hierarchical operations correspond to an order of a respective one of the plurality of hierarchical operations.
Dakkak – NPL Accelerating Reduction and Scan Using Tensor Core Units – teaches an approach a reduction algorithm performed by Tensor Core units, wherein figure 4 illustrates a reduction algorithm having a plurality of hierarchical operations, such as warp level, block level, and grid level. Section 4 further teaches the reduction algorithm is done by performing mma operation that multiple a matrix A with a transpose of matrix P, and as illustrated in figure 4, each level performs reduction algorithm to generate an output, such that each level performs a matrix with a corresponding matrix P. Thus, Dakkak does not teach or suggest performing a multiplication reduction operation of two or more matrices by performing a plurality of hierarchical operations each comprising reduction of results of a matrix multiplication of respective sub-portions of two or more matrices.
Also see OA 04/28/2025 for other prior art of record, which also does not teach or suggest the limitations as required in the independent claims.
Conclusion
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