DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claims
Claims 1-7, 9-23 are pending. Claim 11 are withdrawn. Claim 8 is cancelled.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the when the semiconductor wafer is provided and before a photoresist layer is applied, the continuous through-opening is open from the first opening to the second opening, and neither the first opening nor the second opening is covered or closed by a layer extending across the respective opening in claim 1 and 22 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the such that the photoresist layer recesses an area around the continuous through-opening and the continuous through-opening remains open from the first opening to the second opening during the applying of the photoresist layer in claim 1 and 22 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claim 1 recites “when the semiconductor wafer is provided and before a photoresist layer is applied, the continuous through-opening is open from the first opening to the second opening, and neither the first opening nor the second opening is covered or closed by a layer extending across the respective opening” the first paragraph of the claim language and “such that the photoresist layer recesses an area around the continuous through-opening and the continuous through-opening remains open from the first opening to the second opening during the applying of the photoresist layer” in the second paragraph of the claim language.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-7, 9, 10, 12-23 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1. Claim recites the limitation “when the semiconductor wafer is provided and before a photoresist laver is applied, the continuous through-opening is open from the first opening to the second opening, and neither the first opening nor the second opening is covered or closed by a layer extending across the respective opening” in the first paragraph of the claim language, and the limitation “such that the photoresist layer recesses an area around the continuous through-opening and the continuous through-opening remains open from the first opening to the second opening during the applying of the photoresist layer” in the second paragraph of the claim language. The specification as originally filed lacks support for the limitations recited above.
Claims 2-7, 9-10, 12-21, 23 are rejected for dependence upon a 112(a) rejected instance claim.
Regarding claim 22. Claim 22 is rejected for the same analogous reasons as claim 1 above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7, 9, 10, 12-23 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1. Claim 1 recites the limitation "the respective opening" in the last line of the first paragraph. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-7, 9-10, 12-21, 23 are rejected for dependence upon a 112(b) rejected instance claim.
Regarding claim 22. Claim 22 is rejected for the same analogous reasons as claim 1 above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 6, 7, 9, 10, 12-18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Naber et al (U.S. 2015/0114462), Chary et al (U.S. 2017/0345955), Suarez et al (U.S. 2019/0013429), and Voss et al (U.S. 2015/0349152).
Regarding claim 1. Naber et al discloses a metallization method for a semiconductor wafer, the method comprising:
providing the semiconductor wafer (FIG. 1a, item 1) having a top side (FIG. 1a, item 1a) and a bottom side (FIG. 1a, item 1b) and a solar cell (Title), and at least one through-hole (FIG. 1a, item 2) forming a continuous through-hole (FIG. 1a, item 2) extending continuously through ([0016], i.e. providing a first via hole into the substrate, which first via hole extends from the first side towards or to the second side) the semiconductor wafer (FIG. 1a, item 1) from the top side (FIG. 1a, item 1a) to the bottom side (FIG. 1a, item 1a) with a continuous side wall (FIG. 1a, item 2 sidewall with item 1a and 1b ) and a circumference ([0016] diameter) that is oval ([0016]) in cross section, the continuous through-opening (FIG. 1a, item 2) having a first opening (FIG. 1a, top of item 2) at the top side (FIG. 1a, item 1a) and a second opening (FIG. 1a, bottom of item 2) at the bottom side (FIG. 1a, item 1b) of the semiconductor wafer (FIG. 1a, item 1), wherein when the semiconductor wafer (FIG. 1a, item 1) is provided and before (FIG. 1a, item 1) a photoresist layer is applied (FIG. 1a, shows no photo resist is on item 1), the continuous through-opening (FIG. 1a, item 2) is open ([0016]) from the first opening (FIG. 1a, top of item 2) to the second opening (FIG. 1a, top of item 2), and neither the first opening (FIG. 1a, top of item 2) nor the second opening (FIG. 1a, bottom item 2) is covered or closed by a layer extending (FIG. 1a, shows no layers cover nor layer extend over item 2) across the respective opening (FIG. 1a, item 2);
applying a photoresist layer in certain areas as a resist pattern via a printing method ([0010], i.e. photolithographic masking steps commonly applied in the manufacture of integrated circuits)
applying a metal layer to exposed regions of a surface of the semiconductor wafer ([0007], i.e. Applying a conductor material at parts of the first side and the second side of the substrate and into the first via hole to form a via through the substrate ;[0044] i.e. provide a metal-wrap-through (MWT) type solar cell)
Naber et al fails to explicitly disclose:
at least two solar cell stacks, each solar cell stack has a Ge substrate forming the bottom side of the semiconductor wafer, a Ge subcell, and at least two Ill-V subcells,
a resist pattern such that the photoresist layer recesses an area around the continuous through-opening and the continuous through-opening remains open from the first opening to the second opening during the applying of the photoresist layer
applying a flat metal layer to exposed regions the exposed regions being regions which are not covered with the photoresist layer, and to the photoresist layer; and
removing the resist pattern with the flat metal layer located thereon from the semiconductor wafer.
However, Chary et al teaches at least two solar cell stacks (FIG. 35A-C), each solar cell stack (FIG. 1) has a Ge substrate (FIG.13, item 1305; [0112], i.e. Materials used to form the substrate include, for example, germanium) forming the bottom (FIG. 13, items 1305) of the semiconductor wafer (FIG. 13, items 1304, 1305, and 1313),
applying a photoresist layer (FIG, 13, item 1314) in certain areas as a resist pattern via a printing method ([0122]) to the top side (FIG. 13, top of item 1313) of the semiconductor wafer (FIG. 13, item 1304, 1305, 1313);
a resist pattern (FIG, 13, item 1314) such that the photoresist layer (FIG, 13, item 1314) recesses an area (FIG, 13, item 1314) around the continuous through-opening (FIG. 13 shows item 1314 on each side of item 1310 and that item 1314 is higher than area around the TWV and therefore recesses an area around the through-hole) and the continuous through-opening (FIG. 13, item 1310) open ([0115]) from the first opening (FIG. 13, item 1305 with item 1310) to the second opening (FIG. 13, item 1304 with item 1310) during the applying ([0122]) of the photoresist layer (FIG. 13, item 1314)
applying a metal layer (FIG. 14, items 1417 and 1418) to exposed regions of the surface of the semiconductor wafer (FIG. 14, item 1405, 1413), the exposed regions being regions not covered (FIG. 14, item 1417) by photoresist layer (FIG. 14, item 1414), and to (FIG. 14, item 1418) the photoresist layer (FIG. 14, item 1414); and
removing the resist pattern (FIG. 14, item 1414 is removed from FIG. 15) with the metal layer part (FIG. 14, item 1418 is removed from FIG. 15) located thereon from the semiconductor wafer (FIG. 15, item 1505; [00123], i.e. Sacrificial metal 1418 and metal isolation resist pattern 1414 are then lifted off.. leading to the product shown in FIG. 15).
Since Naber et al and Chary et al teach solar cells, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the a metallization method for a semiconductor wafer as disclosed to modify Naber et al with the teachings of a resist pattern such that the photoresist layer recesses an area around the continuous through-opening and the continuous through-opening remains open from the first opening to the second opening during the applying of the photoresist layer, applying a flat metal layer to exposed regions the exposed regions being regions which are not covered with the photoresist layer, and to the photoresist layer; and removing the resist pattern with the flat metal layer located thereon from the semiconductor wafer as disclosed by Chary et al. The use of sacrificial metal and metal isolation resist pattern are then lifted off leading to the product shown in Chary et al provides for making the photovoltaic cells lighter and appropriate for space applications, simplifies fabrication of the TWV, and improves thermal properties (Chary et al, [0091]).
Naber et al and Chary et al fails to explicitly disclose:
each solar cell has a Ge subcell, and at least two Ill-V subcells, applying a flat metal layer, and removing the resist layer with the flat metal layer.
However Suarez et al teaches each solar cell (FIG. 2, item 4J) has a Ge sub-cell (FIG. 2, item Ge (active junction)), at least two III-V sub-cells (FIG. 2, item GaInNAsSB, item InGaAs,; [0046], i.e. In a 4J or higher-junction solar cell, an active germanium subcell lies underneath the GaInNAsSb subcell).
Since Naber et al, Chary et al and Suarez et al teach methods of manufacturing solar cells, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the metallization method as disclosed to modify Naber et al with the teaching of each solar cell has a Ge sub-cell, at least two III-V sub-cells as disclosed by Suarez et al. The use of an active germanium subcell lies underneath the GaInNAsSb subcell in Suarez et al to absorb lower energy of light (Suarez et al [0046]).
Suarez et al teaches each solar cell (FIG. 2, item 4J) has a Ge sub-cell (FIG. 2, item Ge (active junction)), at least two III-V sub-cells (FIG. 2, item GaInNAsSB, item InGaAs,; [0046], i.e. In a 4J or higher-junction solar cell, an active germanium subcell lies underneath the GaInNAsSb subcell).
Since Naber et al, Chary et al and Suarez et al teach methods of manufacturing solar cells, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the metallization method as disclosed to modify Naber et al and Chary et al with the teaching of each solar cell has a Ge sub-cell, at least two III-V sub-cells as disclosed by Suarez et al. The use of an active germanium subcell lies underneath the GaInNAsSb subcell in Suarez et al to absorb lower energy of light (Suarez et al [0046]).
Naber et al, Chary et al, and Suarez et al fails to explicitly disclose applying a flat metal layer, and removing the resist layer with the flat metal layer.
However, Voss et al teaches applying a flat metal layer (FIG. 2d, item 206; [0101], i.e. [0101] Since also the patterned first resist layer (203) is covered by the conductive seed layer (205), electroplating of the first metal or metal alloy layer (206) is also on this layer. The thickness of the first metal or metal alloy layer (206) should preferably not exceed 10 pm and more preferably not exceed 6 pm on top of the patterned first resist layer (203)),
and removing ([0102], i.e. In step (v) of the method according to the present invention, those parts of the first metal or metal alloy layer (206) which are plated on top of the patterned first resist layer (203) are etched away. At the same time, a similar amount (in terms of thickness of this layer) of the first metal and metal alloy layer (206) plated into the first openings (204) is also etched away. Step (v) of the method according to the present invention is illustrated in FIG. 2e.) the resist layer (FIG. 2b-d, item 203) with the flat metal layer (FIG. 2d-g, item 206)
Since Naber et al, Chary et al, Saurez et al, and Voss et al teach methods of manufacturing solar cells, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the metallization method as disclosed to modify Naber et al, Chary et al, and Saurez et al with applying a flat metal layer, and removing the resist layer with the flat metal layer as disclosed by Voss et al. The use of the patterned first resist layer is covered by the conductive seed layer, electroplating of the first metal or metal alloy layer is also on this layer in Voss et al to provide a homogeneous thickness distribution of plated conducting lines, contact pads and solder pads (Voss et al [0046])
Regarding claim 2. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 1 above.
Chary et al further discloses further comprising after said applying ([0122], i.e. in FIG. 13, TWV metal isolation resist pattern 1314 can be formed with a photosensitive polymer) the photoresist layer (FIG. 13) and before said applying the metal layer (FIG. 15, item 1517), finely patterning the photoresist layer by a photolithographic method ([0122], i.e. This patterning is carried out, for example, by photolithography techniques).
Voss et al discloses the flat metal layer (FIG. 2d, item 206).
Regarding claim 3. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 1 above.
Chary et al further discloses wherein the photoresist layer is formed as a negative resist layer or as a positive resist layer, and wherein the resist pattern is formed in each case as an inverse of a trace diagram ([0122], i.e. In FIG. 13, TWV metal isolation resist pattern 1314 can be formed with a photosensitive polymer This patterning is carried out, for example, by photolithography techniques).
Regarding claim 4. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 1 above.
Chary et al further discloses wherein the photoresist layer recesses an area around the through-holes (FIG. 13 shows item 1314 on each side of item 1310 and that item 1314 is higher than area around the TWV and therefore recesses an area around the through-hole).
Regarding claim 6. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 1 above.
Chary et al further discloses wherein the through-holes of the semiconductor wafer provided have a first diameter ([0125]) of at most 1 mm ([0125]) and at least 300 um ([0125]) or at least 400 um ([0125]) or at least 450 um ([0125]) at an edge adjacent to the top side ([0125]) of the semiconductor wafer, and have a second diameter ([0125]) of at most 500 um ([0125]) and of at least 50 um ([0125]) or at least 100 um ([0125]) at an edge adjacent to the bottom side ([0125]) of the semiconductor wafer,
[0125] A TWV can be, for example, from 20 μm to 50 μm deep, or from 10 μm to 200 μm deep. A TWV can have a width, for example, from about 10 μm to 500 μm, from 10 μm to 400 μm, from 100 μm to 400 μm, or from 100 μm to 250 μm. A TWV can be characterized, for example, by an aspect ratio from 0.5 to 1.5 from 0.8 to 1.2, or from 0.9 to 1.1.
and wherein the semiconductor wafer provided has a total thickness of at most 300 um ([0060]) and of at least 90 um ([0060]) or of at least 150 um or of at least 200 um ([0060], i.e. Using through-wafer-vias, the coverglass can be applied to the front surface of the photovoltaic cells at the wafer-level. The coverglass can be used as a carrier to thin the semiconductor substrate. For example, the epitaxial layers of a multijunction solar cell can be grown on a thick substrate such as a 140 μm thick Ge substrate as is usually the case for conventional three junction space cells. The thickness of the substrate can be reduced, for example, from 140 μm to 50 μm for Ge, and down to as thin as 10 μm for GaAs substrates. As an example, a SMCC with a solar cell on a GaAs substrate thinned-down to 50 μm, results in a 43% reduction in the mass of the photovoltaic cell, relative to a conventional cell on a 140 μm-thick Ge substrate).
Regarding claim 7. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 1 above.
Chary et al further discloses wherein the resist pattern has at least one auxiliary section (FIG. 14, item 1414) extending to an edge of the semiconductor wafer (FIG. 14, item 1405), wherein the removal of the resist layer is started with the auxiliary section ([00123], i.e. Sacrificial metal 1418 and metal isolation resist pattern 1414 are then lifted off.. leading to the product shown in FIG. 15).
Regarding claim 9. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 1 above.
Chary et al further discloses wherein the photoresist layer is finely patterned by a photolithographic method (FIG. 13, item 1414) before the metal layer (FIG. 14, item 1418) is applied ([0122], i.e. In FIG. 13, TWV metal isolation resist pattern 1314 can be formed with a photosensitive polymer This patterning is carried out, for example, by photolithography techniques).
Voss et al discloses the flat metal layer (FIG. 2d, item 206)
Regarding claim 10. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 1 above.
Naber et al further discloses wherein the semiconductor wafer provided has a dielectric insulation layer (FIG. 1g, item 7) covering the side wall (FIG. 1g, item 11 and 12) of the through-hole (FIG. 1g, item 2) and a region adjacent (FIG. 1g, item 3) to the through-hole (FIG. 1g, item 2) on the top side (FIG. 1g, item 1203) of the semiconductor wafer (FIG. 1g, item 2) and a region (FIG. 1g, item 5), adjacent to the through-hole (FIG. 1g, item 2) on the bottom side (FIG. 1g, item 1b) of the semiconductor wafer (FIG. 1g, item 1).
Regarding claim 12. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 1 above.
Chary et al further wherein the metal layer (FIG. 14, items 1418, or 1401) extends along the bottom side (FIG. 14, item 1405) or the top side (FIG. 14, item 1404) of the semiconductor wafer (FIG. 14, item 1404 and 1405).
Voss et al discloses the flat metal layer (FIG. 2d, item 206)
Regarding claim 13. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 1 above.
Chary et al discloses the solar cell stack (FIG. 35A-C; [0039] FIGS. 35A-35C show solar cell panel utilization using full wafers (35A), half wafers (35B), and SMCCs provided by the present disclosure (35C)).
Voss et al further discloses wherein the photoresist layer (FIG. 2b, item 203) extends to edges of each solar cell (FIG. 2a-b, item 201)
Regarding claim 14. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 1 above.
Chary et al discloses the solar cell stacks (FIG. 35A-C; [0039] FIGS. 35A-35C show solar cell panel utilization using full wafers (35A), half wafers (35B), and SMCCs provided by the present disclosure (35C)).
Voss et al further discloses wherein the photoresist layer is connected across all of the solar cell ([0011] (ii) forming a first resist layer (203) on at least one side of the solar cell substrate (201)).
Regarding claim 15. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 1 above.
Voss et al further discloses wherein the photoresist layer (FIG. 2b, item 203) is a flat layer extending to an edge ([0011] (ii) forming a first resist layer (203) on at least one side of the solar cell substrate (201)) of the semiconductor wafer (FIG. 2a-b, item 201).
Regarding claim 16. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 1 above.
Chary et al further wherein said removing the resist pattern comprises continuously removing an entirety of the resist pattern (FIG. 15 shows all resist , item 1414, is removed).
Regarding claim 17. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 1 above.
Naber et al further wherein a top side (FIG. 1g, item 1a) of the at least one through- hole (FIG. 1g, item 2) has a first diameter (FIG. 1g, item A) and a bottom side (FIG. 1g, item 1b) of the at least one through-hole (FIG. 1g, item 2) has a second diameter (FIG. 1g, item B) and the first diameter (FIG. 1g, item A) is larger ([0046]) than the second diameter (FIG. 1g, item B).
Regarding claim 18. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 1 above.
Naber et al further discloses comprising coating a sidewall (FIG. 1g, item 11 and 12) of the through-hole (FIG. 1g, item g) and a region adjacent (FIG. 1g, item 3) to the through-hole (FIG. 1g, item 2) on the top side (FIG. 1g, item 1a) and a region (FIG. 1g, item 5) adjacent to the through-hole (FIG. 1g, item 2) on the bottom side (FIG. 1g, item 1b) with a dielectric insulation layer (FIG. 1g, item 7).
Regarding claim 20. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 18 above.
Chary et al further discloses wherein, on the bottom side (FIG. 13, item 1309), the photoresist layer (FIG. 13, item 1314) extends over the dielectric insulation layer (FIG. 13, item 1313).
Claim 5 rejected under 35 U.S.C. 103 as being unpatentable over (Naber et al (U.S. 2015/0114462), Chary et al (U.S. 2017/0345955), Suarez et al (U.S. 2019/0013429), and Voss et al (U.S. 2015/0349152) as applied to claim 1 above, and further in view of Schultz-Wittman et al (U.S. 2011/0132443).
Regarding claim 5. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 1 above.
Chary et al discloses wherein the printing method ([0122])
Chary et al fails to explicitly disclose wherein the printing method is an inkjet method.
However, Schultz-Wittman et al teaches wherein the printing method is an inkjet method ([0025],i.e. inexpensive technologies for the deposition of a structured resist can be used, such as inkjet).
Since Naber et al, Chary et al, Suarez et al, Voss et al and Schultz-Wittman et al teach photovoltaic devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the a metallization method for a semiconductor wafer as disclosed to modify Naber et al, Chary et al, Suarez et al, and Voss et al with the teachings of the wherein the printing method is an inkjet method as disclosed by Schultz-Wittman et al. The use of inexpensive technologies for the deposition of a structured resist can be used, such as inkjet in Schultz-Wittman et al provides for avoiding the high cost and process complexity of a photo-lithographically defined resist (Schultz-Wittman et al, [0025]).
Claims 19, 21 are rejected under 35 U.S.C. 103 as being unpatentable over Naber et al (U.S. 2015/0114462), Chary et al (U.S. 2017/0345955), Suarez et al (U.S. 2019/0013429), and Voss et al (U.S. 2015/0349152) as applied to claim 18 above, and further in view of Von Malm et al (U.S. 2017/0062351)
Regarding claim 19. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 18 above.
Naber et al fails to explicitly disclose wherein, on the top side, the dielectric insulation layer is spaced apart from the photoresist layer.
However, Von Malm et la teaches wherein, on the top side, the dielectric insulation layer (FIG. 1I, item 73) is spaced apart (FIG. 1I, the photoresist on the top side, item 8, is spaced apart from the dielectric insulation layer, item 73, [0075], i.e. [0075] a masking layer 8, for example a photo resist layer is subsequently applied to the semiconductor layer sequence 2. The masking layer is designed in such a way that openings 81 are formed in the masking layer, wherein the cut-outs 29 are completely arranged within the openings 81 in a top view of the semiconductor layer sequence 2. [0076], i.e. material of the separating layer 73 is removed by means of another directionally selective method.) from the photoresist layer (FIG. 1I, item 8).
Since Naber et al, Chary et al, Suarez et al, Voss et al and Von Malm et al teach Solar cells, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the metallization method for a semiconductor wafer as disclosed to modify Chary et al, Suarez et al, and Voss et al with the wherein, on the top side, the dielectric insulation layer is spaced apart from the photoresist layer as disclosed by Von Malm et al. The use of masking layer is designed in such a way that openings are formed in the masking layer, wherein the cut-outs are completely arranged within the openings in a top view of the semiconductor layer sequence in Von Malm et al provides for with increasing distance from the semiconductor layer sequence, the cross-section of the openings decreases, such that an undercut area is created (Von Malm, [0075]).
Regarding claim 21. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 18 above.
Chary et al further discloses on the bottom side (FIG. 13, item 1309), the photoresist layer (FIG. 13, item 1314) extends over the dielectric insulation layer (FIG. 13, item 1313).
Chary et al fails to explicitly disclose wherein, on the top side, the dielectric insulation layer is spaced apart from the photoresist layer.
However, Von Malm et la teaches wherein, on the top side, the dielectric insulation layer (FIG. 1I, item 73) is spaced apart (FIG. 1I, the photoresist on the top side, item 8, is spaced apart from the dielectric insulation layer, item 73, [0075], i.e. [0075] a masking layer 8, for example a photo resist layer is subsequently applied to the semiconductor layer sequence 2. The masking layer is designed in such a way that openings 81 are formed in the masking layer, wherein the cut-outs 29 are completely arranged within the openings 81 in a top view of the semiconductor layer sequence 2. [0076], i.e. material of the separating layer 73 is removed by means of another directionally selective method.) from the photoresist layer (FIG. 1I, item 8).
Since Naber et al, Chary et al, Suarez et al, Voss et al, and Von Malm et al teach Solar cells, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the metallization method for a semiconductor wafer as disclosed in Chary et al with the wherein, on the top side, the dielectric insulation layer is spaced apart from the photoresist layer as disclosed by Von Malm et al. The use of masking layer is designed in such a way that openings are formed in the masking layer, wherein the cut-outs are completely arranged within the openings in a top view of the semiconductor layer sequence in Von Malm et al provides for with increasing distance from the semiconductor layer sequence, the cross-section of the openings decreases, such that an undercut area is created (Von Malm, [0075]).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Naber et al (U.S. 2015/0114462), Chary et al (U.S. 2017/0345955), Suarez et al (U.S. 2019/0013429), and Voss et al (U.S. 2015/0349152) as applied to claim 1 above, and further in view of Hua et al (U.S. 2006/0273430)
Regarding claim 23. Naber et al, Chary et al, Suarez et al, and Voss et al discloses all the limitations of the method according to claim 1 above.
Naber et al disclose the photoresist pattern ([0010], i.e. photolithographic masking steps) and the metal layer ([0044], i.e. provide a metal-wrap-through (MWT) type solar cell)
Voss et al discloses the flat metal layer (FIG. 2d, item 206)
Naber et al, Chary et al, Suarez et al, and Voss et al fails to explicitly disclose wherein the metal layer remaining after said removing the resist pattern extends over the continuous side wall of the through-hole but does not cover the first opening and does not cover the second opening
Hau et al teaches wherein the metal layer (FIG. 5, item 51, 53; [0073]) remaining after said removing the resist pattern ([0075]) extends over the continuous side wall of the through-hole but does not cover the first opening and does not cover the second opening ([0083])
Since Naber et al, Chary et al, Suarez et al, Voss et al, and Hua et al teach wafer interconnects, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the metallization method for a semiconductor wafer as disclosed to modify Naber et al, Chary et al, Suarez et al and Voss et al with the teachings of the wherein the metal layer remaining after said removing the resist pattern extends over the continuous side wall of the through-hole but does not cover the first opening and does not cover the second opening as disclosed by Hua et al. The use of the isometric view of a through-wafer hole, low aspect ratio electrical interconnection, the fashioned through-wafer hole interconnections include a vertical or substantially vertical portion and a low-aspect ratio side-wall portion, the through-wafer holes consist of, from the surface of the silicon substrate, successive layers of silicon dioxide, UBM, and metal/solder material in Hua et al provides for Electrical interconnections on the front surface of the base wafer are electrically-coupled to electrical interconnections on the front surface of the cap wafer using through-wafer electrical interconnections (Hua et al, [0015]).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Naber et al (U.S. 2015/0114462), Chary et al (U.S. 2017/0345955), Suarez et al (U.S. 2019/0013429), Voss et al (U.S. 2015/0349152), and Hua et al (U.S. 2006/0273430).
Regarding claim 22. Naber et al discloses a metallization method for a semiconductor wafer, the method comprising:
providing the semiconductor wafer (FIG. 1a, item 1) having a top side (FIG. 1a, item 1a) and a bottom side (FIG. 1a, item 1b) and a solar cell (Title) and at least one through-hole (FIG. 1g, item 2) forming ([0016]) a continuous through opening (FIG. 1g, item 2) extending continuously through ([0016], i.e. providing a first via hole into the substrate, which first via hole extends from the first side towards or to the second side) the semiconductor wafer (FIG. 1a, item 1) from the top side (FIG. 1a, item 1a) to the bottom side (FIG. 1g, item 1b) the continuous through opening (FIG. 1a, item 2) having a first opening (FIG. 1g, item A) at the top side (FIG. 1a, item 1a) and a second opening (FIG. 1a, item B) at the bottom side (FIG. 1a, item 1b) of the semiconductor wafer (FIG. 1a, item 1), wherein, when the semiconductor wafer (FIG. 1a, item 1) is provided and before (FIG. 1a, item 1) a photoresist layer is applied (FIG. 1a, shows no photo resist is on item 1), the continuous through-opening (FIG. 1a, item 2) is open ([0016]) from the first opening (FIG. 1a, top of item 2) to the second opening (FIG. 1a, top of item 2), and neither the first opening (FIG. 1a, top of item 2) nor the second opening (FIG. 1a, bottom item 2) is covered or closed by a layer extending (FIG. 1a, shows no layers cover or closed by a layer extend over item 2) across the respective opening (FIG. 1a, item 2)
applying a photoresist layer in certain areas as a resist pattern via a printing method ([0010], i.e. photolithographic masking steps commonly applied in the manufacture of integrated circuits)
applying a metal layer to exposed regions of a surface of the semiconductor wafer ([0007], i.e. Applying a conductor material at parts of the first side and the second side of the substrate and into the first via hole to form a via through the substrate ;[0044] i.e. provide a metal-wrap-through (MWT) type solar cell)
Naber et al fails to explicitly disclose:
at least two solar cell stacks, each solar cell stack has a Ge substrate forming the bottom side of the semiconductor wafer, a Ge subcell, and at least two Ill-V subcells,
as a resist pattern to the top side and bottom side of the semiconductor wafer such that the photoresist layer recesses an area around the continuous through-opening and the continuous through-opening remains open from the first opening to the second opening during the applying of the photoresist layer
applying a flat metal layer to exposed regions of the top side and the bottom side of the semiconductor wafer, the exposed regions being regions not covered by the photoresist layer, and to the photoresist layer; and
removing the resist pattern with the flat metal layer located thereon from the semiconductor wafer.
However, Chary et al teaches at least two solar cell stacks (FIG. 35A-C), each solar cell stack (FIG. 1) has a Ge substrate (FIG.13, item 1305; [0112], i.e. Materials used to form the substrate include, for example, germanium) forming of the semiconductor wafer (FIG. 13, items 1304 and 1305),
a resist pattern (FIG, 13, item 1314) to at least the top side (FIG, 13, item 1309) of the semiconductor wafer (FIG. 11, items 1304 and 1305) such that the photoresist layer (FIG, 13, item 1314) recesses an area (FIG, 13, item 1314) around the continuous through-opening (FIG. 13 shows item 1314 on each side of item 1310 and that item 1314 is higher than area around the TWV and therefore recesses an area around the through-hole) and the continuous through-opening (FIG. 13, item 1310) open ([0115]) from the first opening (FIG. 13, item 1305 with item 1310) to the second opening (FIG. 13, item 1304 with item 1310) during the applying ([0122]) of the photoresist layer (FIG. 13, item 1314)
applying a metal layer (FIG. 14, items 1417 and 1418) to exposed regions of the top side (FIG. 14, items 1409) of the semiconductor wafer (FIG. 14, item 1405, 1413), the exposed regions being regions not covered (FIG. 14, item 1417) by photoresist layer (FIG. 14, item 1414), and to (FIG. 14, item 1418) the photoresist layer (FIG. 14, item 1414); and
removing the resist pattern (FIG. 14, item 1414 is removed from FIG. 15) with the metal layer part (FIG. 14, item 1418 is removed from FIG. 15) located thereon from the semiconductor wafer (FIG. 15, item 1505; [00123], i.e. Sacrificial metal 1418 and metal isolation resist pattern 1414 are then lifted off.. leading to the product shown in FIG. 15).
Since Naber et al and Chary et al teach methods of manufacturing solar cells, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the a metallization method for a semiconductor wafer as disclosed to modify Naber et al with the teachings of at least two solar cell stacks, each solar cell stack has a Ge substrate forming the bottom side of the semiconductor wafer, a resist pattern such that the photoresist layer recesses an area around the continuous through-opening and the continuous through-opening open from the first opening to the second opening during the applying of the photoresist layer, applying a metal layer to exposed regions of the top side of the semiconductor wafer, the exposed regions being regions not covered by photoresist layer, and to the photoresist layer; and removing the resist pattern with the metal layer located thereon from the semiconductor wafer as disclosed by Chary et al. The use of sacrificial metal and metal isolation resist pattern are then lifted off leading to the product shown in Chary et al provides for making the photovoltaic cells lighter and appropriate for space applications, simplifies fabrication of the TWV, and improves thermal properties (Chary et al, [0091]).
Naber et al and Chary et al fails to explicitly disclose:
each solar cell has a Ge subcell, and at least two Ill-V subcells, a Ge substrate forming the bottom side of the semiconductor wafer, applying a flat metal layer, and removing the resist layer with the flat metal layer, photoresist and metal layer on the bottom side of the semiconductor wafer.
However Suarez et al teaches each solar cell (FIG. 2, item 4J) has a Ge sub-cell (FIG. 2, item Ge (active junction)), at least two III-V sub-cells (FIG. 2, item GaInNAsSB, item InGaAs,; [0046], i.e. In a 4J or higher-junction solar cell, an active germanium subcell lies underneath the GaInNAsSb subcell), a Ge substrate forming the bottom side of the semiconductor wafer ([0045], i.e. the solar cells may be formed on a germanium substrate).
Since Naber et al, Chary et al and Suarez et al teach methods of manufacturing solar cells, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the metallization method as disclosed to modify Naber et al with the teaching of each solar cell has a Ge sub-cell, at least two III-V sub-cells as disclosed by Suarez et al. The use of an active germanium subcell lies underneath the GaInNAsSb subcell in Suarez et al to absorb lower energy of light (Suarez et al [0046]).
Naber et al, Chary et al, and Suarez et al fails to explicitly disclose applying a flat metal layer, and removing the resist layer with the flat metal layer, photoresist and metal layer on the top side of the semiconductor wafer.
However, Voss et al teaches applying a flat metal layer (FIG. 2d, item 206; [0101], i.e. [0101] Since also the patterned first resist layer (203) is covered by the conductive seed layer (205), electroplating of the first metal or metal alloy layer (206) is also on this layer. The thickness of the first metal or metal alloy layer (206) should preferably not exceed 10 pm and more preferably not exceed 6 pm on top of the patterned first resist layer (203)),
and removing ([0102], i.e. In step (v) of the method according to the present invention, those parts of the first metal or metal alloy layer (206) which are plated on top of the patterned first resist layer (203) are etched away. At the same time, a similar amount (in terms of thickness of this layer) of the first metal and metal alloy layer (206) plated into the first openings (204) is also etched away. Step (v) of the method according to the present invention is illustrated in FIG. 2e.) the resist layer (FIG. 2b-d, item 203) with the flat metal layer (FIG. 2d-g, item 206)
Since Naber et al, Chary et al, Saurez et al, and Voss et al teach methods of manufacturing solar cells, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the metallization method as disclosed to modify Naber et al, Chary et al, and Saurez et al with applying a flat metal layer, and removing the resist layer with the flat metal layer as disclosed by Voss et al. The use of the patterned first resist layer is covered by the conductive seed layer, electroplating of the first metal or metal alloy layer is also on this layer in Voss et al to provide a homogeneous thickness distribution of plated conducting lines, contact pads and solder pads (Voss et al [0046])
Naber et al, Chary et al, Suarez et al, and Voss et al fails to explicitly disclose a photoresist and metal layer on the top side of the semiconductor wafer.
However, Hua et al teaches a photoresist and metal layer on the top side of the semiconductor wafer ([0073], As shown in FIG. 3G, the metal/solder mixture will also be deposited to cover or adhere to the exposed, in the electrical contact region 48 between photo-resist portions 45 and 46 on the front surface 33, and in the electrical insulation region 59 between photo-resist portions 44 and 45 on the front surface 33).
Since Naber et al, Chary et al, Suarez et al, Voss et al, and Hua et al teach wafer interconnects, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the metallization method for a semiconductor wafer as disclosed to modify Naber et al, Chary et al, Suarez et al and Voss et al with the teachings of the photoresist and metal layer on the top and bottom side of the semiconductor wafer as disclosed by Hua et al. The use of the metal/solder mixture will also be deposited to cover or adhere to the exposed, in the electrical contact region 48 between photo-resist portions 45 and 46 on the front surface 33, and in the electrical insulation region 59 between photo-resist portions 44 and 45 on the front surface 33 in Hua et al provides for Electrical interconnections on the front surface of the base wafer are electrically-coupled to electrical interconnections on the front surface of the cap wafer using through-wafer electrical interconnections (Hua et al, [0015]).
Response to Arguments
Applicant's arguments filed July 30, 2026 have been fully considered but they are not persuasive.
On page 11 of applicant’s remarks, applicant respectfully request that claim 23 be rejoined and examined.
Examiner respectfully indicates that claim 23 has been rejoined and examined.
On page 15 of applicant’s remarks, applicant appears to argue that Nadar does not disclose a metallization process.
Examiner respectfully disagrees with applicant’s assertion. Examiner respectfully points out that Naber et al teaches applicant’s alleged metallization process in [0007] and [0049].
On page 16 of applicant’s remarks applicant appears to argue that Nadar does not disclose applying a flat metal layer to regions not covered by the photoresist layer and to the photoresist layer, removing the resist pattern together with the flat metal layer located thereon, a Ge substrate, a Ge subcell, and at least two Ill-V subcells. These are not minor omissions; they are important features of the claimed process.
Examiner respectfully points out that Chary et al teaches applying a metal layer to regions not covered by the photoresist layer and to the photoresist layer, removing the resist pattern together with the metal layer located thereon, a Ge substrate. Examiner respectfully further points out that Saurez et al teaches Ge substrate, a Ge subcell, and at least two Ill-V subcells. Voss et al teaches a flat metal layer. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On pages 18-21 of applicant’s remarks, applicant appears to argue that Chary et al does not disclose a continuous through-hole in figures 5-11.
Examiner respectfully points out that figures 5-11 of Chary et al was not used and that Chary et al teaches a continuous through hole in FIG. 13-14 with the process methods of the photoresist and metal. Furthermore, Naber et al discloses a continuous through-hole. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On pages 19-20 of applicant’s remarks, applicant appears to remarks that one of ordinary skill in the art would not modify Chary’s backside TWV process based on the open silicon via of Naber et al.
Examiner respectfully points out that the Nader et al was modified based upon the photoresist layer and metal layer of Chary et al.
On page 21 of applicant’s remarks, applicant appears to argue that Chary et al’s photolithography techniques are not a printing method.
Examiner respectfully point out that applicant has not claimed any specific printing method that does not read upon the photolithography techniques of the prior art.
On page 22 of applicant’s remarks, applicant appears to argue that Chary et al does not disclose a printing method to apply the resist pattern so that the already present though-contact holes can be reliably recessed.
Examiner respectfully disagrees with applicant’s assertion. Examiner respectfully points out that Chary teaches applicant’s alleged limitation in the rejection cited above.
On page 22 of applicant’s remarks, applicant appears to argue that Chary et al does not disclose a frontside metallization of a wafer already having a continuous through-opening.
Examiner respectfully disagrees with applicant’s assertion. Examiner respectfully points out that Chary teaches applicant’s alleged limitation in the rejection cited above.
On page 23 of applicant’s remarks, applicant appears to argue that Chary is read in hindsight.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
On page 23 of applicant’s remarks, applicant appears to argue that Chary et al fails to disclose for claim 2, first printing a photoresist pattern on a wafer having a pre-existing continuous through-opening and then fine-patterning that printed photo resist pattern.
Examiner respectfully disagrees with applicant’s assertion. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., first printing a photoresist pattern on a wafer having a pre-existing continuous through-opening) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
However, this limitation is claimed in claim 1, of which both Naber et al and Chary et al discloses first printing a photoresist pattern on a wafer having a pre-existing continuous through-opening. Furthermore, Chary et al teaches then fine-patterning that printed photo resist pattern.
On page 23 of applicant’s remarks, applicant appears to argue that Suarez does not disclose the limitations that are disclosed by Naber et al and Chary et al.
Examiner respectfully point out that Naber et al and Chary et al discloses the limitations cited by Naber et al and Chary et al. Saurez et al teaches the Ge substrate, a Ge subcell, and at least two Ill-V subcells. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 24 of applicant’s remarks, applicant appears to argue there is no motivation to combine Saurez with Naber et al and Chary et al
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Naber et al, Chary et al and Suarez et al teach methods of manufacturing solar cells.
On page 24 of applicant’s remarks, applicant argues that Voss does not disclose the claimed removal step.
Examiner respectfully points out that Chary et al teaches the claimed removal step. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 25 of applicant’s remarks, applicant appears to argue none of these references teaches or suggest the required base sequence providing a Ge/I1I-V multijunction semiconductor wafer having a pre-existing open continuous through-opening, printing a photoresist layer while recessing that throughopening, applying a flat metal layer to exposed regions not covered by the photoresist layer and to the photoresist layer, and removing the resist pattern with the metal located thereof.
Examiner respectfully disagrees with applicant’s assertion as Naber et al, Chary et al, and Voss et al suggest and teach applicant’s alleged sequence.
On page 25 of applicant’s remarks, applicant’s appears to argue there is no rational to modifying Chary with Naber.
Examiner respectfully points out that Naber et al was modified with Chary et al.
On page 25 of applicant’s remarks, applicant appears to argue that Chary last a pre-existing open continuous through-opening before resist application and does not disclose printing.
Examiner respectfully points out that Naber et discloses pre-existing open continuous through-opening before resist application. Chary et al discloses printing. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 26 of applicant’s remarks, applicant appears to argue that there is no teaching or suggestion in the cited art of a wafer has already has a continuous through-opening before the printed photoresist is applied, wherein the printed photoresist recesses the through-opening and is later removed with the metal located thereon.
Examiner respectfully points out that Naber et al discloses a wafer has already has a continuous through-opening before the printed photoresist is applied and Chary et al teaches wherein the printed photoresist recesses the through-opening and is later removed with the metal located thereon. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 27 of applicant’s remarks, applicant appears to argue adopting Naber’s open silicon via into Chary’s TWV process.
Examiner respectfully disagrees with applicant’s assertion that Chary et al is modified with Naber et al. Examiner respectfully points out that Naber et al is modified with Chary et al process.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lopatin et al (U.S. 2008/0121276) discloses selective electroless deposition for solar cells
Baker-O’Neal et al (2017/0309760) disclose surface preparation and uniform plating on through wafer vias and interconnects for photovoltaics..
Naber et al (U.S. 2015/0114462) disclose method of manufacturing a solar cell and solar cell this obtained.
Sharps (U.S. 2008/0185038) discloses inverted metamorphic solar cells with via for backside contacts.
Gee et al (U.S. 2005/0176164) disclose Back contact solar cells and methods of fabrication.
Moon et al (U.S. 2012/0288980) discloses method for manufacturing a back contact solar cell.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.E.B./ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
Prosecution Insights