DETAILED ACTION
Claims 1, 3-12, 14-17, and 19-23 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 3-12, 14-17, and 19-23 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Referring to claim 1 (and similarly claims 10 and 17), applicant recites “before executing program instructions of a program, selecting memory zones based on respective positions of the program instructions of the program”. The examiner cannot find original support for this limitation, including in paragraphs 46-48 and 74-76, as pointed out by applicant on page 10 of the response submitted on March 31, 2026. Instead, paragraph 47 states “During the execution of the program, each memory zone 154 can then be selected as a function of the memory address of the beginning of the executed instruction.”, which is contrary to that claimed. Applicant is claiming an active step that must be performed. The examiner cannot find any actual selecting occurring before program execution.
Referring to claim 4 (and similarly claim 15), the examiner has not found original support for selecting a memory zone before executing a program instruction in combination with storing being performing in parallel with execution. If the storing is occurring, then a memory zone must have been selected to store data in. Thus, claim 4 suggests that the selecting occurs before or at least in parallel with execution of the instruction.
All dependent claims are rejected due to their dependence on a claim lacking adequate written description.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, 9-12, 15-17, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over DeWitt, Jr. et al., U.S. Patent Application Publication No. 2003/0135719 A1, optionally in view of Ward et al. (EP 0238754), and in view of the examiner’s taking of Official Notice, and Van Praet et al., U.S. Patent No. 5,918,035.
Referring to claim 1, DeWitt has taught a method comprising:
selecting memory zones based on respective positions of program instructions of a program (see paragraphs [0102]-[0103] and [0109]. Basically, memory zones (in a register, or in a memory) are selected one after another as a series of instructions are processed (with each instruction position corresponding to a memory zone, e.g. a next instruction position corresponds to a next selected memory zone)),
Referring to the limitation that the selecting occurs before executing the program instructions of the program, this is not patentable for multiple reasons:
As is known, before fetching and executing a program, program instructions are stored in order in memory (e.g. FIG.1B, RAM 114). Thus, by storing the instructions in an order, corresponding memory zones are selected, i.e., the first zone is selected for the first instruction stored, the second zone is selected for the second instruction stored, and so on.
Alternatively, where the selecting is interpreted as storing a pointer/address of a zone, DeWitt has not taught that the selecting occurs before executing the program instructions of the program. However, Ward has taught a FIFO that writes to a current zone and then immediately increments so that it points to (i.e., selects) the next zone for the next write (see FIG.5, IWDP, and column 5, lines 46-50). This is common operation, where the current write results in selecting the zone for the next write. Official Notice is further taken that delaying instruction execution for a variety of reasons was well known in the art before applicant’s invention. Specifically, subsequent instructions may be delayed due to dependency (e.g. source operands not being yet produced by previous instructions), structural hazard, control hazard, etc., all well-known reasons for delay to ensure correct execution. This is largely based on the design of the program and the nature of the dependencies and flow thereof. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify DeWitt such that, for at least some of the instructions, execution is delayed such that selecting some zones occurs before executing the instructions.
Dewitt, alone or as modified, has further taught:
the program instructions each occupying one or more memory locations (see paragraphs [0040]-[0041] and note that instructions occupy one or more locations in instruction cache and/or RAM, from which the instructions are fetched), and
the memory zones comprising, for each memory location, a same number of bits (from paragraphs [0099], [0103], and FIG.6B, there is one bit in each zone for each instruction (and its location). This one bit stores the predicate value associated with that instruction).
DeWitt, alone or as modified, has not taught executing, more than once in a single run of the program, a plurality of instructions of the program instructions, each instruction of the plurality of instructions having a same respective program counter value each time the respective instruction is executed. However, Official Notice is taken that execution of a given instruction more than once, in a single run of a program, was well-known in the art before applicant’s invention. This can happen due to looping or calling the same function repeatedly, for instance. Basically, executing the same instruction more than once allows a program to re-use or repeat code that is needed multiple times (without inefficiently storing the code multiple times). Additionally, Van Praet has taught that each instruction is bound to a certain program counter value when the code is generated (see column 8, lines 22-62). This allows for simplified instruction addressing where each instruction can be individually and repeatedly accessed using a unique program counter value. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify DeWitt for executing, more than once in a single run of the program, a plurality of instructions of the program instructions, each instruction of the plurality of instructions having a same respective program counter value each time the respective instruction is executed.
DeWitt, as modified, has further taught, for each initial execution of each instruction of the plurality of instructions, storing a first value in a corresponding memory zone based on the respective program counter value for the respective instruction (as described above, memory zones are written one after another, in sequence, for a plurality of instructions (e.g. a loop)). Further, since processing any instruction requires first obtaining that instruction via its program counter value, the storing is ultimately based on the program counter); and
DeWitt, as modified, has not taught for each subsequent execution of each instruction of the plurality of instructions after the initial execution of the respective instruction, replacing a previously-stored first value in the corresponding memory zone with the first value.
It should be noted that DeWitt teaches an out-of-order processor (paragraph [0043]), which means instructions may not be processed/executed in the same order dictated by their program counters. However, Official Notice is taken that in-order processing was well-known in the art before applicant’s invention. In-order processing is understood to require a less-complex implementation compared to out-of-order execution. For instance, a re-order buffer isn’t needed and resources for scheduling and control are reduced since out-of-order tracking is not performed with in-order execution. While this is at the expense of potentially more idle/stall time, one of ordinary skill in the art that prefers simpler/cheaper hardware and reduced power consumption would be motivated to modify DeWitt to implement an in-order processor instead of an out-of-order processor. Alternatively, one may be motivated to modify DeWitt to include both out-of-order and in-order modes for increased flexibility, where systems with both modes were well-known in the art before applicant’s invention (where in-order mode could be used when lower power is desired. For instance, see Comparan et al., U.S. Patent Application Publication No. 2014/0281402 (abstract) as an example of support).
Secondly, given in-order execution (one instruction after another in program counter order), one of ordinary skill in the art would have recognized that a given instruction could cause the same memory zone to be selected during first and second executions of the given instruction during a single run of the program. This would happen when the number of instructions executed between the first and second executions of the given instruction is one less than the number of bits in the disposition storage. For instance, with a 128-bit disposition storage (paragraph [0103]), if the first instruction is executed twice and there are 127 instructions that execute between the multiple executions of the first instruction, the first instruction will write to the same memory zone of the disposition storage due to wrap-around. A program could be written with any number of instructions that may be executed in any sequence or any number of times such that, eventually, at least one of practically an infinite number of possible programs would select the same memory zone for multiple executions of the same instruction. In such a situation, every time the program counter equals X, the same memory zone would be written to. For instance, when there is a loop with 128 instructions where all instructions execute in order in each iteration, a 128-bit disposition storage would always write the same zone for the same instruction, each time it is executed. Changing size of a loop/function, i.e., the number of instructions therein, is not deemed a patentable distinction, particularly absent a demonstration of the criticality of the size of the loop/function. See MPEP 2144.04, including section (IV)(A).
Finally, paragraph [0104] of DeWitt states that when the disposition register is full, it is emptied and then it can be filled again starting with the least significant bit. As such, next instructions will cause writes of bits that replace what was there before.
As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify DeWitt to execute a program that causes repeated in-order execution of N-1 instructions (that use an N-bit disposition storage) between first and second executions of a given instruction, thereby causing the same memory zone to be written each time for the given instruction. For example, with a 128-bit register, if a loop has 128 instructions and they all execute in order for ten loop iterations, then during the initial iteration, the 128 instructions will fill the register, then during the 2nd iteration, the 128 instructions will write first values where the 128 instructions of the initial iteration wrote initial first values, thereby replacing those initial first values. This process will repeat with each instruction in the loop writing to the same memory zone in the register each time due to the number of instructions in the loop and in-order processing.
DeWitt, as modified, has further taught each program instruction bijectively associated with a respective memory zone, such that a total number of the program instructions equals a total number of the memory zones (based on the example above, each of the loop instructions is associated with one and only one memory zone that it will write to in each iteration. This will occur when a 128-instruction loop is writing to a 128-bit disposition register).
Referring to claim 4, DeWitt, as modified with or without Ward, has taught the method according to claim 1, but has not taught wherein, for each instruction of the plurality of instructions, the storing is performed in parallel with execution of the respective instruction (instead, FIG.6B and paragraph [0105] state that the storing 626 occurs after completion of execution 622). However, the timing of the write would be considered a routine expedient absent a demonstration by applicant of its criticality to the invention. Essentially, changing when the timing occurs amounts to a rearrangement of parts (processor functions in the computing realm). See MPEP 2144.04, including part (VI)(C). Changing when the storing occurs will not affect the operation or outcome of DeWitt. As explained throughout DeWitt, the predicate is known at the time of execution of the corresponding instruction because the predicate dictates whether the instruction will or will not execute. Thus, because it is known at the time of execution, one of ordinary skill in the art would have recognized that it could be stored at the time of execution, as opposed to waiting until after execution completes, thereby realizing earlier storage and earlier completion of the algorithm of FIG.6B, which could speed up overall operation. Additionally, doing something in parallel (storing and executing) versus doing something serially (storing after executing, as presently taught in FIG.6B) is a known improvement that improves speed and results in success. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify DeWitt such that, for each instruction of the plurality of instructions, the storing is performed in parallel with execution of the respective instruction.
Referring to claim 5, DeWitt, as modified with or without Ward, has taught the method according to claim 1, further comprising executing fourth and fifth instructions of the plurality of instructions simultaneously (see paragraph 41, 1st sentence), but has not taught performing the respective storings for the fourth and fifth instructions simultaneously. However, for reasons set forth in the rejection of claim 4, it is obvious for a storing to occur simultaneously with the execution of the corresponding instruction. Further, Official Notice is taken that resources with multiple ports to accommodate multiple writes in parallel were well-known in the art before applicant’s invention. This speeds up execution by avoiding serialization of writes. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify DeWitt for performing the respective storings for the fourth and fifth instructions simultaneously.
Referring to claim 6, DeWitt, as modified with or without Ward, has taught the method according to claim 1, further comprising, after the storings, verifying a presence or absence of the first value in each of the memory zones (this is the reason the trace is made. It may be analyzed to determine the execution flow as part of testing/debugging the machine. Also, see paragraph [0057], and note that a server may analyze the trace output).
Referring to claim 9, DeWitt, as modified with or without Ward, has taught the method according to claim 1, but has not taught wherein the memory zones are located in at least two distinct memory banks. However, implementing memory banks so as form an interleaved memory with higher throughput was well-known in the art before applicant’s invention (as an example, applicant is encouraged to review the “Interleaved memory” entry at Wikipedia.org, which is not cited at this time). This allows for contiguous reads/writes to occur to different banks so that each access doesn’t have to wait for the previous to finish. From paragraphs [0108]-[0111], the disposition indicators will be written to consecutive locations in memory, a technique that would naturally benefit from interleaved memory with memory banks. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify DeWitt such that the memory zones are located in at least two distinct memory banks.
Claim 10 is partially rejected for similar reasoning as claim 1. Furthermore, DeWitt has taught:
a data processing circuit configured to execute program instructions of a program (FIG.1B, at least execution unit 138, which would be included in any processor integrated circuit); and
a trace generation circuit coupled to the data processing circuit and configured to select memory zones in a trace memory (again, the trace memory may be the disposition trace register, zones of which are selected for writing. The circuit to do this selecting is a trace generation circuit).
Referring to claim 11, DeWitt, as modified with or without Ward, has taught the integrated circuit according to claim 10, further comprising the trace memory (again, the memory zones are in register 506, which is in processor (integrated circuit) 502).
Referring to claim 12, DeWitt, as modified with or without Ward, has taught the integrated circuit according to claim 11, wherein the integrated circuit is configured to: couple to an outside memory disposed outside the integrated circuit; and transmit contents of the memory zones to the outside memory (see FIG.1A and paragraphs [0018] and [0057]. Basically, the trace output could be sent to a server for analysis. The server would inherently include memory to receive the trace output. Thus, the integrated circuit in the client is coupled to an outside memory in a server).
Claims 15-16 are rejected for similar reasoning as claims 4-5, respectively.
Referring to claim 17, DeWitt has taught a system (e.g. FIG.1A, client 105) comprising:
an integrated circuit comprising memory zones (see FIG.5B and note that a processor (integrated circuit, includes a multiple-bit register, each bit being a memory zone (e.g. it could include 128 bits per paragraph [0103]), wherein the integrated circuit is configured to:
select the memory zones based on respective positions of program instructions of a program (see paragraphs [0102]-[0103]. Basically, memory zones (in a register, or in a memory) are selected one after another as a series of instructions are processed (with each instruction position corresponding to a memory zone, e.g. a next instruction position corresponds to a next selected memory zone)).
Referring to the limitation that the selecting occurs before executing the program instructions of the program, this is not patentable for multiple reasons:
As is known, before fetching and executing a program, program instructions are stored in order in memory (e.g. FIG.1B, RAM 114). Thus, by storing the instructions in an order, corresponding memory zones are selected, i.e., the first zone is selected for the first instruction stored, the second zone is selected for the second instruction stored, and so on.
Alternatively, where the selecting is interpreted as storing a pointer/address of a zone, DeWitt has not taught that the selecting occurs before executing the program instructions of the program. However, Ward has taught a FIFO that writes to a current zone and then immediately increments so that it points to (i.e., selects) the next zone for the next write (see FIG.5, IWDP, and column 5, lines 46-50). This is common operation, where the current write results in selecting the zone for the next write. Official Notice is further taken that delaying instruction execution for a variety of reasons was well known in the art before applicant’s invention. Specifically, subsequent instructions may be delayed due to dependency (e.g. source operands not being yet produced by previous instructions), structural hazard, control hazard, etc., all well-known reasons for delay to ensure correct execution. This is largely based on the design of the program and the nature of the dependencies and flow therein. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify DeWitt such that, for at least some of the instructions, execution is delayed such that selecting some zones occurs before executing the instructions.
DeWitt, alone or as modified, has further taught:
the program instructions each occupying one or more memory locations (see paragraphs [0040]-[0041] and note that instructions occupy one or more locations in instruction cache and/or RAM, from which the instructions are fetched), wherein the memory zones comprise, for each memory location, a same number of bits (from paragraphs [0099], [0103], and FIG.6B, there is one bit in each zone for each instruction. This one bit stores the predicate value associated with that instruction);
DeWitt, alone or as modified, has further taught the integrated circuit is configured to:
execute the program instructions (the processor 502/120 executes instructions in at least execution unit 130 (FIG.1B)); and
transmit contents of the memory zones to an outside memory coupled to the integrated circuit (see paragraphs [0056]-[0057], [0077]-[0078], and also [0104]. Basically, one way or another, the trace data will end up in an outside memory. That is, when the register fills up, to prevent overflow, the data in the memory zones will be transmitted to an outside memory. Further, ultimately, the trace data ends up written to a file so that it can be analyzed. Files are stored in outside memory such as somewhere in outside memory 110 (FIG.1B)); and
the outside memory (again, see FIG.1B, 110), configured to:
receive the contents of the memory zones; and write the contents of the memory zones in the outside memory (see the reasoning above. The outside memory stores the trace data to avoid overflow of internal memory and to generate a collective file for trace analysis).
DeWitt has not taught executing, more than once in a single run of the program, a plurality of instructions of the program instructions, each instruction of the plurality of instructions having a same respective program counter value each time the respective instruction is executed. However, Official Notice is taken that execution of a given instruction more than once, in a single run of a program, was well-known in the art before applicant’s invention. This can happen due to looping or calling the same function repeatedly, for instance. Basically, executing the same instruction more than once allows a program to re-use or repeat code that is needed multiple times (without inefficiently storing the code multiple times). Additionally, Van Praet has taught that each instruction is bound to a certain program counter value when the code is generated (see column 8, lines 22-62). This allows for simplified instruction addressing where each instruction can be individually and repeatedly accessed using a unique program counter value. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify DeWitt for executing, more than once in a single run of the program, a plurality of instructions of the program instructions, each instruction of the plurality of instructions having a same respective program counter value each time the respective instruction is executed.
DeWitt, as modified, has further taught, for each initial execution of each instruction of the plurality of instructions, storing a first value in a corresponding memory zone based on the respective program counter value for the respective instruction (as described above, memory zones are written one after another, in sequence, for a plurality of instructions (e.g. a loop)). Further, since processing any instruction requires first obtaining that instruction via its program counter value, the storing is ultimately based on the program counter); and
DeWitt, as modified, has not taught for each subsequent execution of each instruction of the plurality of instructions after the initial execution of the respective instruction, replace a previously-stored first value in the corresponding memory zone with the first value.
It should be noted that DeWitt teaches an out-of-order processor (paragraph [0043]), which means instructions may not be processed/executed in the same order dictated by their program counters. However, Official Notice is taken that in-order processing was well-known in the art before applicant’s invention. In-order processing is understood to require a less-complex implementation compared to out-of-order execution. For instance, a re-order buffer isn’t needed and resources for scheduling and control are reduced since out-of-order tracking is not performed with in-order execution. While this is at the expense of potentially more idle/stall time, one of ordinary skill in the art that prefers simpler/cheaper hardware and reduced power consumption would be motivated to modify DeWitt to implement an in-order processor instead of an out-of-order processor. Alternatively, one may be motivated to modify DeWitt to include both out-of-order and in-order modes for increased flexibility, where systems with both modes were well-known in the art before applicant’s invention (where in-order mode could be used when lower power is desired. For instance, see Comparan et al., U.S. Patent Application Publication No. 2014/0281402 (abstract) as an example of support).
Secondly, given in-order execution (one instruction after another in program counter order), one of ordinary skill in the art would have recognized that a given instruction could cause the same memory zone to be selected during first and second executions of the given instruction during a single run of the program. This would happen when the number of instructions executed between the first and second executions of the given instruction is one less than the number of bits in the disposition storage. For instance, with a 128-bit disposition storage (paragraph [0103]), if the first instruction is executed twice and there are 127 instructions that execute between the multiple executions of the first instruction, the first instruction will write to the same memory zone of the disposition storage due to wrap-around. A program could be written with any number of instructions that may be executed in any sequence or any number of times such that, eventually, at least one of practically an infinite number of possible programs would select the same memory zone for multiple executions of the same instruction. In such a situation, every time the program counter equals X, the same memory zone would be written to. For instance, when there is a loop with 128 instructions where all instructions execute in order in each iteration, a 128-bit disposition storage would always write the same zone for the same instruction, each time it is executed. Changing size of a loop/function, i.e., the number of instructions therein, is not deemed a patentable distinction, particularly absent a demonstration of the criticality of the size of the loop/function. See MPEP 2144.04, including section (IV)(A).
Finally, paragraph [0104] of DeWitt states that when the disposition register is full, it is emptied and then it can be filled again starting with the least significant bit. As such, next instructions will cause writes of bits that replace what was there before.
As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify DeWitt to execute a program that causes repeated in-order execution of N-1 instructions (that use an N-bit disposition storage) between first and second executions of a given instruction, thereby causing the same memory zone to be written each time for the given instruction. For example, with a 128-bit register, if a loop has 128 instructions and they all execute in order for ten loop iterations, then during the initial iteration, the 128 instructions will fill the register, then during the 2nd iteration, the 128 instructions will write first values where the 128 instructions of the initial iteration wrote initial first values, thereby replacing those initial first values. This process will repeat with each instruction in the loop writing to the same memory zone in the register each time due to the number of instructions in the loop and in-order processing.
DeWitt, as modified, has further taught each program instruction bijectively associated with a respective memory zone, such that a total number of the program instructions equals a total number of the memory zones (based on the example above, each of the loop instructions is associated with one and only one memory zone that it will write to in each iteration. This will occur when a 128-instruction loop is writing to a 128-bit disposition register).
Referring to claim 21, DeWitt, as modified with or without Ward, has taught the system according to claim 17, wherein the number of bits is one (again, from paragraphs [0099], [0103], and FIG.6B, there is one bit in each zone for each instruction. This one bit stores the predicate value associated with that instruction).
Claims 22-23 are rejected for similar reasoning as claim 21.
Claims 14 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over DeWitt optionally in view of Ward, and in view of the examiner’s taking of Official Notice, Van Praet, and Emma et al., U.S. Patent Application Publication No. 2008/0010555 A1.
Referring to claim 14, DeWitt, as modified, has taught the integrated circuit according to claim 10, but has not taught wherein each of the memory zones comprises a first bit and a second bit. Instead DeWitt only teaches a 1-bit predicate value indicating completion (or lack thereof) of an instruction. However, Emma has taught that in addition to tracing a similar completion bit 250 (paragraph [0082]) in an entry (memory zone) of a trace buffer (FIG.3), other information comprising a plurality of bits may be recorded (see the fields in FIG.3 and paragraphs [0046]-[0060]). The examiner asserts that any amount of information may be collected to try to provide more information to user for testing/debugging. As a result, to make the user more aware of other conditions in the system for each instruction, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify DeWitt to store, along with the trace disposition bit, at least one other bit that indicates the information of Emma. The combination then further teaches that the trace generation circuit is configured to, for each instruction of the plurality of instructions: store one as the first value in a location of the first bit based on the respective instruction having a predicate set to a true value (see DeWitt, FIG.6B, where the relevant predicate bit is stored in the first bit (disposition indicator). From paragraph [0013]), a true predicate has a value of ‘1’)); (note that struck-through language is alternative in nature and not required by the claim).
Claim 19 is rejected for similar reasoning as claim 14.
Referring to claim 20, DeWitt, as modified with or without Ward, has taught the system according to claim 17, wherein the system is configured to verify a presence of the first value in the content of each of the memory zones, and detect an absence of the first value in one of the memory zones (this is the reason the trace is made. It may be analyzed to determine the execution flow as part of testing/debugging the machine. Also, from paragraph [0057], this verification may be done by the client device itself. Note that any presence detection necessarily includes an absence detection, e.g. if something is detected as not present, it is detected as absent).
Allowable Subject Matter
Claims 3 and 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art of record, alone or in combination, has not taught, together with all other claimed features, the final detecting and storing steps.
Regarding claim 7, the prior art of record, alone or in combination, has not taught, together with all other claimed features, the writing of claim 7. Instead DeWitt, writes only to the next bit in sequence for each instruction (paragraph [0103]). This is different than writing a word for each instruction, where the word includes data from a zone outside of the at least one of the memory zones. To illustrate, in applicant’s FIG.5, if a first store involves writing a value X to the rightmost field in word 540, a second store writing a value Y to field 550 will also at least rewrite X to the rightmost field, i.e., the second store will write YX to the rightmost two fields in word 540 along with any other values already previously written in word 540. In DeWitt, no rewrite occurs.
Response to Arguments
On page 10 of applicant’s response, applicant argues that DeWitt has not taught the selecting before the execution of instructions.
The examiner asserts that based on one interpretation of selecting, DeWitt has taught the claim as amended. Based on another interpretation of selecting, the examiner agrees that DeWitt has not taught the claim as amended; however, the added feature is deemed an obvious modification. Both rejections have been set forth above.
On page 11 of applicant’s response, applicant argues that the prior art does not teach the bijective association before execution.
The bijective association is not claimed to occur before execution. And, for reasons set forth above, it is obvious for the prior art to include the bijective association.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
Prosecution Insights