DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 21, 22, 23, and 25 through 40 rejected
Present action: claims 21, 22, 23, and 25 through 40 rejected
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 23, 27, 30 through 40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 23 recites “the substrate comprises a dielectric layer comprising a first aperture through which the die pad of the semiconductor die is exposed from the dielectric layer, and a second aperture through which the first end of at least one of the plurality of vertical vias is exposed from the dielectric layer” in lines 2 through 5. However, when the die and components are mounted (see claim 21) the die pad and vias are not exposed.
Claim 27 recites “each of the plurality of vertical vias is exposed from the molding material at the top component side and the bottom component side” in lines 1 through 3. However, claim 21 recites that the component is mounted to the substrate in lines 7 and 8. Mounting the component to the substrate would cover the bottom side of the first component so that the bottom side is not exposed.
Claim 30 recites that the first component has “the second end surface of each of the plurality of parallel vias exposed from the bottom component side of the encapsulating material” in lines 13 and 14. However, the claim also states that the first component is mounted to the signal distribution structure in line 3. Mounting the component to the signal distribution structure would cover the bottom side of the first component so that the bottom side is not exposed.
Claim 34 recites “the SDS comprises a dielectric layer comprising a first aperture through which the die pad of the semiconductor die is exposed from the dielectric layer, and a second aperture through which the first end surface of at least one of the plurality of parallel vias is exposed from the dielectric layer” in lines 2 through 5. However, when the die and components are mounted (see claim 30) the die pad and vias are not exposed.
Claim 36 recites “wherein the first pattern end is exposed from the molding material at the bottom component side” in lines 12 and 13. However, the claim also states that the first component is mounted to the substrate structure in lines 7 and 8. Mounting the component to the substrate would cover the bottom side of the first component so that the bottom side is not exposed.
Claim 40 recites “the second pattern end exposed from the molding material at the bottom component side” in lines 2 and 3. Mounting the component to the substrate would cover the bottom side of the first component so that the bottom side is not exposed.
For the purpose of the examination and in order for all elements of the claim to be given meaning, “exposed” will be understood to mean “not covered by”, as in “not covered by the dielectric layer” or “not covered by the encapsulating layer”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21, 22, 23, 25, 26, 27, 28, and 29 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Liu (US 2017/0033062)
Regarding claim 21.
Liu teaches:
an electronic device (fig 3f:192; [para 0059]) comprising:
a substrate (fig 3f:216(0052]) having a first side, a second side, and lateral sides extending between the first side and the second side;
a first component (fig 3f,3i:170; [para 0042]) comprising: a top component side, a bottom component side, and outermost lateral component sides extending between the top component side and the bottom component side, wherein the bottom component side is mounted to the first side of the substrate (fig 3f:216; [para 0026]) (see annotated figure 3f);
at least one row of a plurality of vertical vias (fig 3f:174; [para 0044]) extending between the top component side and the bottom component side, each of the plurality of vertical vias comprising a top via side, a bottom via side, and a lateral via side extending between the top via side and the bottom via side (see annotated figure 3f);
and a molding material (fig 3f:172; [para 0042]) of a first composition laterally surrounding and contacting each of the plurality of vertical vias (fig 3f:174; [para 0044]), wherein each of the outermost lateral component sides comprises only the molding material (fig 3i,3f:172; [para 0042]), and wherein a single continuous layer of the molding material (fig 3f:172; [para 0042]) of the first composition extends from the lateral via side of the plurality of vias to (fig 3f,3i:174; [para 0044]) at least three of the outermost lateral component sides of the first component (fig 3i; [para 0056]);
a semiconductor die (fig 3f:124; [para 0045]) having a top die side, a bottom die side, and lateral die sides extending between the top die side and the bottom die side, the bottom die side coupled to the first side of the substrate (fig 3f:216; [para 0026]) (see annotated figure);
and a molded package body (fig 3f:190; [para 0046]) comprising a first package body side, a second package body side, and lateral package body sides extending between the first package body side and the second package body side (fig 3f,3i190; [para 0046]), the molded package body comprising a molding compound ([para 0046])covering at least a portion of the first side of the substrate (fig 3f:216; [para 0026]), and laterally surrounding the entire semiconductor die (fig 3i:124; [para 0057]) and the entire first component (see annotated figure 3i:170; [para 0052]), wherein the lateral package body sides are coplanar with the lateral sides of the substrate (fig 3i), and wherein the molded package body directly contacts each of the outermost lateral component sides (fig 3i).
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Regarding claim 22,
Liu teaches the electronic device of claim 21, wherein,
Liu teaches:
the substrate (fig 3f:216; [para 00216]) comprises a conductive layer (fig 2h:212a; [para 0049]) that electrically connects a die pad (fig 3f:132; [para 0034]) of the semiconductor die (fig 3f:124; [para 0034]) to a first end of at least one of the plurality of vertical vias (fig 3f:174; [para 0074]).
Regarding claim 23, Liu teaches the electronic device of claim 22.
Liu teaches:
the substrate (fig 3f:216; [para 0052]) comprises a dielectric layer (fig 3f:210; [para 0051]) comprising a first aperture (see annotated figure) through which the die pad (fig 3f:132; [para 0034]) of the semiconductor die (fig 3f:124; [para 0034]) is exposed from the dielectric layer (fig 3f:210; [para 0047]), and a second aperture through which the first end of at least one of the plurality of vertical vias (fig 3f:174; [para 0044]) is exposed from the dielectric layer (fig 3f:210; [para 0047]);
and the conductive layer (fig 3f:212a; [para 0049]) extends into the first and second apertures (annotated figure).
Regarding claim 25,
Liu teaches the electronic device of claim 21.
Liu teaches:
a top side of the molding compound (fig 3f:190; [para 0046]) is coplanar with the top component side (annotated figure).
Regarding claim 26,
Liu teaches the electronic device of claim 21
Liu teaches:
the molding compound (fig 3f:190; [para 0046]) covers the top die side (annotated 3f).
Regarding claim 27,
Liu teaches the electronic device of claim 21
Liu teaches:
each of the plurality of vertical vias (fig 3f:174; [para 0044]) is exposed from the molding material (fig 3f:190; [para 0052]) at the top component side and the bottom component side (see annotated figure).
Regarding claim 28,
Liu teaches the electronic device of claim 21
Liu teaches:
each of the plurality of vertical vias (fig 3f:174; [para 0044]) is one of a plurality of parallel straight-line traces of a component conductive layer.
Regarding claim 29,
Liu teaches the electronic device of claim 21
Liu teaches:
a die pad on the bottom die side, wherein the die pad (fig 3f:132; [para 0034]) on the bottom die side is attached to the substrate (fig 3f:216; [para 0052]).
Claim(s) 30, 31, 32, 33, 34, and 35 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Liu (US 2017/0033062)
Regarding claim 30
Liu teaches:
an electronic device (fig 3f,3i:192; [para 0047]) comprising: a signal distribution structure (SDS) (fig 3f:212a; [para 0048]);
a first component (fig 3f:170; [para 0042]) mounted to the SDS (fig 3f:212a; [para 0048]), the first component (fig 3f:170; [para 0042]) comprising: a plurality of parallel vias (fig 3f:174; [para 0043]), each of the plurality of parallel vias (fig 3f:174; [para 0044]) having a first end surface, a second end surface, and a lateral side surface (see annotated figure);
an encapsulating material (fig 3f:172; [para 0043]) of a first composition contacting the lateral side surface of each of the plurality of parallel vias (fig 3f:174; [para 0044]), the encapsulating material (fig 3f:172; [para 0043]) having a top component side, a bottom component side, and outermost lateral components sides extending between the top and bottom component sides (annotated figure), each of the outermost lateral component sides comprising only the encapsulating material (fig 3f,3i:172; [para 0043]), the first end surface of each of the plurality of parallel vias (fig 3f:174; [para 0044]) exposed from the top component side of the encapsulating material (fig 3f:172; [para 0043]), and the second end surface of each of the plurality of parallel vias (fig 3f:174; [para 0044]) exposed from the bottom component side of the encapsulating material (fig 3f:172; [para 0043]) (see annotated figure), and wherein a single continuous layer of the encapsulating material (fig 3f,3i:172; [para 0043]) of the first composition extends from the lateral side surface of the plurality of parallel vias (fig 3f,3i:172; [para 0043]) to at least three of the outermost lateral component sides of the first component (fig 3f,3i:170; [para 0056]); a semiconductor die (fig 3f:124; [para 0036]) coupled to the SDS (fig 3f:212a; [para 0049]);
and a molded package body comprising a first package body side, a second package body side, and a lateral package body side extending between the first package body side and the second package body side (see annotated figure), the molded package body comprising a molding compound (fig 3f:190; [para 0046])laterally covering the semiconductor die (fig 3f:124; [para 0053]) and directly contacting each of the outermost lateral components sides (fig 3i), wherein: the molding compound (fig 3f:190; [para 0053]) is coplanar with the top component side, the lateral package body side forms a first lateral side of the electronic device (fig 3i:192), a first lateral die side of the semiconductor die (fig 3f:124; [para 0053]) and the first lateral side of the electronic device (fig 3f:192; [para 0053]) are oriented in a first direction, and the encapsulating material (fig 3i:172; [para 0042]) of the first component (fig 3i:170; [para 0042]) is directly laterally between the first lateral die side of the semiconductor die (fig 3i:124; [para 0036]) and at least a portion of the molded package body that forms the first lateral side of the electronic device (fig 3i:192).
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Regarding claim 31,
Liu teaches the electronic device of claim 30.
Liu teaches:
the molding compound (fig 3f:190; [para 0046]) of the molded package body laterally surrounds the entire semiconductor die (fig 3f,3i:124; [para 0046]).
Regarding claim 32,
Liu teaches the electronic device of claim 32.
Liu teaches:
the molding compound (fig 3f:190; [para 0046]) covers the top die side (fig 3f).
Regarding claim 33,
Liu teaches the electronic device of claim 30
Liu teaches:
the SDS (fig 3f:212a; [para 0048]) comprises an SDS conductive path that electrically connects a die pad (fig 3f:132; [para 0048]) of the semiconductor die (fig 3f:124; [para 0047]) to the first end surface of at least one of the plurality of parallel vias (fig 3f:174; [para 0047]).
Regarding claim 34,
Liu teaches the electronic device of claim 33
Liu teaches:
the SDS (fig 3f:212a; [para 0048]) comprises a dielectric layer (fig 3f:210; [para 0048]) comprising a first aperture through which the die pad (fig 3f:132; [para 0048]) of the semiconductor die (fig 3f:124; [para 0045]) is exposed from the dielectric layer (fig 3f:210; [para 0048]), and a second aperture through which the first end surface of at least one of the plurality of parallel vias (fig 3f:174; [para 0048]) is exposed from the dielectric layer (fig 3f:210; [para 0048]);
and the SDS conductive path (fig 3f:212a; [para 0049]) extends into the first and second apertures.
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Regarding claim 35,
Liu teaches the electronic device of claim 30.
Liu teaches:
the plurality of parallel vias (fig 3f:174; [para 0044]) comprise at least three parallel vias arranged in a row (fig 3i).
Claim(s) 36, 37, 38, and 39 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Liu (US 2017/0033062)
Regarding claim 36.
Liu teaches:
an electronic device (fig 3f:192; [para 0053]) comprising: a substrate (fig 3f:216; [para 0052]) having a first side, a second side, and a lateral side extending between the first side and the second side;
a first component (fig 3f:170; [para 0044]) comprising: a top component side, a bottom component side, and outermost lateral component sides extending between the top component side and the bottom component side, wherein the bottom component side is mounted to the first side of the substrate (fig 3f:216; [para 0052]);
a conductive pattern (fig 3f:174; [para 0044]) comprising a first pattern end;
and a molding material (fig 3f:172; [para 0043]) of a first composition at least partially laterally surrounding and contacting the conductive pattern (fig 3f:174; [para 0044]), wherein the first pattern end is exposed from the molding material (fig 3f:172; [para 0043]) at the bottom component side, and-wherein each of the outermost lateral component sides comprises only the molding material (fig 3i:172; [para 0043]), and wherein a single continuous layer of the molding material (fig 3i:172; [para 0072]) of the first composition extends from the conductive pattern (fig 3i:174; [para 0044]) to at least three of the outermost lateral component sides of the first component (fig 3i:170; [para 0062]);
a semiconductor die (fig 3f:124; [para 0045]) having a top die side, a bottom die side, and lateral die sides extending between the top die side and the bottom die side, the bottom die side coupled to the first side of the substrate (fig 3f:216; [para 0052]);
and a molding compound (fig 3f:190; [para 0046]) comprising a first molding compound side, a second molding compound side, and a lateral molding compound side extending between the first molding compound side and the second molding compound side, the molding compound (fig 3f:190; [para 0046]) covering at least a portion of the first side of the substrate (fig 3f,3i:216), and laterally surrounding the entire semiconductor die (fig 3i:124; [para 0046]) and the entire first component (fig see annotated figure 3i:170; [para 0046]), wherein: the first molding compound side is coplanar with the top component side, the lateral molding compound side is coplanar with the lateral side of the substrate (fig 3f,3i:216; [para 0052]);
and the molding compound (fig 3i:190; [para 0046]) directly contacts each of the outermost lateral component sides (fig 3i:170; [para 0052]).
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Regarding claim 37,
Liu teaches the electronic device of claim 36
Liu teaches:
the conductive pattern (fig 3f,174; [para 0044]) comprises at least one trace.
Regarding claim 38,
Liu teaches the electronic device of claim 36.
Liu teaches:
the conductive pattern (fig 3f:174; [para 0044]) comprises a second pattern end, the second pattern end exposed from the molding material (fig 3f:172; [para 0043]) at the top component side (annotated figure 3f).
Regarding claim 39,
Liu teaches the electronic device of claim 38
Liu teaches:
the conductive pattern (fig 3f:174; [para 0044]) is one of a resistive component pattern (copper paste inherently has a resistance), a capacitive component pattern, a bimetallic connection component pattern, a shield component pattern, an inductive component pattern, a coaxial connection component pattern, and an insulated coaxial connection component pattern.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2017/0033062) as applied to claim 36 and further in view of Han (US 9853003)
Regarding claim 40.
Liu teaches the elements of the claim 36 above.
Liu does not teach an inductive conductive pattern
Han teaches:
the conductive pattern (fig 11a:112a-i[column 10 lines 55-65]) comprises a second pattern end, the second pattern end exposed from the molding material (fig 11a:111b[column 10 lines 60-65]) at the bottom component side, and wherein the conductive pattern is an inductive component pattern (column 11 line 14).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an inductor conductive pattern in order to control the power supplied to the die (column 1 lines 40-45)
Response to Arguments
Applicant's arguments filed 5/8/2026 have been fully considered but they are not persuasive.
The applicant argues that the term “exposed” does not result in an ambiguity because the term is applied to being pad in regards to not being covered by the surrounding dielectric.
However, the term “exposed” can also be given the broadest interpretation of being exposed to the surrounding environment, in which case an ambiguity results because the structure requires that the surface be covered and exposed.
The applicant argues that Liu (US 2017/0033062) does not anticipate the claimed invention because figure 3j does not show all the lateral surfaces of the first component are surrounded and in contact with the molded package body.
The applicant will note that the examiner specifically referred to figures 3f and 3i (see above) which clearly and graphically teaches that the first component is embedded in and completely surrounded by the molded package body, the applicant will note the annotated figure (above) which shows in detail all lateral side surfaces are in contact with the molded package body.
The applicant will note that any portion of the prior art may be relied upon, MPEP 2125.I. The drawings must be evaluated for what they reasonably disclose and suggest to one of ordinary skill in the art. In re Aslanian, 590 F.2d 911, 200 USPQ 500 (CCPA 1979). Further, the structure shown in figure 3I was not unintended or inadvertent arrangement, but rather a specifically fabricated and carefully assembled arrangement of parts.
The prior art may be relied upon where an intermediate product anticipates the claimed invention. MPEP 2112.II. SmithKline Beecham Corp. v. Apotex Corp., 403 F.3d 1331, 1343-44, 74 USPQ2d 1398, 1406-07 (Fed. Cir. 2005)
Further, the applicant will note “When a claim covers several structures or compositions, either generically or as alternatives, the claim is deemed anticipated if any of the structures or compositions within the scope of the claim is known in the prior art.” Brown v. 3M, 265 F.3d 1349, 1351, 60 USPQ2d 1375, 1376, MPEP 2131.
The applicant has provided no evidence or reasoning as to why the structure illustrated in figures 3f and 3I and relied upon in the rejection (see above) does not disclose each and every element of the claimed invention. The subsequent processing of the structure illustrated in figure 3i does not eliminate the teaching of figures 3i.
The applicant argues that the prior art does not teach the first component is directly laterally between the first lateral die side of the semiconductor die and at least a portion of the molded package body. The applicant argues that the examiner relied upon an arbitrary line that extended towards the side rather than “directly laterally”.
The applicant will note that by definition laterally means towards the side, the annotated figure shows a line that extends towards the side, and the examiner applied a broad and reasonable interpretation. MPEP 211.01. An applicant is entitled to be their own lexicographer and may rebut the presumption that claim terms are to be given their ordinary and customary meaning, but this requires clearly setting forth a definition of the term that is different from its ordinary and customary meaning(s) in the specification at the relevant time. See In re Paulsen, 30 F.3d 1475, 1480, 31 USPQ2d 1671, 1674 (Fed. Cir. 1994). MPEP 211.IV.A. The applicant did not clearly redefine the term “laterally” so an alternative definition was not applied.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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