Prosecution Insights
Last updated: October 02, 2026

Examiner: GOODWIN, DAVID J

Tech Center 4100 • Art Units: 2817 2818 4100

This examiner grants 67% of resolved cases

Analysis

David J Goodwin is an examiner in Tech Center 4100 and Art Unit 2817. He has managed 820 resolved cases, maintaining an allowance rate of 67.3 percent. The data includes an interview lift of 16.4 percent, representing the increase in allowance probability associated with examiner interviews. This 16.4 percent lift is a notable gain when compared to the 67.3 percent baseline allowance rate. Practitioners should consider scheduling interviews to clarify technical points and potentially improve the likelihood of a grant.

The median days to allowance for the 820 resolved cases is 1178. This figure establishes the expected timeframe for reaching a successful conclusion in Art Unit 2817. The 67.3 percent allowance rate suggests a moderate level of success for applicants seeking patent protection. Practitioners can use the 1178 days to allowance to plan their prosecution budgets and manage client expectations. The 16.4 percent interview lift indicates that direct engagement remains a productive tactic in Tech Center 4100.

In Art Unit 2817, the resolved cases provide a stable statistical foundation for these observations. The 1178 days to allowance is the median duration for successful outcomes. Understanding the relationship between the allowance rate and the interview lift helps in developing a realistic strategy. These figures offer a data-grounded view of the examination process. Practitioners can rely on these numbers to guide their interactions with the examiner and optimize their prosecution approach.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

67.4%
Allow Rate
+7.4% vs TC avg
892
Total Applications
+16.5%
Interview Lift
1178
Avg Prosecution Days
Based on 821 resolved cases, 2023–2026

Rejection Statute Breakdown

0.1%
§101 Eligibility
17.8%
§102 Novelty
60.4%
§103 Obviousness
18.6%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
17761516 DISPLAY DEVICE USING MICRO LED, AND MANUFACTURING METHOD THEREFOR Final Rejection LG ELECTRONICS INC.
18674004 SEMICONDUCTOR PACKAGE HAVING DIELECTRIC LAYER WITH STEP DIFFERENCE Non-Final OA SAMSUNG ELECTRONICS CO., LTD.
18596240 THREE-DIMENSIONAL SEMICONDUCTOR PACKAGE Non-Final OA SAMSUNG ELECTRONICS CO.,LTD.
18442274 GATE STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME Final Rejection Samsung Electronics Co., Ltd.
18402021 SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME Final Rejection SAMSUNG ELECTRONICS CO., LTD.
18086086 SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME Final Rejection SAMSUNG ELECTRONICS CO., LTD.
17659135 SEMICONDUCTOR DEVICE Final Rejection SAMSUNG ELECTRONICS CO., LTD.
17932182 Structure and Method of Fabrication for High Performance Integrated Passive Device Non-Final OA Apple Inc.
18565028 DISPLAY PANEL AND MANUFACTURING METHOD THEREOF Final Rejection BOE Technology Group Co., Ltd.
18745789 DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME Non-Final OA Samsung Display Co., Ltd.
18825338 LIGHT EMITTING DISPLAY DEVICE Non-Final OA LG DISPLAY CO., LTD.
18415383 Light Emitting Element Display Device Final Rejection LG Display Co., Ltd.
17886894 Electroluminescent Display Device Final Rejection LG Display Co., Ltd.
17749806 Display Device Non-Final OA LG Display Co., Ltd.
18051543 ELECTRONIC DEVICE Final Rejection InnoLux Corporation
17686943 ENCAPSULATION ARRANGEMENTS IN LIGHT-EMITTING DIODE PACKAGES Final Rejection CreeLED, Inc.
17728147 PACKAGING ARCHITECTURE FOR WAFER-SCALE KNOWN-GOOD-DIE TO KNOWN-GOOD-DIE HYBRID BONDING Non-Final OA Intel Corporation
18519172 METHOD OF FORMING AN ORGANIC POLYMER COMPRISING POLYIMIDE Final Rejection ASM IP Holding B.V.
18057135 SCRIBE LANE REINFORCEMENT Non-Final OA ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
18564966 SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE Non-Final OA SONY SEMICONDUCTOR SOLUTIONS CORPORATION
17983863 DIAGONAL WIRING LEVEL WITH SKIP-LEVEL VIA CONNECTIONS Final Rejection International Business Machines Corporation
17941987 SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME Non-Final OA Kioxia Corporation
17975071 CONDUCTIVE PERFORATED PLATE FOR ELECTRICAL TEST Final Rejection TEXAS INSTRUMENTS INCORPORATED
18403007 METHODS FOR MECHANICAL SELF-ALIGNMENT AND SLIP-RESISTANCE IN BONDING SEMICONDUCTOR SUBSTRATES, AND SEMICONDUCTOR DEVICES COMPRISING MECHANICAL SELF-ALIGNMENT STRUCTURES Non-Final OA Micron Technology, Inc.
18238848 HIGH VOLTAGE DEVICE AND METHOD Final Rejection Micron Technology, Inc.
17943104 TIGHTLY-COUPLED RANDOM ACCESS MEMORY INTERFACE SHIM DIE Final Rejection Micron Technology, Inc.
17884775 FORMATION OF MEMORY DIE AND LOGIC DIE WITH WAFER-ON-WAFER BOND Non-Final OA Micron Technology, Inc.
18344857 METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE Final Rejection Taiwan Semiconductor Manufacturing Company, Ltd.
17729893 Metal Contact Isolation and Methods of Forming the Same Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
17105341 SEMICONDUCTOR DEVICE STRUCTURE, STACKED SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE STRUCTURE Final Rejection Taiwan Semiconductor Manufacturing Company, Ltd.

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