DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 10/30/25, responding to the Office action mailed on 8/5/25, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1 and 4-17 are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 8, 10-12, 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (US 20160056113 A1) in view of Farooq et al. (US 20110193197 A1).
Re Claim 1 Ko teaches a method for manufacturing a wafer having crack- stopping through-silicon-vias (FIG. 4), comprising:
providing a first wafer body (100) [0093] and a second wafer body (200) [0099] that are stacked together, the first wafer body (100) having a first scribe lane (SR1) [0098] for die cutting, the second wafer body (200) having a second scribe lane (SR2) [0099] for die cutting (FIG. 4);
forming a plurality of first crack-stopping through-silicon-vias (TSVs) (TSV1 and CS1) [0093] on a side of the first scribe lane (SR1, claim language does not require TSV to be in scribe lane region) of the first wafer body (100),
forming a plurality of second crack-stopping TSVs (TSV2) on a side of the second scribe lane (SR2, claim language does not require TSV to be in scribe lane region) of the second wafer body (200), wherein each of the plurality of second crack-stopping TSVs (TSV2) is aligned to one of the plurality of first crack-stopping TSVs (TSV1 and CS1) and exposes a surface of the one of the plurality of first crack-stopping TSVs (TVS1 and TSV2 are both connected to 310, and part of the top surface of TSV1 is exposed, FIG. 4); and
wherein the plurality of first crack-stopping TSVs (TSV1 and CS1) and the plurality of second crack-stopping TSVs (TSV2) constitute plurality of crack-stopping TSVs (FIG. 4).
Ko does not teach the plurality of first crack-stopping TSVs exposing an interfacial surface of the second wafer body;
filling each of the plurality of first crack-stopping TSVs with a protective material; and
filling each of the plurality of second crack-stopping TSVs with the protective material.
Farooq teaches the plurality of first crack-stopping TSVs (392/394) exposing an interfacial surface of the second wafer body (100) [0033];
filling each of the plurality of crack stopping TSVs with a protective material (362/364, [0036], FIG. 5). Farooq does explicitly teach two separate plurality sets of TSVs, but the process can be repeated for a 2nd wafer.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Farooq into the structure of Ko since Farooq teaches a stacked wafer structure.
The ordinary artisan would have been motivated to modify Farooq in combination with Ko in the above manner for the motivation of integrating a protective liner around the TSVs to isolate and protect the electric current in the device in an optimal manner as chip feature size continues to shrink and space is limited in a semiconductor structure. [0004] states, “Integrated circuit technology has steadily advanced to increase the number and density of devices on a chip by decreasing the feature size.”
Re Claim 4 Ko in view of Farooq teaches the method of claim 1, wherein the plurality of crack-stopping TSVs (Ko, TSV1, TSV2, CS1) are formed on both sides and along an extending direction of the first scribe lane (SR1) and the second scribe lane (SR2, considering FIG. 1 and FIG. 4 shows the TSV’s will appear on each side of a scribe lane).
Re Claim 5 Ko in view of Farooq teaches the method of claim 4, wherein the plurality of crack-stopping TSVs (Ko, TSV1, TSV2, CS1) comprise continuously distributed or separately distributed TSVs (TSV1 and TSV2 are continuous, CS1 is separately distributed, FIG. 4).
Re Claim 8 Ko in view of Farooq teaches the method of claim 1, wherein the protective material (Farooq, 362/364 are same parts as 262/264, [0032] states, “…sidewall coatings 264 and 262 can be deposited. The sidewall coating can be formed using any material appropriate for passivation layer 260.”, and [0029] says 260 can be silicon nitride) comprises one or more of copper, tungsten, aluminum, tantalum, titanium, tantalum nitride, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, carbide silicon, silicon carbonitride, polyimide and tetraethyl orthosilicate.
Re Claim 10 Ko teaches a wafer having crack-stopping through-silicon-vias (FIG. 4), comprising:
a first wafer body (100) [0092] and a second wafer body (200) [0092] that are stacked together, the first wafer body having a first scribe lane (SR1) [0093] for die cutting, the second wafer body having a second scribe lane (SR2) [0099] for die cutting (FIG.4);
a plurality of first crack-stopping through-silicon-vias (TSVs) (TSV1 and CS1) [0093] on a side of the first scribe lane (SR1, claim language does not require TSV to be in scribe lane region) of the first wafer body (100),
a plurality of second crack-stopping TSVs (TSV2) on a side of the second scribe lane (SR2, claim language does not require TSV to be in scribe lane region) of the second wafer body (200), wherein each of the plurality of second crack-stopping TSVs (TSV2) is aligned to one of the plurality of first crack-stopping TSVs (TSV1 and CS1) and exposes a surface of the one of the plurality of first crack-stopping TSVs (TVS1 and TSV2 are both connected to 310, and part of the top surface of TSV1 is exposed, FIG. 4)
wherein the plurality of first crack-stopping TSVs (TSV1 and CS1) and the plurality of second crack-stopping TSVs (TSV2) constitute plurality of crack-stopping TSVs (FIG. 4).
Ko does not teach each of the plurality of first crack-stopping TSVs is filled with a protective material; and
each of the plurality of second crack-stopping TSVs is filled with the protective material;
Farooq teaches filling each of the plurality of crack stopping TSVs with a protective material (362/362, [0036], FIG. 5). Farooq does explicitly teach two separate plurality sets of TSVs, but the process can be repeated for a 2nd wafer/structure.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Farooq into the structure of Ko since Farooq teaches a stacked wafer structure.
The ordinary artisan would have been motivated to modify Farooq in combination with Ko in the above manner for the motivation of integrating a protective liner around the TSVs to isolate and protect the electric current in the device in an optimal manner as chip feature size continues to shrink and space is limited in a semiconductor structure. [0004] states, “Integrated circuit technology has steadily advanced to increase the number and density of devices on a chip by decreasing the feature size.”
Re Claim 11 Ko in view of Farooq teaches the wafer of claim 10, wherein the plurality of crack-stopping TSVs (Ko, TSV1, TSV2, CS1) are formed on both sides and along an extending direction of the first scribe lane (SR1) and the second scribe lane (SR2, considering FIG. 1 and FIG. 4 shows the TSV’s will appear on each side of a scribe lane).
Re Claim 12 Ko in view of Farooq teaches the wafer of claim 11, wherein the plurality of crack-stopping TSVs (Ko, TSV1, TSV2, CS1) comprises continuously distributed or separately distributed TSVs (TSV1 and TSV2 are continuous, CS1 is separately distributed, FIG. 4).
Re Claim 15 Ko in view of Farooq teaches the wafer of claim 10, wherein the protective material (Farooq, 362/364 are same parts as 262/264, [0032] states, “…sidewall coatings 264 and 262 can be deposited. The sidewall coating can be formed using any material appropriate for passivation layer 260.”, and [0029] says 260 can be silicon nitride) comprises one or more of copper, tungsten, aluminum, tantalum, titanium, tantalum nitride, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, carbide silicon, silicon carbonitride, polyimide and tetraethyl orthosilicate.
Re Claim 17 Ko in view of Farooq teaches a semiconductor device (Ko, FIG. 4), comprising multiple wafers (100 and 200) [0092] each disclosed of claim 10, wherein the multiple wafers are stacked together (FIG. 4).
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (US 20160056113 A1) in view of Farooq et al. (US 20110193197 A1) and further in view of Gratz et al. (US 20140264767 A1, IDS)
Re Claim 6 Ko in view of Farooq teaches the method of claim 4, but does not teach the plurality of crack-stopping TSVs are distributed in multiple rows on one side of the first scribe lane and the second scribe lane.
Gratz teaches the plurality of crack-stopping TSVs (108a 108b) [0045] are distributed in multiple rows on one side of the first scribe lane (FIG 3 and 4 shows TSVs extend with first scribe lane, and FIG 8 shows wafer pattern from FIG 3 repeating, so 108a and 108b would be on same side of a single TSV). Gratz does not explicitly teach a second scribe lane, but the process can be repeated.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Gratz into the structure of Ko in view of Farooq since Gratz teaches a wafer structure with a scribe lane integrated to the design.
The ordinary artisan would have been motivated to modify Gratz in combination with Ko in view of Farooq in the above manner for the motivation of distributing multiple rows on one side of a scribe lane to allow for easy dicing at the end of the manufacturing line. [0002] states, “The wafer needs to be separated or diced for obtaining the individual integrated circuit chips which may be subjected to further processing steps, e.g., packaging.”
Re Claim 13 Ko in view of Farooq teaches the wafer of claim 11, but does not teach the plurality of crack-stopping TSVs are distributed in multiple rows on one side of the first scribe lane and the second scribe lane.
Gratz teaches the plurality of crack-stopping TSVs (108a 108b) [0045] are distributed in multiple rows on one side of the first scribe lane (FIG 3 and 4 shows TSVs extend with first scribe lane, and FIG 8 shows wafer pattern from FIG 3 repeating, so 108a and 108b would be on same side of a single TSV). Gratz does not explicitly teach a second scribe lane, but the process can be repeated.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Gratz into the structure of Ko in view of Farooq since Gratz teaches a wafer structure with a scribe lane integrated to the design.
The ordinary artisan would have been motivated to modify Gratz in combination with Ko in view of Farooq in the above manner for the motivation of distributing multiple rows on one side of a scribe lane to allow for easy dicing at the end of the manufacturing line. [0002] states, “The wafer needs to be separated or diced for obtaining the individual integrated circuit chips which may be subjected to further processing steps, e.g., packaging.”
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (US 20160056113 A1) in view of Farooq et al. (US 20110193197 A1) and further in view of Chen et al. (US 20130187277 A1).
Re Claim 7 Ko in view of Farooq teaches the method of claim 1, but does not teach a width of each of the plurality of crack-stopping TSVs is in the range from 2 microns to 20 microns, and a depth of each of the plurality of crack-stopping TSVs is in the range from 15 microns to 150 microns.
Chen teaches a width of each of the plurality of crack-stopping TSVs (116) [0014] is half of its height (claim 3), and the depth of each of the plurality of crack-stopping TSVs is over 15 microns making the width over 7.5 microns (FIG. 7).
The ordinary artisan would have been motivated to modify Chen in combination with Ko in view of Farooq in the above manner since Chen teaches a semiconductor structure with crack stopping structures.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal crack stopping TSV dimensions.
Re Claim 14 Ko in view of Farooq teaches the wafer according to claim 10, but does not teach a width of each of the plurality of crack-stopping TSVs is in the range from 2 microns to 20 microns, and a depth of each of the plurality of crack-stopping TSVs is in the range from 15 microns to 150 microns.
Chen teaches a width of each of the plurality of crack-stopping TSVs (116) [0014] is half of its height (claim 3), and the depth of each of the plurality of crack-stopping TSVs is over 15 microns making the width over 7.5 microns (FIG. 7).
The ordinary artisan would have been motivated to modify Chen in combination with Ko in view of Farooq in the above manner since Chen teaches a semiconductor structure with crack stopping structures.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal crack stopping TSV dimensions.
Claims 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (US 20160056113 A1) in view of Farooq et al. (US 20110193197 A1) and further in view of Bao et al. (US 20160181208 A1).
Re Claim 9 Ko in view of Farooq teaches the method of claim 8, but does not teach an air gap is provided in at least one of the plurality of crack-stopping TSVs.
Bao teaches an air gap ([0038] states, “…the first opening 116 may be pinched-off or capped to form a line level air gap or first crack stop 128. In other words, the first crack stop 128 may be constructed from a pocket of air trapped in the first opening 116 …”) is provided in at least one of the plurality of crack-stopping TSVs (128, FIG. 3).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Bao into the structure of Ko in view of Farooq since Bao teaches a semiconductor device with crack stop layers.
The ordinary artisan would have been motivated to modify Bao in combination with Ko in view of Farooq in the above manner for the motivation of integrating air gaps into the crack stops to better protect the active regions of the semiconductor device. [0005] states, “By using the crack stop (e.g., air gap), it has been found that the cracks and delaminations will terminate at the crack stop, prior to reaching the active chip area.”
Re Claim 16 Ko in view of Farooq teaches the wafer of claim 15, but does not teach an air gap ([0038] states, “…the first opening 116 may be pinched-off or capped to form a line level air gap or first crack stop 128. In other words, the first crack stop 128 may be constructed from a pocket of air trapped in the first opening 116 …”) is provided in at least one of the plurality of crack-stopping TSVs (128, FIG. 3).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Bao into the structure of Ko in view of Farooq since Bao teaches a semiconductor device with crack stop layers.
The ordinary artisan would have been motivated to modify Bao in combination with Ko in view of Farooq in the above manner for the motivation of integrating air gaps into the crack stops to better protect the active regions of the semiconductor device. [0005] states, “By using the crack stop (e.g., air gap), it has been found that the cracks and delaminations will terminate at the crack stop, prior to reaching the active chip area.”
Response to Amendment
Applicant’s arguments with respect to claims 1 and 4-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/3/26
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