Prosecution Insights
Last updated: August 04, 2026
Application No. 17/040,954

WAFER AND METHOD OF MAKING, AND SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Apr 03, 2023
Priority
Jun 28, 2019 — CN 201910580407.9 +1 more
Examiner
CHAN, CANDICE
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Changxin Memory Technologies Inc.
OA Round
2 (Non-Final)
73%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
400 granted / 551 resolved
+4.6% vs TC avg
Strong +19% interview lift
Without
With
+19.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
31 currently pending
Career history
613
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
79.4%
+39.4% vs TC avg
§102
11.0%
-29.0% vs TC avg
§112
5.9%
-34.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 551 resolved cases

Office Action

§102 §103
DETAILED ACTION This Office action is in response to the amendment filed 8 January 2026. By this amendment, claims 1, 8 and 9 are amended; claims 2-3 are cancelled. Claims 1 and 4-16 are currently pending; claims 9-16 stand withdrawn. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 8 January 2026 have been fully considered but they are not persuasive. Regarding claim 1 as amended, Applicant references Figs. 10-11 and paragraph [0056] of the instant specification, arguing a “first scribe-lane through-silicon-via 230 be formed on the first wafer body 300 to expose the interfacial surface of the second wafer 400 . . . [t]he first scribe-lane through-silicon-vias 230 is filled with a protective material. Then a second scribe-lane through-silicon-via 240 is formed on the surface of the second wafer body” and that the first scribe-lane TSVs and the second scribe-lane TSVs are formed step by step. (Remarks, pp. 8-9.) In response to Applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the first scribe-lane through-silicon-vias are filled with protective material before the second scribe-lane through-silicon-vias are formed) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). It is noted that claim 1 does not require the above sequencing of steps as currently drafted. Claim Objections Claim 8 is objected to because of the following informalities: “a” at the end of line 2 should be deleted. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 4-5, and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2015/0069609 A1 to Farooq et al. (hereinafter “Farooq”). Regarding claim 1, Farooq (Figs. 1-7) discloses a wafer manufacturing method, comprising: providing a first wafer 102C (Fig. 1; ¶ 0022) and a second wafer stacking together 102B (Fig. 1, ¶ 0022), the first wafer has a first scribe lane 115 (Fig. 1; ¶ 0022) for die cutting, the second wafer has a second scribe lane 115 (Fig. 1; ¶ 0022) for die cutting; forming a plurality of first scribe-lane through-silicon-vias (TSVs) 424 (Fig. 4; ¶ 0025) at the first scribe lane, wherein each of the plurality of first scribe-lane TSVs passes through the first wafer 402C (Fig. 4; labeled 102C in Fig. 1) and exposes the surface of the second wafer 402B (Fig. 4; labeled 102B in Fig. 1), each of the plurality of first scribe-lane TSVs is filled with a protective material 628 (Fig. 6; ¶ 0027), forming a plurality of second scribe-lane TSVs 424 (Fig. 4; ¶ 0025) at the second scribe lane, wherein each of the plurality of second scribe-lane TSVs passes through the second wafer 402B (labeled 102B in Fig. 1) and exposes the surface of one of the plurality of first scribe-lane TSVs (424 in 402C); and where each of the plurality of second scribe-lane TSVs is filled with the protective material 628 (Fig. 6). Regarding claim 4, Farooq (Figs. 1-7) discloses the wafer manufacturing method of claim 1, wherein the plurality of first scribe-lane TSVs (728 disposed therein) comprises continuously distributed or separately distributed scribe-lane TSVs (Fig. 7, Fig. 8A for top-down view - no interruptions in structure 828 along dicing channel 815, thus “continuously distributed”; ¶ 0029). Regarding claim 5, Farooq (Fig. 7) discloses the wafer manufacturing method of claim 1, wherein the plurality of first scribe-lane TSVs (728 disposed therein) is distributed in multiple rows at the scribe lane (Fig. 7- row of 728 on each side of 715: left, right). Regarding claim 7, Farooq discloses the wafer manufacturing method of claim 1, wherein the protective material 628 comprises one or more of copper, tungsten, aluminum, tantalum, titanium, tantalum nitride, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, carbide silicon, silicon carbonitride, polyimide and tetraethyl orthosilicate (¶ 0027). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Farooq. Regarding claim 6, Farooq discloses the wafer manufacturing method of claim 1, wherein a width of each of the plurality of first scribe-lane TSVs is in the range from 2 microns to 50 microns (¶ 0026 - disclosing about 7-30 microns), and a depth of each of the plurality of first scribe-lane TSVs is in the range from 15 microns to 150 microns (¶ 0026 - disclosing 30-1000 microns). In the case where claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. MPEP § 2144.05(I). Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Farooq as applied to claim 7 above, and further in view of US 2011/0204488 A1 to Itou et al. (hereinafter “Itou”). Regarding claim 8, Farooq discloses the wafer manufacturing method according to claim 7, however fails to expressly disclose: wherein an air gap is provided in one of the plurality of first scribe-lane TSVs and one of the plurality of second scribe-lane TSVs. In the same field of endeavor, Itou (Fig. 17) discloses a wafer manufacturing method including an air gap 101 provided in a scribe-lane TSV 100 (¶ 0076; see Fig. 12 for labelled scribe-lane: 100 located on either side at scribe-lane 300, ¶ 0059). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include an air gap as disclosed by Itou in each wafer of the method of Farooq, i.e., in one of the plurality of first scribe-lane TSVs and one of the plurality of second scribe-lane TSVs, for the purpose of decreasing the likelihood of damage to the blade while performing dicing (Itou, ¶ 0081). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B. Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. CANDICE Y. CHAN Examiner Art Unit 2813 5 May 2026 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Apr 03, 2023
Application Filed
Dec 13, 2022
Response after Non-Final Action
Oct 09, 2025
Non-Final Rejection mailed — §102, §103
Jan 08, 2026
Response Filed
May 15, 2026
Final Rejection mailed — §102, §103
Jul 14, 2026
Response after Non-Final Action

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
73%
Grant Probability
92%
With Interview (+19.2%)
3y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 551 resolved cases by this examiner. Grant probability derived from career allowance rate.

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