Prosecution Insights
Last updated: April 19, 2026
Application No. 17/041,689

METHOD OF ASSEMBLING A SEMICONDUCTOR POWER MODULE COMPONENT AND A SEMICONDUCTOR POWER MODULE WITH SUCH A MODULE COMPONENT AND MANUFACTURING SYSTEM THEREFOR

Non-Final OA §103
Filed
Sep 25, 2020
Examiner
BRASFIELD, QUINTON A
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Danfoss Silicon Power GmbH
OA Round
5 (Non-Final)
72%
Grant Probability
Favorable
5-6
OA Rounds
3y 1m
To Grant
89%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allow Rate
312 granted / 435 resolved
+3.7% vs TC avg
Strong +17% interview lift
Without
With
+17.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
26 currently pending
Career history
461
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
69.6%
+29.6% vs TC avg
§102
14.9%
-25.1% vs TC avg
§112
14.4%
-25.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 435 resolved cases

Office Action

§103
DETAILED ACTION This office action is in response to the RCE and amendments/arguments filed on 1/23/2026. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114 was filed in this application after a decision by the Patent Trial and Appeal Board, but before the filing of a Notice of Appeal to the Court of Appeals for the Federal Circuit or the commencement of a civil action. Since this application is eligible for continued examination under 37 CFR 1.114 and the fee set forth in 37 CFR 1.17(e) has been timely paid, the appeal has been withdrawn pursuant to 37 CFR 1.114 and prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant’s submission filed on 1/23/2026 has been entered. Accordingly, pending in this office action are claims 1-4,7-19 and 21-23. Claims 10-12, 14-18 are withdrawn as Non-Elected claims. Claims 5-6 and 20 are canceled. Information Disclosure Statement The information disclosure statements (IDS) submitted on 9/25/2020, 12/14/2020 and 9/18/2024 are being considered by the examiner. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 1, 2, 4, 7-9, 13, 19, 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Hohlfeld (US 2012/0080799) in view of Okamura (JP 29270091 A) and in further view of Busche (US 2017/0117162). With respect to Claim 1, Hohlfeld shows (Fig 14-15) most aspects of the current invention including a method of assembling a semiconductor power module component comprising at least a first element (8), a second element (2), and a third element (1) arranged in a stack, wherein the first element and the second element are joined by sintering in a sintering area (81) (par 67), and the second element and the third element are joined by soldering in a soldering area (4) (par 36), wherein the soldering area is heated to a temperature of soldering (par 41) and the sintering area is heated to a temperature of sintering (par 38 and 41), wherein pressure (par 59) is applied to the stack comprising the soldering area and the sintering area (implicit from par 73) with stabilizing means (3) being arranged in the soldering area (see fig 1-3, 14-17; par 50), wherein the stabilizing means is solid spacer means (see Fig 4-6, Fig 7-8B, 11A-11B; par 46) placed between the second element and the third element. Furthermore, Hohlfeld shows the solid spacer means is incorporated with soldering material to form a solder preform before the solid spacer means is arranged between the second element and the third element (see Fig 14A-14B; par 55; The solder 4 can be applied, for example, as a preform solder in an overall thickness D4 ranging from 50 µm to 500 µm or from 50 µm to 300 µm to the metal surface it and/or to the bottom side of the insert 3 facing the metal surface 1t, or it can top the metal surface it as a prefabricated solder pad). Hohlfeld does not explicitly disclose wherein the solid spacer means is fully incorporated with soldering material to form a solder preform before the solid spacer means is arranged between the second element and the third element and wherein the sintering and the soldering are simultaneously executed and the temperature of soldering and the temperature of sintering being harmonized to each other. On the other hand, and in a related field of endeavor, Okamura teaches (Fig 1) a first element (1), a second element (2), and a third element (3) arranged in a stack, wherein the second element and the third element are joined by soldering in a soldering area (5b) (par 27) and further a stabilizing means (4) being arranged in the soldering area, wherein the stabilizing means is solid spacer means (net-like sheet made of Ni fibers) that is fully incorporated with soldering material to form a solder preform before the solid spacer means is arranged between the second element and the third element (par 9; the net or net-like sheet is used as a composite solder sheet in which a solder layer is previously formed on its surface before assembling as a semiconductor device). Okamura teaches by arranging the composite solder material in which the solder layer is formed on the surface of the mesh sheet in advance before assembling the semiconductor device, workability and reliability of the joint portion are improved (par 20-22). Additionally a more reliable bonding layer is formed (par 9-11). Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the solid spacer means is fully incorporated with soldering material to form a solder preform before the solid spacer means is arranged between the second element and the third element, in the device of Hohlfeld, as taught by Okamura because by arranging the composite solder material in which the solder layer is formed on the surface of the mesh sheet in advance before assembling the semiconductor device, workability and reliability of the joint portion are improved and additionally a more reliable bonding layer is formed. However, Okamura does not explicitly disclose wherein the sintering and the soldering are simultaneously executed and the temperature of soldering and the temperature of sintering being harmonized to each other. On the other hand, and in a related field of endeavor, Busche teaches (Fig 1-3) a first element (12), a second element (13), and a third element (31) arranged in a stack, wherein the first element, second element and third element may be joined together by soldering or sintering (par 47-48), wherein the sintering and the soldering are simultaneously executed (par 43) and the temperature of soldering and the temperature of sintering being harmonized to each other (par 45). Busche teaches the greater the number of different joining levels that can be incorporated in one working step during the manufacture of the connections, the greater the extent to which the mounting process is simplified, which ultimately also has an advantageous effect on the profitability of said process (par 43). It would have been obvious at the time of the invention to one having ordinary skill in the art, or before the effective filing date of the invention to incorporate wherein the sintering and the soldering are simultaneously executed and the temperature of soldering and the temperature of sintering being harmonized to each other in the device of Hohlfeld and Okamura for the reason that the greater the number of different joining levels that can be incorporated in one working step during the manufacture of the connections, the greater the extent to which the mounting process is simplified, which ultimately also has an advantageous effect on the profitability of said process. With respect to Claim 2, Busche teaches (Fig 1-3) wherein pressure is applied to a complete area of the module component comprising at least the first element, the second element and the third element being component parts to be assembled together (par 62). With respect to Claim 4, Okamura teaches (Fig 1) wherein the stabilizing means remains solid during soldering. With respect to Claim 7, Okamura teaches (Fig 1) wherein the solder preform comprises substantially spherical bodies made of metal, glass or ceramics or comprises a wire mesh (par 9; net-like sheet made of Ni fibers) With respect to Claim 8, Hohlfeld shows (Fig 14A-15) wherein the second element is a DCB substrate and/or the third element is a base plate. With respect to Claim 9, Hohlfeld shows (Fig 14A-15) wherein additional component parts (8) are sintered onto the first element and/or the second element simultaneously with the sintering and the soldering of the stack. With respect to Claim 13, Hohlfeld shows (Fig 14A-15) a method of assembling a semiconductor power module comprising a semiconductor power module component assembled according to claim 1. With respect to Claim 19, Hohlfeld shows (Fig 14A-15) a method of assembling a semiconductor power module comprising a semiconductor power module component as claimed in claim 1, and wherein connections are made to the upper face of the substrate, using wire bonds (82) and in which the semiconductor power module component is encapsulated using a mold compound or attached to a frame (6) with a lid (62) and with a silicone protective filling (51) (par 71). With respect to Claim 22, Okamura teaches (Fig 1) wherein the wire mesh is made of metal (par 9; net-like sheet made of Ni fibers). With respect to Claim 23, Okamura teaches (Fig 1) wherein the wire mesh is made of metal (nickel). However, Okamura does not teach wherein the wire mesh is made of copper. Alternatively, Hohlfeld discloses (Fig 14A-15) wherein the wire mesh is made of copper (see Fig 6-8B; par 38: preform is made of a metal and par 61; perform mad be made of copper). Hohlfeld discloses copper are known to be equivalent materials for their use as wire mesh of a stabilizing means. Accordingly, it would have been obvious at the time of the invention to one having ordinary skill in the art, or before the effective filing date of the invention to use either Ni or Cu as the wire mesh material used as a stabilizing means, in the structure of Hohlfeld in view of Okamura and in further view of Busche, as suggested by Hohlfeld, because these were known in the semiconductor art as being equivalent, and good conduction materials for wire mesh material used as a stabilizing means and selecting among them would have been obvious to the skilled artisan. See In re KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007). Claims 3 are rejected under 35 U.S.C. 103 as being unpatentable over Hohlfeld (US 2012/0080799) in view of Busche (US 2017/0117162) and in further view of Bergmann (WO 2018/065483 A1) and Sugaya (US 2004/0145044). With respect to Claim 3, Hohlfeld shows (Fig 14-15) most aspects of the current invention including a method of assembling a semiconductor power module component comprising at least a first element (8), a second element (2), and a third element (1) arranged in a stack, wherein the first element and the second element are joined by sintering in a sintering area (81) (par 67), and the second element and the third element are joined by soldering in a soldering area (4) (par 36), wherein the soldering area is heated to a temperature of soldering (par 41) and the sintering area is heated to a temperature of sintering (par 38 and 41), wherein pressure (par 59) is applied to the stack comprising the soldering area and the sintering area (implicit from par 73) with stabilizing means (3) being arranged in the soldering area (see fig 1-3, 14-17; par 50). Hohlfeld does not explicitly disclose wherein the sintering and the soldering are simultaneously executed and the temperature of soldering and the temperature of sintering being harmonized to each other and wherein the stabilizing means are bumps on a surface of the second element facing the third element or on a surface of the third element facing the second element, wherein the bumps are part of the second or third element, and wherein the bumps are configured to provide sufficient space between the second element and the third element such that, at the sintering temperature, soldering material liquidized between the second element and the third element will not squeeze out when the pressure is applied. On the other hand, and in a related field of endeavor, Busche teaches (Fig 1-3) a first element (12), a second element (13), and a third element (31) arranged in a stack, wherein the first element, second element and third element may be joined together by soldering or sintering (par 47-48), wherein the sintering and the soldering are simultaneously executed (par 43) and the temperature of soldering and the temperature of sintering being harmonized to each other (par 45). Busche teaches the greater the number of different joining levels that can be incorporated in one working step during the manufacture of the connections, the greater the extent to which the mounting process is simplified, which ultimately also has an advantageous effect on the profitability of said process (par 43). It would have been obvious at the time of the invention to one having ordinary skill in the art, or before the effective filing date of the invention to incorporate wherein the sintering and the soldering are simultaneously executed and the temperature of soldering and the temperature of sintering being harmonized to each other in the device of Hohlfeld for the reason that the greater the number of different joining levels that can be incorporated in one working step during the manufacture of the connections, the greater the extent to which the mounting process is simplified, which ultimately also has an advantageous effect on the profitability of said process Furthermore, Busche does not explicitly teach wherein the stabilizing means are bumps on a surface of the second element facing the third element or on a surface of the third element facing the second element, wherein the bumps are part of the second or third element, and wherein the bumps are configured to provide sufficient space between the second element and the third element such that, at the sintering temperature, soldering material liquidized between the second element and the third element will not squeeze out when the pressure is applied. On the other hand, and in a related field of endeavor, Bergmann teaches (Fig 1) a first element (par 25; carrier including 1, 2a, 2b) and a second element (4) joined by soldering in a soldering area (3), and further comprising a stabilizing means (3a) being arranged in the soldering area, wherein the stabilizing means are bumps on a surface (surface 0) of the first element facing the second element or on a surface of the second element facing the first element. Bergmann teaches (see Bergmann par 7-8) using a solder layer which has spacer particles distributed in the solder mass and the solder layer which connects the at least one power component to the carrier is at least 100 µm thick; and the thickness reduces the shear stresses in the solder layer, which arise from different temperature expansion of the carrier and the power component. With the spacer particles, the solder layer or its thickness can be achieved in a simple and relatively precise manner during the manufacturing process. In addition, and in a related field of endeavor, Sugaya teaches (Fig 2A-2F) a first element (carrier 207) and a second element (chip 203) joined by soldering in a soldering area (element 206) and further comprising a stabilizing means (bumps 205) being arranged in the soldering area, wherein the stabilizing means are bumps on a surface of the second element facing the first element, and wherein the bumps are part of the second element (par 60-61; Sugaya teaches bumps 205 are on chip 203 and element 206 is a sealing resin, a non-conductive film (NCF) or an anisotropic conductive film (ACF) containing conductive particles the may be used to suppress the concentration of the stress when connecting the chip to the patterns 202c on the carrier). Additionally, the bumps are configured to provide sufficient space between the second element and the third element such that, at the sintering temperature, soldering material liquidized between the second element and the third element will not squeeze out when the pressure is applied (see Fig 2D-2E; the soldering material does not squeeze out when the pressure is applied) Therefore, it would have been obvious at the time of the invention to one having ordinary skill in the art, or before the effective filing date of the invention to incorporate wherein the stabilizing means are a solid spacer or bumps on a surface of the second element facing the third element or on a surface of the third element facing the second element, wherein the bumps are part of the second element, and further wherein the bumps are configured to provide sufficient space between the second element and the third element such that, at the sintering temperature, soldering material liquidized between the second element and the third element will not squeeze out when the pressure is applied in the device of Hohlfeld in view of Busche and in further view of Bergmann and Sugaya, as taught by Sugaya to suppress the concentration of the stress when connecting a first element to a second element. Claim 7 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Hohlfeld (US 2012/0080799) in view of Okamura (JP 29270091 A) and in further view of Busche (US 2017/0117162) and Bergmann (WO 2018/065483 A1). With respect to Claim 7, in a second interpretation of the claim, Hohlfeld in view Okamura and Busche shows most aspects of the present invention (see above par 6-9, and 11). However, the combination of references do not show wherein the solder preform comprises substantially spherical bodies made of metal. On the other hand, and in a related field of endeavor, Bergmann teaches (Fig 1) a first element (par 25; carrier including 1, 2a, 2b) and a second element (4) joined by soldering in a soldering area (3), and further comprising a stabilizing means (3a) being arranged in the soldering area, wherein the solid spacer means is incorporated with soldering material to form a solder preform, wherein the solder preform comprises substantially spherical bodies made of metal (See Bergmann par 26-27). Bergmann teaches (see par 7-8) using a solder layer which has spacer particles distributed in the solder mass and the solder layer which connects the at least one power component to the carrier is at least 100 µm thick; and the thickness reduces the shear stresses in the solder layer, which arise from different temperature expansion of the carrier and the power component. With the spacer particles, the solder layer or its thickness can be achieved in a simple and relatively precise manner during the manufacturing process. Therefore, it would have been obvious at the time of the invention to one having ordinary skill in the art, or before the effective filing date of the invention to incorporate wherein the stabilizing means are a solid spacer or bumps and wherein the solder preform comprises substantially spherical bodies made of metal, in the device of Hohlfeld in view Okamura and Busche, as taught by Bergmann because using a solder layer which has spacer particles distributed in the solder mass and the solder layer which connects the at least one power component to the carrier is at least 100 µm thick; and the thickness reduces the shear stresses in the solder layer, which arise from different temperature expansion of the carrier and the power component. With the spacer particles, the solder layer or its thickness can be achieved in a simple and relatively precise manner during the manufacturing process. With respect to Claim 21, in a second interpretation of the claim, Bergmann teaches (Fig 1) a first element (par 25; carrier including 1, 2a, 2b) and a second element (4) joined by soldering in a soldering area (3), and further comprising a stabilizing means (3a) being arranged in the soldering area, wherein the solid spacer means is incorporated with soldering material to form a solder preform, wherein the solder preform comprises substantially spherical bodies made of copper (See Bergmann par 26-27). Also, see comments stated above in Par. 38-40 with regards to Claim 7, which are considered repeated here. Response to Arguments Applicant's amendments/arguments filed on 1/23/2026 have been fully considered and are not persuasive. Applicant’s arguments with respect to claims 1-2, 4, 7-9, 19 and 21-23 have been considered but are moot because the new ground of rejection provided above teaches the matter specifically challenged in the argument. With respect to claim 3, the examiner maintains the rejection and further clarifies the matter specifically challenged in the argument of claim 3. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUINTON A BRASFIELD whose telephone number is (571)272-0804. The examiner can normally be reached M-F 9AM-6PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Q.A.B/Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
Read full office action

Prosecution Timeline

Sep 25, 2020
Application Filed
Sep 25, 2020
Response after Non-Final Action
Jan 10, 2023
Non-Final Rejection — §103
Mar 23, 2023
Response Filed
Sep 01, 2023
Final Rejection — §103
Nov 07, 2023
Response after Non-Final Action
Dec 08, 2023
Non-Final Rejection — §103
Dec 08, 2023
Response after Non-Final Action
Feb 20, 2024
Response Filed
May 18, 2024
Final Rejection — §103
Jul 19, 2024
Response after Non-Final Action
Aug 13, 2024
Notice of Allowance
Aug 30, 2024
Response after Non-Final Action
Sep 13, 2024
Response after Non-Final Action
Dec 04, 2024
Response after Non-Final Action
Jan 14, 2025
Response after Non-Final Action
Jan 15, 2025
Response after Non-Final Action
Jan 16, 2025
Response after Non-Final Action
Jan 16, 2025
Response after Non-Final Action
Nov 24, 2025
Response after Non-Final Action
Jan 23, 2026
Request for Continued Examination
Feb 03, 2026
Response after Non-Final Action
Feb 07, 2026
Non-Final Rejection — §103 (current)

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Prosecution Projections

5-6
Expected OA Rounds
72%
Grant Probability
89%
With Interview (+17.3%)
3y 1m
Median Time to Grant
High
PTA Risk
Based on 435 resolved cases by this examiner. Grant probability derived from career allow rate.

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