DETAILED ACTION
Claims 1 and 3-17 are pending
Claims 8-14 have been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 26, 2025, has been entered.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Notes/Recommendations
In anticipation of rejoining the withdrawn claims, the examiner has examined them for informalities and 112 issues. The examiner recommends addressing the following:
In claim 8, last two lines, there is a lack of antecedent basis for both instances of “the opcode” since there is an opcode in line 2 and another in line 4.
In claim 9, line 2, “the opcode” lacks basis for similar reasoning.
In claim 9, each instance of “the S-bit opcode” lacks basis because there is an S-bit opcode in claim 8, line 4, and another in claim 9, line 5.
In claim 14, each instance of “the J-bit reference address” lacks basis because there are multiple instances of “a J-bit address” in claim 13 (lines 2 and 6).
Claim Interpretation
The following is a quotation of MPEP 2111.04(II):
“The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.”
“The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.”
Regarding claim 15, when a predetermined type of instruction is not decoded, the steps of the last paragraph are not performed and are thus not required by the claimed method. The examiner recommends claiming a step of --decoding a predetermined type of instruction…-- and then starting the last paragraph with --in response to decoding the predetermined type of instruction…--. Thus will require the steps of the last paragraph to be performed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 15 is firstly rejected under 35 U.S.C. 102(a)(1) as being anticipated by Damron, U.S. Patent No. 7,210,026.
Referring to claim 15, Damron has taught a data processing method comprising:
receiving a program instruction (at least one of FIGs.2A-C, 2E, and 3A-B) to be processed according to a predetermined architecture defining a plurality of architectural registers accessible in response to the program instructions (from FIG.3A, note field 306, which identifies one of registers 352 (e.g. FIG.3C), and field 308, which identifies one of registers 354 (e.g. FIG.3C). All registers accessible by the instructions are architectural registers defined by the architecture);
transferring data corresponding to at least one architectural register from a corresponding register emulating memory location in memory to at least one of a set of hardware registers (see FIG.3B and FIG.4), wherein a storage capacity of the set of hardware registers is insufficient for storing data associated with all of the plurality of architectural registers of the predetermined architecture (from FIG.4, there is unimplemented register space, meaning that there are more architectural registers than hardware registers. For instance, see column 7, lines 51-61, which sets forth that field 308 is a 13-bit field capable of identifying 8192 architectural registers. However, from column 8, lines 3-28, fewer than 8192 registers may be implemented, with the remaining “registers” being emulated by locations in a memory region pre-reserved for this purpose); and
processing the program instruction using the set of hardware registers (FIGs.2A-C, 2E, and 3A-B. Also, see column 7, lines 27-30, for instance);
wherein the set of hardware registers comprises a program counter register to store a program counter identifying a program instruction to be processed by the processing circuitry (a program counter (PC) register must exist within Damron to fetch instructions from memory. A PC register stores the memory address of the next instruction to fetch. In response, fetch logic will lookup memory at that address to obtain the next instruction for processing); and
(these limitations are not required by the claim as they are contingent on decoding a predetermined type of instruction. When such an instruction does not exist, it cannot be decoded to perform the steps in the last paragraph. However, even if such an instruction did exist, a program does not require inclusion of every possible instruction in the instruction set. As such, when not included in a program, it cannot be decoded to perform the steps in the last paragraph).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Damron in view of Bright et al., U.S. Patent No. 6,523,110.
Referring to claim 1, Damron has taught an apparatus comprising:
processing circuitry (FIG.1) to process program instructions (at least FIGs.2A-C, 2E, and 3A-B) in accordance with a predetermined architecture defining a plurality of architectural registers accessible in response to the program instructions (from FIG.3A, note field 306, which identifies one of registers 352 (e.g. FIG.3C), and field 308, which identifies one of registers 354 (e.g. FIG.3C). All registers accessible by the instructions via these instruction fields are architectural registers defined by the architecture);
a set of hardware registers (see FIG.4, at least registers 402 and 404 (non-dashed portion)), wherein a storage capacity of the set of hardware registers is insufficient for storing data associated with all of the plurality of architectural registers of the predetermined architecture (from FIG.4, there is unimplemented register space, meaning that there are more architectural registers than hardware registers. For instance, see column 7, lines 51-61, which sets forth that field 308 is a 13-bit field capable of identifying 8192 architectural registers. However, from column 8, lines 3-28, fewer than 8192 registers may be implemented, with the remaining “registers” being emulated by locations in a memory region pre-reserved for this purpose (See the dashed portion in FIG.4)); and
control circuitry responsive to the program instructions to transfer data between the set of hardware registers and at least one register-emulating memory location in memory for storing data corresponding to at least one of the plurality of architectural registers of the predetermined architecture (see FIG.3B and FIG.4);
wherein the set of hardware registers comprises a program counter register to store a program counter identifying a program instruction to be processed by the processing circuitry (a program counter (PC) register must exist within Damron to fetch instructions from memory. A PC register stores the memory address of the next instruction to fetch. In response, fetch logic will lookup memory at that address to obtain the next instruction for processing); and
Damron has not taught in response to decoding a predetermined type of instruction for triggering the processing circuitry to perform a processing operation, the control circuitry is configured to write the program counter to memory, the processing circuitry is configured to use the program counter register to store at least one data value during processing of said predetermined type of instruction, and following said processing operation, the control circuitry is configured to read the program counter from memory to recover the program counter before fetching the next instruction to be executed by the processing circuitry after the predetermined type of instruction. However, Bright has taught branch prediction, which is known to reduce stalls and speed up processing related to branch paths by starting processing of a predicted branch path before the outcome of the branch is known. See column 1, line 60, to column 2, line 4, and to the background of Bright in general. Branch instructions flexibly allow for execution of different paths of code depending on some condition. And, part of branch prediction involves correcting mispredictions. One way to do this is to store sequential program counter value into a state register (memory). This register would later be used to restore the program counter in response to mispredicting that a branch is taken. See column 9, lines 45-62. As a result, in order to realize branch functionality, increased throughput/speed by predicting branches, and appropriate recovery from mispredictions to ensure correct execution, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Damron to execute branch instructions, predict their outcomes, and also to implement the state register memory to store the correct program counter value for misprediction purposes.
Given this modification, the combination teaches:
in response to decoding a predetermined type of instruction for triggering the processing circuitry to perform a processing operation (Bright, column 9, lines 50-60; in response to decoding an instruction of the branch type, which triggers branch-related operation), the control circuitry is configured to write the program counter to memory (Bright column 9, lines 50-60; when a branch is to be predicted taken, the sequential address, i.e., the address of the instruction immediately after the branch instruction is the program counter value ultimately used to fetch the instruction immediately after the branch instruction),
the processing circuitry is configured to use the program counter register to store at least one data value during processing of said predetermined type of instruction (when the branch instruction is predicted taken in Bright, the predicted target address is stored in the program counter register, as is known in the art, so as to begin fetching an instruction of the predicted branch path), and
following said processing operation, the control circuitry is configured to read the program counter from memory to recover the program counter before fetching the next instruction to be executed by the processing circuitry after the predetermined type of instruction (following the branch being processed, the system would determine that a misprediction occurred, i.e., that the sequential path should have been fetched instead of the taken path. As such, the program counter would be recovered by loading the sequential address from the state register (memory) into the program counter register. The recovered program counter would then be used to fetch the correct instruction, i.e., the instruction immediately following the branch that is to be executed).
Referring to claim 5, Damron, as modified, has taught the apparatus according to claim 1, wherein the set of hardware registers comprises two N-bit operand registers to store operand values to be processed by the processing circuitry (see FIG.2C and column 6, lines 41-50. Registers identified by fields 246 and 248 store N-bit values to be added. For instance, from column 4, lines 41-43, N = 64).
Referring to claim 15, Damron has taught a data processing method comprising:
receiving a program instruction (at least FIGs.2A-C, 2E, and 3A-B) to be processed according to a predetermined architecture defining a plurality of architectural registers accessible in response to the program instructions (from FIG.3A, note field 306, which identifies one of registers 352 (e.g. FIG.3C), and field 308, which identifies one of registers 354 (e.g. FIG.3C). All registers accessible by the instructions are architectural registers defined by the architecture);
transferring data corresponding to at least one architectural register from a corresponding register emulating memory location in memory to at least one of a set of hardware registers (see FIG.3B and FIG.4), wherein a storage capacity of the set of hardware registers is insufficient for storing data associated with all of the plurality of architectural registers of the predetermined architecture (from FIG.4, there is unimplemented register space, meaning that there are more architectural registers than hardware registers. For instance, see column 7, lines 51-61, which sets forth that field 308 is a 13-bit field capable of identifying 8192 architectural registers. However, from column 8, lines 3-28, fewer than 8192 registers may be implemented, with the remaining “registers” being emulated by locations in a memory region pre-reserved for this purpose); and
processing the program instruction using the set of hardware registers (FIGs.2A-C, 2E, and 3A-B. Also, see column 7, lines 27-30, for instance);
wherein the set of hardware registers comprises a program counter register to store a program counter identifying a program instruction to be processed by the processing circuitry (a program counter (PC) register must exist within Damron to fetch instructions from memory. A PC register stores the memory address of the next instruction to fetch. In response, fetch logic will lookup memory at that address to obtain the next instruction for processing); and
Damron has not taught in response to decoding a predetermined type of instruction for triggering the processing circuitry to perform a processing operation, control circuitry is configured to write the program counter to memory, the processing circuitry is configured to use the program counter register to store at least one data value during processing of said predetermined type of instruction, and following said processing operation, the control circuitry is configured to read the program counter from memory to recover the program counter before fetching the next instruction to be executed by the processing circuitry after the predetermined type of instruction. However, Bright has taught branch prediction, which is known to reduce stalls and speed up processing related to branch paths by starting processing of a predicted branch path before the outcome of the branch is known. See column 1, line 60, to column 2, line 4, and to the background of Bright in general. Branch instructions flexibly allow for execution of different paths of code depending on some condition. And, part of branch prediction involves correcting mispredictions. One way to do this is to store sequential program counter value into a state register (memory). This register would later be used to restore the program counter in response to mispredicting that a branch is taken. See column 9, lines 45-62. As a result, in order to realize branch functionality, increased throughput/speed by predicting branches, and appropriate recovery from mispredictions to ensure correct execution, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Damron to execute branch instructions, predict their outcomes, and also to implement the state register memory to store the correct program counter value for misprediction purposes.
Given this modification, the combination teaches:
in response to decoding a predetermined type of instruction for triggering the processing circuitry to perform a processing operation (Bright, column 9, lines 50-60; in response to decoding an instruction of the branch type, which triggers branch-related operation), the control circuitry is configured to write the program counter to memory (Bright column 9, lines 50-60; when a branch is to be predicted taken, the sequential address, i.e., the address of the instruction immediately after the branch instruction is the program counter value ultimately used to fetch the instruction immediately after the branch instruction),
the processing circuitry is configured to use the program counter register to store at least one data value during processing of said predetermined type of instruction (when the branch instruction is predicted taken in Bright, the predicted target address is stored in the program counter register, as is known in the art, so as to begin fetching an instruction of the predicted branch path), and
following said processing operation, the control circuitry is configured to read the program counter from memory to recover the program counter before fetching the next instruction to be executed by the processing circuitry after the predetermined type of instruction (following the branch being processed, the system would determine that a misprediction occurred, i.e., that the sequential path should have been fetched instead of the taken path. As such, the program counter would be recovered by loading the sequential address from the state register (memory) into the program counter register. The recovered program counter would then be used to fetch the correct instruction, i.e., the instruction immediately following the branch that is to be executed).
Claim 16 is rejected for a subset of reasoning set forth in the rejection of claim 1.
Referring to claim 17, Damron, as modified, has taught the apparatus according to claim 1, wherein the processing operation for the predetermined type of instruction comprises a processing operation for which, without use of the program counter register to store said at least one data value, the set of hardware registers would provide insufficient capacity for supporting the processing operation for the predetermined type of instruction (taking the INT instruction of Kudo, this instruction requires that the address of the interrupt service routine (ISR) be stored in a program counter register. There is only one program counter register, which is the reason the contents thereof need to be saved so that the contents are not list when the address of the ISR is stored in the program counter register. Because the set of registers does not provide a second program counter register, the capacity of the set is insufficient to carry out INT without using the only program counter register in the system. Similar reasoning applies to the other rejections based on Kudo and Valvano (for any interrupt instruction, a PC register is needed so that the interrupt can be returned from. Since there is only one PC register, the set has otherwise insufficient capacity to carry out interrupt service routines).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Damron in view of Bright and Ball, U.S. Patent Application Publication No. 2005/0223198 A1.
Referring to claim 3, Damron, as modified, has taught the apparatus according to claim 1, but has not taught wherein the predetermined type of instruction comprises a multiply or divide instruction. However, Ball has taught a branch instruction that multiplies its immediate field by 4 before adding it to the current program counter address to obtain a target address (see paragraphs [0037]-[0038] and [0040]). One advantage gained from this multiplication is for proper alignment for byte addressing and expanded target range (paragraph [0040]). As a result, in order to realize these benefits, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Damron such that the predetermined type of instruction comprises a multiply instruction, i.e., a branch instruction that performs a multiply operation.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Damron in view of Bright and Gueron et al., U.S. Patent Application Publication No. 2014/0006755 A1.
Referring to claim 6, Damron, as modified, has taught the apparatus according to claim 5, but has not taught wherein in response to a multiply instruction for controlling the processing circuitry to multiply two N-bit operand values stored in the two operand registers to generate an N-bit result value representing a least significant N bits of a product of the two N-bit operand values, the processing circuitry is configured to accumulate the N-bit result value into one of said two operand registers. However, Gueron has taught a VPMULADDLO instruction that multiplies two operands of the same size (K bits), and from two operand registers, to generate a 2K-bit result, of which the lower K bits are accumulated with a value in one of the two operand registers (e.g. see paragraphs [0055] and [0063]). Multiply-accumulate is a known mathematical operation in the art and allowing for performance thereof would realize such functionality. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Damron such that in response to a multiply instruction for controlling the processing circuitry to multiply two N-bit operand values stored in the two operand registers to generate an N-bit result value representing a least significant N bits of a product of the two N-bit operand values, the processing circuitry is configured to accumulate the N-bit result value into one of said two operand registers.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Damron in view of Bright, Gueron, and McNally, “Design Specification 2003 - 4-bit Multiplier”.
Referring to claim 7, Damron, as modified, has taught the apparatus according to claim 6, but has not taught wherein in response to the multiply instruction, the processing circuitry is configured to perform an iterative process for generating the N-bit result value in a plurality of steps, each step comprising shifting out a bit of one of the operand values from said one of said two operand registers to accommodate an additional bit of an accumulator value representing a sum of partial products of said two operand values. However, McNally has taught a circuit performing such a process (see pp.1-2). For instance, in each iteration, a bit is shifted out of both operands (or just one in the second circuit shown) so as to create another bit in the accumulator value, which is a sum of partial products generated in iterations where the least significant bit of the multiplier is 1. There are many ways to implement multiplication circuitry and this one is deemed the simplest by McNally (see p.1). The second circuit is deemed more efficient. As a result, in order to design for simplicity or efficiency, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Damron such that in response to the multiply instruction, the processing circuitry is configured to perform an iterative process for generating the N-bit result value in a plurality of steps, each step comprising shifting out a bit of one of the operand values from said one of said two operand registers to accommodate an additional bit of an accumulator value representing a sum of partial products of said two operand values.
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable over the prior art if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant argues that the combination of prior art relied on by the pervious rejection does not teach the claims as amended.
The examiner agrees and has withdrawn those rejections. However, an updated search revealed another reference that may be combined with Damron to render the claims unpatentable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
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