DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/14/25 has been entered.
Response to Arguments
Applicant's arguments filed 10/14/25 have been fully considered but they are not persuasive.
First, the applicant argues:
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This argument is not persuasive because as seen in the below rejection, Ward teaches the amended limitation. The applicant’s argument cited a portion of Ward and referred to it as “generic component-level description.” However, the sentences that followed the cited portion of Ward gave more description, including describing the differences between a netlist, a layout, and design files that describe the layout. In the below rejection, the examiner considered the design file teachings of Ward to be analogous to the claimed correspondence relation.
Furthermore, in the applicant’s arguments, the applicant appears to be reading in many unclaimed elements, such as traces that correspond to Metal1, Metal2, Via1, Poly … DRC/LVS tool … Calibre, Assura, IVC … etc … The examiner notes that broadest reasonable interpretation (BRI) is given to the claimed limitations, and unclaimed limitations are not read in. Also, it appears that many of these elements mentioned by the applicant are also not supported in the applicant’s disclosure.
The examiner also notes that the applicant’s key argument begins with “It is well understood in the art …” The examiner is not clear whether the applicant is admitting prior art. However, the examiner suggests that the applicant may consider amending the claims with novel subject matter, rather than well-understood subject matter, if the amendment is meant to serve as a basis of patentability.
Next, the applicant argues:
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This argument is not persuasive because the applicant’s arguments focus on Blanton in a vacuum, while overlooking that Blanton served as a secondary reference to primary reference Ma et al. As seen in the below rejection, Ma et al explicitly discloses the applicant’s new amendment of, “wherein some of the defective points cause a final product to malfunction, and some of the defective points do not cause the final product to malfunction.” (see Ma et al paragraph 0011).
The applicant’s other arguments, with respect to art, are rendered moot, in view of the above rebuttal.
With respect to the 35 U.S.C. 101 rejection, the applicant argues:
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This argument is not persuasive for a number of reasons.
First, the claims do not merely “involve data processing.” Data processing is the entire solution. The applicant’s argument frames its first argument in the context of, “The Claims Are Rooted in a Specific Semiconductor Technology Problem.” However, the examiner considers the claimed solution. Here, the solution involves collecting data, training a model with data, and evaluating the data, such that a yield rate is predicted. However, this outcome stays on the computer. The claims do not positively recite changing the semiconductor manufacturing process or scrapping the chip/wafer, as a result of the predictions.
The applicant also argues that the claimed correspondence relation cannot be obtained by the human mind or ordinary computing. The applicant proceeds to give many technical details to establish that mental steps or generic processing are technically impossible. However, these details are not claimed, nor are many of these details supported in the applicant’s disclosure. The applicant’s support for the claimed limitations appears to be found in applicant’s figures 3-4, and these figures are easily digested and understandable to the human mind.
The applicant further argues integration into a practical application. However, as discussed above, the applicant’s claims appear to lie entirely in the realm of data processing, without positively reciting any structural transformations of the semiconductor manufacturing process. The applicant also argues elements, such as “LVS/DRC rule-based extraction … guided by foundry rule decks …” that are not actually claimed.
For the reasons above, the applicant’s arguments are not persuasive. The rejection is maintained.
Drawings
As discussed previously, the drawings filed on 11/05/24 are accepted.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: establishment unit, data acquisition unit, and machine learning unit in claims 8 and 15, as well as recognition unit and prediction unit in claim 8.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 3-8, 10-15, and 17-19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
With respect to step 1 of the patent subject matter eligibility analysis, the claims are directed to a process, machine, manufacture, or composition of matter. Independent claim 1 is directed to a yield rate prediction method, which is a process. Independent claim 8 is directed to a yield rate prediction system, which is a machine. Independent claim 15 is directed to a model training device, which is a machine. All other claims depend on independent claims 1, 8, and 15. As such, claims 1, 3-8, 10-15, and 17-19 are directed to a statutory category.
With respect to step 2A, prong one, the claims recite an abstract idea, law of nature, or natural phenomenon. Specifically, the following limitations recite mathematical concepts and/or mental processes.
Claim 1
establishing a correspondence relation between a circuit path of a netlist and an integrated circuit layout when the netlist does not include the correspondence relation, wherein the correspondence relation describes a correspondence between a position, a shape and an area of each hardware unit on each stacking layer and the circuit path (Establishing some sort of general correspondence relationship between a description of components and connections in an integrated circuit (i.e. a netlist) with the layout of the integrated circuit may be practically performed in the human mind by observation, evaluation, judgement, and/or opinion. It constitutes an abstract mental process.)
training a recognition model to recognize a fault occurred on the circuit path, wherein the recognition model is trained based on the correspondence relation between the circuit path of the netlist and the integrated circuit layout (paragraph 0031 of the applicant’s specification states, “In the present embodiment, the recognition model MD can be trained using a convolutional neural networks algorithm, a k-means clustering algorithm or a decision tree.” Because the recognition model is being trained on specific mathematical algorithms, it recites an abstract mathematical concept.)
recognizing, for each of the stacking layers, a probability of the fault of the circuit path of a semiconductor semi-final product according to the recognition model (Probability is an abstract mathematical concept, and recognizing that mathematical concept is an abstract mental process that can be performed by the human mind.)
predicting a yield rate of the semiconductor semi-final product according to the probability (making a prediction based on data, such as a probability, may be practically performed in the human mind by observation, evaluation, judgement, and/or opinion. It constitutes an abstract mental process.)
Claim 8
establish a correspondence relation between a circuit path of a netlist and an integrated circuit layout when the netlist does not include the correspondence relation, wherein the correspondence relation describes a correspondence between a position, a shape and an area of each hardware unit on each stacking layer and the circuit path (Establishing some sort of general correspondence relationship between a description of components and connections in an integrated circuit (i.e. a netlist) with the layout of the integrated circuit may be practically performed in the human mind by observation, evaluation, judgement, and/or opinion. It constitutes an abstract mental process.)
train a recognition model to recognize a fault of the circuit path, wherein the recognition model is trained based on the correspondence relation between the circuit path of the netlist and the integrated circuit layout (paragraph 0031 of the applicant’s specification states, “In the present embodiment, the recognition model MD can be trained using a convolutional neural networks algorithm, a k-means clustering algorithm or a decision tree.” Because the recognition model is being trained on specific mathematical algorithms, it recites an abstract mathematical concept.)
recognize, for each of the stacking layers, a probability of the fault occurred on the circuit path of a semiconductor semi-final product according to the recognition model (Probability is an abstract mathematical concept, and recognizing that mathematical concept is an abstract mental process that can be performed by the human mind.)
predict a yield rate of the semiconductor semi-final product according to the probability (making a prediction based on data, such as a probability, may be practically performed in the human mind by observation, evaluation, judgement, and/or opinion. It constitutes an abstract mental process.)
Claim 15
establish a correspondence relation between a circuit path of a netlist and an integrated circuit layout when the netlist does not include the correspondence relation, wherein the correspondence relation describes a correspondence between a position, a shape and an area of each hardware unit on each stacking layer and the circuit path (Establishing some sort of general correspondence relationship between a description of components and connections in an integrated circuit (i.e. a netlist) with the layout of the integrated circuit may be practically performed in the human mind by observation, evaluation, judgement, and/or opinion. It constitutes an abstract mental process.)
train a recognition model to recognize a fault of the circuit path, wherein the recognition model is trained based on the correspondence relation between the circuit path of the netlist and the integrated circuit layout (paragraph 0031 of the applicant’s specification states, “In the present embodiment, the recognition model MD can be trained using a convolutional neural networks algorithm, a k-means clustering algorithm or a decision tree.” Because the recognition model is being trained on specific mathematical algorithms, it recites an abstract mathematical concept.)
All dependent claims depend on independent claims 1, 8, and 15 and also recite their abstract limitations by virtue of their dependence. In addition, some of the dependent claims also recite their own abstract mathematical concepts and/or mental processes. For example, dependent claims 5, 12, and 19 disclose training the recognition model to recognize the fault on the circuit path according to positions shapes and areas of the defective points (The training of such a model inherently utilizes abstract mathematical calculations in order to perform its function.). Dependent claims 6-7 and 13-14 are directed to when the recognition and prediction occurs, but the act of recognizing and predicting still recite abstract mental processes.
With respect to step 2A, prong two, the claims do not recite additional elements that integrate the judicial exception into a practical application. The following limitations are considered “additional elements” and explanation will be given as to why these “additional elements” do not integrate the judicial exception into a practical application.
Claim 1
A yield rate prediction method of a semiconductor manufacturing process (This limitation is not indicative of integration into a practical application because it generally links the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h). No detail is given in terms of how the prediction method transforms or improves the semiconductor manufacturing process. There is just the general link.)
obtaining a plurality of defective points on a plurality of stacking layers (This limitation is directed to mere data gathering, recited at a high level of generality, which is considered insignificant extra-solution activity (see MPEP 2106.05(g)) The recitation of the stacking layers merely serve to link the judicial exception to a particular technological environment or field of use).
including a bridging fault and a stuck fault (This limitation is not indicative of integration into a practical application because it merely serves to generally link the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). The claims do not positively recite the structure of the circuit and the structural consequences to the circuit of a bridging fault and/or stuck fault. Rather, the bridging fault and stuck fault are presented as general technological context for the type of data that is processed.)
according to the defective points (This limitation is not indicative of integration into a practical application because it recites to the data that is used by the training model, and data, in itself, merely serves to add insignificant extra-solution activity (see MPEP 2106.05(g)). The “solution” is in the processing of the data and not the data itself.)
occurred on a current stacking layer and a further stacking layer (This limitation is not indicative of integration into a practical application because it merely serves to generally link the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). The claims do not positively recite the layers of the semiconductor in a structural manner. Here, they are references to provide general technological context for the type of data that is processed.)
wherein some of the defective points cause a final product to malfunction, and some of the defective points do not cause the final product to malfunction (This limitation is not indicative of integration into a practical application because it merely serves to generally link the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). The claims do not positively recite the layers of the semiconductor in a structural manner. Here, context about the defective points on the layers merely serve as references to provide general technological context for the type of data that is processed.)
Claim 8
A yield rate prediction system of a semiconductor manufacturing process (This limitation is not indicative of integration into a practical application because it generally links the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h). No detail is given in terms of how the prediction system transforms or improves the semiconductor manufacturing process. There is just the general link.)
a model training device; an establishment unit; a data acquisition unit; a machine learning unit; a prediction device; a recognition unit; and a prediction unit (These limitations are not indicative of integration into a practical application because they generally link the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). No detail is given in terms of the structure of these various elements; They are generically recited followed by an intended use/function. Furthermore, these elements appear to simply be components of a computer system, and merely using a computer as a tool to perform an abstract idea is not indicative of integration into a practical application (see MPEP 2106.05(f)).)
obtain a plurality of defective points on a plurality of stacking layers (This limitation is directed to mere data gathering, recited at a high level of generality, which is considered insignificant extra-solution activity (see MPEP 2106.05(g)) The recitation of the stacking layers merely serve to link the judicial exception to a particular technological environment or field of use).
including a bridging fault and a stuck fault (This limitation is not indicative of integration into a practical application because it merely serves to generally link the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). The claims do not positively recite the structure of the circuit and the structural consequences to the circuit of a bridging fault and/or stuck fault. Rather, the bridging fault and stuck fault are presented as general technological context for the type of data that is processed.)
occurred on a current stacking layer or a further stacking layer (This limitation is not indicative of integration into a practical application because it merely serves to generally link the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). The claims do not positively recite the layers of the semiconductor in a structural manner. Here, they are references to provide general technological context for the type of data that is processed.)
according to the defective points (This limitation is not indicative of integration into a practical application because it recites to the data that is used by the training model, and data, in itself, merely serves to add insignificant extra-solution activity (see MPEP 2106.05(g)). The “solution” is in the processing of the data and not the data itself.)
and some of the defective points cause a final product to malfunction, and some of the defective points do not cause the final product to malfunction (This limitation is not indicative of integration into a practical application because it merely serves to generally link the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). The claims do not positively recite the layers of the semiconductor in a structural manner. Here, context about the defective points on the layers merely serve as references to provide general technological context for the type of data that is processed.)
Claim 15
A model training device (This limitation is not indicative of integration into a practical application because it generally links the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h). No detail is given in terms of how the training device transforms or improves the semiconductor manufacturing process. There is just the general link.)
an establishment unit; a data acquisition unit; a machine learning unit (These limitations are not indicative of integration into a practical application because they generally link the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). No detail is given in terms of the structure of these various elements; They are generically recited followed by an intended use/function. Furthermore, these elements appear to simply be components of a computer system, and merely using a computer as a tool to perform an abstract idea is not indicative of integration into a practical application (see MPEP 2106.05(f)).)
obtain a plurality of defective points on a plurality of stacking layers (This limitation is directed to mere data gathering, recited at a high level of generality, which is considered insignificant extra-solution activity (see MPEP 2106.05(g)) The recitation of the stacking layers merely serve to link the judicial exception to a particular technological environment or field of use).
including a bridging fault and a stuck fault (This limitation is not indicative of integration into a practical application because it merely serves to generally link the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). The claims do not positively recite the structure of the circuit and the structural consequences to the circuit of a bridging fault and/or stuck fault. Rather, the bridging fault and stuck fault are presented as general technological context for the type of data that is processed.)
according to the defective points (This limitation is not indicative of integration into a practical application because it recites to the data that is used by the training model, and data, in itself, merely serves to add insignificant extra-solution activity (see MPEP 2106.05(g)). The “solution” is in the processing of the data and not the data itself.)
on a current stacking layer or a further stacking layer (This limitation is not indicative of integration into a practical application because it merely serves to generally link the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). The claims do not positively recite the layers of the semiconductor in a structural manner. Here, they are references to provide general technological context for the type of data that is processed.)
and some of the defective points cause a final product to malfunction, and some of the defective points do not cause the final product to malfunction (This limitation is not indicative of integration into a practical application because it merely serves to generally link the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). The claims do not positively recite the layers of the semiconductor in a structural manner. Here, context about the defective points on the layers merely serve as references to provide general technological context for the type of data that is processed.)
Dependent claims 3-4, 10-11, and 17-18 disclose the nature of the fault and where the fault occurs. They are directed to fault characteristics. These limitations are not indicative of integration into a practical application because they generally link the use of the judicial exception to a particular technological environment or field of use. The judicial exception is directed to abstract data processing, and these limitations merely serve to give generalized context to the nature of the data being processed. They do not recite an improvement or transformation of a particular article to a different state or thing.
With respect to step 2B, the claims do not recite additional elements that amount to significantly more than the judicial exception. The claimed invention does not add significantly more because, as discussed above in step 2A, prong two, the claims do nothing more than merely use a computer as a tool to perform an abstract idea; add insignificant extra-solution activity to the judicial exception; and/or generally link the use of the judicial exception to a particular technological environment or field of use. The claims are directed to receiving and processing data. This is well-understood, routine, and conventional. Simply appending well-understood, routine, and conventional activities previously known to the industry, and specified at a high level of generality, to the judicial exception is not indicative of an inventive concept (aka “significantly more”) (see MPEP 2106.05(d) and Berkheimer Memo).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-5, 8, 10-12, 15, and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al (CN101183399A) (Please note attached machine translation) in view of Ward (US PgPub 20130326441) and Blanton et al (US PgPub 20210042644).
With respect to claim 1, Ma et al discloses:
A yield rate prediction method of a semiconductor manufacturing process (paragraph 0054 states, “the most critical part is to establish a yield rate model.”; paragraph 0107 states, “yield predicted by the yield model”), comprising:
obtaining a plurality of defective points on a plurality of stacking layers (paragraphs 0019-0022 state, “The test circuit for measuring power failure and leakage defects in the test chip is preferably a collection of comb-shaped and P serpentine lines, the test circuit for measuring the failure rate of the contact hole is a collection composed of many contact holes and connecting lines … Because the defect curve needs to be fitted from the test results … there must be at least 3 data points to fit … The acquisition of the power failure and leakage defect curves of each layer …”);
recognizing, for each of the stacking layers, a probability of the fault of the circuit path of a semiconductor semi-final product according to the recognition model (paragraphs 0042, 0047, 0095, and 0140 discuss defect probability; layers discussed in paragraphs 0044 and 0049-0051)
wherein some of the defective points cause a final product to malfunction, and some of the defective points do not cause the final product to malfunction (paragraph 0011 states, “Not all measured defects are fatal defects. Even if the sensitivity is set correctly and all defects are measured, not all defects are fatal and will definitely cause the chip to fail.)
predicting a yield rate of the semiconductor semi-final product according to the probability (paragraph 0052 states, “Calculate the impact of defects in each process module on the yield rate …”; see also paragraph 0097, 0099, 0101, and 0149)
With respect to claim 1, Ma et al differs from the claimed invention in that it does not explicitly disclose:
establishing a correspondence relation between a circuit path of a netlist and an integrated circuit layout when the netlist does not include the correspondence relation, wherein the correspondence relation describes a correspondence between a position, a shape and an area of each hardware unit on each stacking layer and the circuit path
training a recognition model to recognize a fault including a bridging fault and a stuck fault occurred on the circuit path according to the defective points, wherein the recognition model is trained based on the correspondence relation between the circuit path of the netlist and the integrated circuit layout (Ma et al paragraph 0016 states, “The present invention uses test chips to accurately determine the defect rate curves of various process modules of the production line and the failure rate of contact holes, and combines the analysis of the effective area curves of power failure and leakage of each layer of the product layout and the number of contact holes, thereby establishing a yield model framework to analyze and improve the yield of semiconductor production lines.”; Ma et al paragraph 0051 states, “The power failure and leakage yield model is established by integrating the defect curves and effective area curves of power failure and leakage …” However, even though Ma et al does teach a recognition model to recognize failures and defects, it does not clearly teach “training” that model, such as via machine learning techniques. The word “training” is not explicitly disclosed in Ma et al, nor is there an explicit teaching of machine learning.)
recognizing … including the bridging fault and the stuck fault … occurred on a current stacking layer and a further stacking layer
With respect to claim 1, Ward discloses:
establishing a correspondence relation between a circuit path of a netlist and an integrated circuit layout when the netlist does not include the correspondence relation, wherein the correspondence relation describes a correspondence between a position, a shape and an area of each hardware unit on each stacking layer and the circuit path (paragraph 0005 states, “An IC chip is fabricated by first conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. This process is usually carried out using a ‘netlist,’ which is a record of all of the nets, or interconnections, between the cell pins, including information about the various components such as transistors, resistors and capacitors. A layout typically consists of a set of planar geometric shapes in several layers (emphasis mine). The layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements. The result is a set of design files known as an intermediate form that describes the layout …” Here, Ward draws a distinction between a netlist, a layout, and the design files that describe the layout. The design files described by Ward are broadly construed to read on the claimed correspondence relation, which is clearly separate from the netlist, such that the netlist does not include the correspondence relation.)
training a recognition model to recognize a fault occurred on the circuit path according to the defective points (paragraph 0027 states, “Both graph-based and physical features can be analyzed and extracted from the netlist, mapping a set of parameters most critical and sensitive to datapath logic. Effective features can be used to create differentiation between random and datapath logic, allowing the patterns extracted from a training set to classify datapath structures in new circuits.”; paragraph 0040-0041 states, “In the illustrative implementation, computer system 10 carries out datapath extraction by generating candidate clusters of the original netlist in which to search for datapath structures, and evaluating each cluster to identify specific characteristics used to distinguish datapath logic from random logic. Machine learning techniques can then be used to classify the clusters based on training models. The clustering stage prepares the netlist to analyze and extract datapath structures from. The goal is to find clusters exhibiting identifiable structural and physical features.” The claimed limitation is obvious in view of the combination between Ma et al in view of Ward. As discussed above, Ma et al does teach a recognition model to recognize failures and defects, it does not clearly teach “training” that model, such as via machine learning techniques. Ward teaches training models based on netlist and circuit layout data.), wherein the recognition model is trained based on the correspondence relation between the circuit path of the netlist and the integrated circuit layout (paragraphs 0009-0010, 0027, 0040-0041, 0043, 0046, and 0049)
With respect to claim 1, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Ward into the invention of Ma et al. The motivation for the skilled artisan in doing so is to gain the benefit of improved datapath extraction for enhanced model classification of circuits.
With respect to claim 1, Blanton et al discloses:
training a recognition model to recognize a fault including a bridging fault and a stuck fault (figure 9; paragraph 0046 states, “In one embodiment, possible candidate fault types considered in one embodiment of the invention are STUCK … BRIDGE …”)
recognizing … including the bridging fault and the stuck fault … occurred on a current stacking layer and a further stacking layer (obvious in view of combination; Ma teaches defect probability. Blanton teaches stuck faults and bridge faults as data for diagnosing and classifying defects. Furthermore, Blanton also teaches defect probability (paragraphs 0039, 0042, 0062, 0066). Also, one of ordinary skill in the art understands that the nature of bridging faults and stuck faults is that they have a direct effect on current and further stacking layers. One of ordinary skill in the art understands that faults in lower layers tend to propagate and exacerbate issues in higher layers. Recognizing these issues would be obvious to one of ordinary skill in the art applying the machine learning defect diagnosis principles of Blanton et al (that take both stuck and bridging faults into account) and applying those principles to the method of analyzing and improving yield rate of semiconductor production lines, as taught by Ma et al. As discussed above, Ma also teaches consideration of defects for each layer.).
With respect to claim 1, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Blanton et al into the invention of modified Ma et al. The motivation for the skilled artisan in doing so is to gain the benefit of more accurate defect diagnosis.
Independent claims 8 and 15 represent variations of claim 1 and are rejected for similar reasons. These claims incorporate “units” that are evaluated under 112(f). However, modified Ma et al discloses the necessary structure to perform the claimed functions, which are taught, as discussed in claim 1. Figure 2 of Ward discloses various computer components, such as a processing units, memory, etc … that one of ordinary skill in the art would recognize to be equipped to process and execute the claimed functions of Ma et al. As disclosed in paragraph 0016, Ma et al pertains to both a method and a system.
With respect to claims 3, 10, and 17, Ma et al, as modified, discloses:
wherein the bridging fault or the stuck fault occurs at one of the stacking layers (obvious in view of combination; The very disclosure of bridging and stuck faults suggests this limitation, as part of the nature of how bridging and stuck faults in an integrated circuit work.)
With respect to claims 4, 11, and 18, Ma et al, as modified, discloses:
wherein the bridging fault or the stuck fault occurs at two adjacent layers of the stacking layers (obvious in view of combination; The very disclosure of bridging and stuck faults suggests this limitation, as part of the nature of how bridging and stuck faults in an integrated circuit work.)
With respect to claims 5, 12, and 19, Ma et al, as modified, discloses:
wherein in the step of training the recognition model, the recognition model is trained to recognize the fault on the circuit path according to positions, shapes and areas of the defective points (obvious in view of combination; Ward teaches training model in the context of semiconductor chips and integrated circuits, and Ma et al teaches faults and failures of circuit; also paragraph 0070 of Ma et al states, “The defect must reach a certain size … and the defect must be located at a certain position to cause chip failure.”)
Claim(s) 6-7 and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al (CN101183399A) (Please note attached machine translation) in view of Ward (US PgPub 20130326441) and Blanton et al (US PgPub 20210042644), as applied to claims 1, 3-5, 8, 10-12, 15, and 17-19 above, and further in view of Motojima et al (JP2007294756A).
With respect to claims 6 and 13, Ma et al, as modified, discloses:
the yield rate prediction method (as applied to claim 1 above)
the yield rate prediction system (as applied to claim 8 above)
With respect to claims 6 and 13, Ma et al, as modified, differs from the claimed invention in that it does not explicitly disclose:
wherein the step of recognizing the probability of the fault occurred on the circuit path is performed before the semiconductor manufacturing process of the semiconductor semi-final product is completed
With respect to claims 6 and 13, Motojima et al discloses:
wherein the step of recognizing the probability of the fault occurred on the circuit path is performed before the semiconductor manufacturing process of the semiconductor semi-final product is completed (paragraph 0004 states, “Conventionally, when such manufacturing variations occur, a feedback-based manufacturing system has been used in which a completed product is inspected, and based on the inspection results, the manufacturing conditions for products to be manufactured after the product in question are changed … in recent years, feedforward manufacturing systems have come into use, in which deviations of a product’s characteristics from its design values are detected during the manufacturing process of the product, and based on the results, the manufacturing conditions of the product itself are changed …”; The claimed limitation is obvious in view of combining the feedforward teachings of Motojima et al into the invention of modified Ma et al. One of ordinary skill in the art recognizes that in a feedforward system, it would be obvious to perform certain functions before there is a completed product. Modified Ma et al teaches these types of functions.)
With respect to claims 6 and 13, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Motojima et al into the invention of modified Ma et al. The motivation for the skilled artisan in doing so is to gain the benefit of reducing costs by obviating the need for a completed product before adjustments and improvements can occur.
With respect to claims 7 and 14, Ma et al, as modified, discloses:
the yield rate prediction method (as applied to claim 1 above)
the yield rate prediction system (as applied to claim 8 above)
With respect to claims 7 and 14, Ma et al, as modified, differs from the claimed invention in that it does not explicitly disclose:
wherein the step of predicting the yield rate of the semiconductor semi-final product is performed before the semiconductor manufacturing process of the semiconductor semi-final product is completed
With respect to claims 7 and 14, Motojima et al discloses:
wherein the step of predicting the yield rate of the semiconductor semi-final product is performed before the semiconductor manufacturing process of the semiconductor semi-final product is completed (paragraph 0004 states, “Conventionally, when such manufacturing variations occur, a feedback-based manufacturing system has been used in which a completed product is inspected, and based on the inspection results, the manufacturing conditions for products to be manufactured after the product in question are changed … in recent years, feedforward manufacturing systems have come into use, in which deviations of a product’s characteristics from its design values are detected during the manufacturing process of the product, and based on the results, the manufacturing conditions of the product itself are changed …”; The claimed limitation is obvious in view of combining the feedforward teachings of Motojima et al into the invention of modified Ma et al. One of ordinary skill in the art recognizes that in a feedforward system, it would be obvious to perform certain functions before there is a completed product. Modified Ma et al teaches these types of functions.)
With respect to claims 7 and 14, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Motojima et al into the invention of modified Ma et al. The motivation for the skilled artisan in doing so is to gain the benefit of reducing costs by obviating the need for a completed product before adjustments and improvements can occur.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ge et al (CN111026058A) discloses a semi-supervised deep learning fault diagnosis method based on Wasserstein distance and auto-encoder. Machine Translation also included.
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/LEONARD S LIANG/Examiner, Art Unit 2857 03/19/26