Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Non-Final office action based on application 17/084,940 in response to reply filed September 30, 2025. Claims 1-6, 8-9, 13-14, 16, 18, 21-27 are currently pending and have been considered below.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 17, 2025 has been entered.
Election/Restrictions
Claims 3-4, 13-14, 16, 18, 22 & 24 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species III (Fig. 11-12) there being no allowable generic or linking claim. Election was made without traverse in the reply filed on February 28, 2024.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5-6, 8-9, 21, 23, 25-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Samachisa (Pre-Grant Publication 2022/0173251) in view of Sharangpani (US Patent 11,024,648).
Regarding claim 1 & 27, Samachisa discloses a memory device comprising:
ferroelectric memory cells arranged into a three-dimensional (3D) structure (Fig. 13b, Paragraph [0079]), each ferroelectric memory cell comprising a ferroelectric layer (271) adapted to provide non-volatile storage of data, wherein the memory is arranged as a plurality of vertically extending conductive layers physically formed as word lines (272) and a plurality of stacks of layers (254-1, 254-2, 254-3, 254-4) between adjacent pairs of the vertically extending layers, wherein each stack comprises multiple sets of repeating layers comprising a drain layer (204d), bit line layer (204e), a source layer (204b) and a channel (270)/isolation layer (204c) wherein the drain layer is configured distinct from the bit line layer.
Samachisa does not explicitly disclose the ferroelectric memory comprises a film of ferroelectric orthorhombic material. However Sharangpani discloses a ferroelectric memory device comprising:
A ferroelectric material wherein the ferroelectric material can be Hf1-xZrxO2 wherein Zr can be 0.3≤x≤0.7 therefore the ferroelectric material can be Hf0.5Zr0.5O2 and the ferroelectric material can be an orthorhombic phase material (Col. 14, Lines 37-67 & Col. 15, Lines 1-3).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the ferroelectric material as orthorhombic Hf0.5Zr0.5O2 because it will serve to form a ferroelectric film exhibiting desired ferroelectric properties such as high electrical polarization and coercive field.
Regarding claim 2, Samachisa further discloses:
each ferroelectric memory cell is arranged as a ferroelectric field effect transistor (FeFET) comprising a source region (204b), a drain region (204d), and a control gate region (272), the control gate region comprising the ferroelectric layer (271).
Regarding claim 5 & 6, Samachisa disclose all of the limitations of claim 1 (addressed above). Although Samachisa does not explicitly disclose the ferroelectric layer is configured to store less than a full bit of data, it should be known where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d (MPEP 2112.01 I). Therefore since Samachisa disclose the same structure/material of the ferroelectric layer such as HfOx or HfZrO (Paragraph [0083]), the ferroelectric layer of Ramaswamy will be capable of storing multiple bits of data or less than a full bit of data.
Regarding claim 8, Samachisa further discloses:
the memory is characterized as a 3D horizontal NOR (HNOR) ferroelectric field effect transistor (FeFET) memory, the memory further comprising a plurality of FeFETs at each connecting interface between an associated word line and an associated stack (Paragraph [0079]).
Regarding claim 9, Samachisa further discloses:
each stack comprises multiple sets of repeating layers comprising a drain layer (204d), a bit line layer (204e), a source layer (204b) and a channel/isolation layer (270/204c) (Fig. 13b).
Regarding claim 21, Samachisa discloses a memory device comprising:
ferroelectric memory cells arranged into a three-dimensional (3D) structure (Fig. 13b, Paragraph [0079]), each ferroelectric memory cell comprising a ferroelectric layer (271) adapted to provide non-volatile storage of data, wherein the memory is arranged as a FeFET comprising a source region (204b), a drain region (204d) and a control gate region (272), a plurality of vertically extending conductive layers physically formed as word lines (272) and a plurality of stacks of layers (254-1, 254-2, 254-3, 254-4) between adjacent pairs of the vertically extending layers, wherein each stack comprises multiple sets of repeating layers comprising a drain layer (204d), bit line layer (204e), a source layer (204b) and a channel (270)/isolation layer (204c) wherein the drain layer is configured distinct from the bit line layer.
Samachisa does not explicitly disclose the ferroelectric memory comprises a film of ferroelectric orthorhombic material. However Sharangpani discloses a ferroelectric memory device comprising:
A ferroelectric material wherein the ferroelectric material can be Hf1-xZrxO2 wherein Zr can be 0.3≤x≤0.7 therefore the ferroelectric material can be Hf0.5Zr0.5O2 and the ferroelectric material can be an orthorhombic phase material (Col. 14, Lines 37-67 & Col. 15, Lines 1-3).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the ferroelectric material as orthorhombic Hf0.5Zr0.5O2 because it will serve to form a ferroelectric film exhibiting desired ferroelectric properties such as high electrical polarization and coercive field.
Regarding claim 23, Samachisa further discloses:
the ferroelectric layer comprises at least a selected one of HfO2, ZrO2, or Hfl-xZxO2 (Paragraph [0083]).
Regarding claim 25, Samachisa further discloses:
the memory is characterized as a 3D horizontal NOR (HNOR) ferroelectric field effect transistor (FeFET) memory, the memory further comprising a plurality of FeFETs at each connecting interface between an associated word line and an associated stack (Paragraph [0079]).
Regarding claim 26, Samachisa further discloses:
each stack comprises multiple sets of repeating layers comprising a drain layer (204d), a bit line layer (204e), a source layer (204b) and a channel/isolation layer (270/204c) (Fig. 13b).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 & 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM.
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/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818