DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 02/26/2026 has been entered. Claims 1-20 remain pending in the application.
Response to Arguments
Applicant’s arguments, filed 02/26/2026, with respect to the rejections of claim 1 under 103 have been fully considered and are not persuasive.
Applicant’s arguments, filed 02/26/2026, with respect to the rejections of claims 5 and 14 under 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn.
Applicant argues (pages 6-8)
Amended independent claim 1 overcomes this rejection by reciting at least the following: …
Amended independent claim 1 recites a self-rectifying memory cell for a memory array that includes (1) a crested barrier selector device connected in series with (2) a separate memory element. For example, the Applicant's FIG. 2 illustrates how the selector device may be arranged between a first connection in the memory array and the memory element. The memory element may then be arranged between the selector and a second connection to the memory array. This structural arrangement ensures that the selector device physically and electrically isolates the memory element from the array connection and from neighboring memory elements during non-read/write operations. See Specification, ¶ [0051], FIG. 2.
The Office cannot reject the structure limitations of the selector in amended claim 1 using materials found in memory elements of the cited references …
In summary, the cited references exclusively show the use of the claimed HfOx, TiOx, and SiOx materials as memory elements relying on filamentary conduction. The cited references fail to suggest a structural combination where these specific materials are utilized as in a crested barrier selector that is coupled to a separate and distinct memory element. Therefore, it is respectfully requested that the rejection of claim 1 be withdrawn.
In Response
The Applicant amended the claim by reciting “a memory element connected in series with selector device, the selector device isolating the memory element from a connection in the memory array”, and argued that the cited references do not teach the new limitation which is the structure arrangement of the selector and memory element such that the memory element is isolated from a connection in the memory array.
This argued limitation is a newly amended limitation, and a newly found reference Parkinson et al. (US Patent 11,222,678) teaches this limitation. (Please see the 103 rejections section below for detail)
Parkinson in Fig. 11, abstract, Col. 18 teaches memory element, such as an MRAM device, is connected in series with a selector to reduce current leakage. Fig. 11 below shows a selector is placed in series with a memory element (MRAM) to isolate the memory element from connecting to the bit line/word line; Since the claim does not define what is “a connection in the memory array”, and according to the reciting in paragraph 0051 of the specification of the current Application “To minimize the leakage current through the circuit network 200, and to isolate memory elements connected on the same word/bit lines, the synapse 202c may each include the selector device”, the examiner interprets the limitation “a connection in the memory array” as a connection to the word/bit lines.
PNG
media_image1.png
664
756
media_image1.png
Greyscale
Examiner’s Note
Examiner have called the Applicant’ Representative (Attorney James Bergstrom) on Wednesday 5/20 to offer an examiner’s amendment to move up allowable limitations of claim 5 into claim 1 so that the case can be allowed, but, the Applicant’ Representative did not want to take the offer and asked for the rejection to be sent.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US Pub. 2017/0110515) in view of Hashim et al. (US Pub. 2014/0192585) in view of Lam et al. (US Pub. 2016/0141494) and further in view of Parkinson et al. (US Patent 11,222,678).
As per claim 1, Yang teaches a memory cell for a memory array [Figs. 1-2, paragraphs 0013-0016, discloses an example I-Selector n-Resistor memristive device 100 comprising memristors 130, each maybe a single memory cell in a crossbar array”], the memory cell comprising:
crested barrier selector device [Figs. 1-2, paragraphs 0013-0014, “a selector may be used with memristors in a crossbar array”], the selector device comprising:
a first electrode [Fig. 2, paragraph 0027, electrode 210];
a first tunneling layer comprising cobalt oxide [paragraph 0026, “FIG. 2 depicts an example 1-Selector n-Resistor memristive device 200 having a crested tunnel barrier selector 220 with a three-layer structure … selector 220 may include at least three semiconducting or insulating layers 222 that form a tunneling barrier … more than three tunneling layers may be used to create crested tunnel barrier selector 220”; paragraphs 0028-0029, “Selector 220 may also be oxide-based, meaning that at least a portion of selector 220 is formed from an oxide-containing material … compound forming metals X, Y, and Z may be Co (cobalt)”];
two or more interface switching modulation (ISM) layers [Figs. 1-2, paragraphs 0009-0010, “Memristors are devices that may be used as components in a wide range of electronic circuits, such as switches … Some memristors exhibit bipolar switching, where applying a voltage of one polarity may switch the state of the memristor and where applying a voltage of the opposite polarity may switch back to the original state”; paragraph 0014, “a plurality of memristors 130 coupled to selector”], wherein the first tunneling layer is between the first electrode and the two or more ISM layers [Fig. 2 shows the tunneling layers 220 is located between the first electrode 210 and ISM layers (memristors 230)], and wherein each of the two or more ISM layers comprises:
a layer of hafnium oxide [paragraph 0017, “Memristor 130 may be based on a variety of materials … memristor 130 may be formed based on hafnium oxide … materials of memristor 130 may include silicon dioxide … materials of memristor 130 may include titanium oxide”];
a second electrode [Fig. 2, paragraph 0027, electrode 240], wherein the two or more ISM layers are between the first tunneling layer and the second electrode [Fig. 2 shows the ISM layers (memristors 230) is located between the first tunneling layer 220 and the second electrode 240].
Yang teaches the switching layers (memristors 230) may include either hafnium oxide, silicon oxide or titanium oxide.
Yang does not explicitly teach
each of the two or more ISM layers comprises:
a layer of hafnium oxide;
a layer of silicon oxide; and
a monolayer of titanium oxide between the layer of hafnium oxide and the layer of silicon oxide;
the first tunneling layer directly contacts a layer of hafnium oxide in the two or more ISM layers; and
a memory element connected in series with selector device, the selector device isolating the memory element from a connection in the memory array.
Hashim teaches
each of the two or more ISM layers comprises:
a layer of hafnium oxide;
a layer of silicon oxide; and
a monolayer of titanium oxide between the layer of hafnium oxide and the layer of silicon oxide;
[Fig. 3 shows a schematic representation of ReRAM cell 300 which includes first electrode layer 302, resistive switching layer 304, and second electrode layer 306; paragraph 0071, “resistive switching layer 304 includes multiple sub-layers. For example, resistive switching layer 304 includes a titanium oxide sub-layer, a hafnium oxide sub-layer, and a silicon oxide sub-layer … In some embodiments, the titanium oxide sub-layer may be disposed in between the hafnium oxide sub-layer and the silicon oxide sub-layer … the thickness of titanium oxide sub-layer may be between about 5 Angstroms and 15 Angstroms, such as about 8 Angstroms”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the crested tunnel barrier device of Yang to include the switch layer comprises: a layer of hafnium oxide, a layer of silicon oxide, and a monolayer of titanium oxide between the layer of hafnium oxide and the layer of silicon oxide of Hashim. Doing so would help exhibiting multi
state resistive state, providing multistate switching of the ReRAM cell, and facilitating read accuracy (Hashim, 0070 and 0100).
Yang and Hashim do not teach
the first tunneling layer directly contacts a layer of hafnium oxide in the two or more ISM layers; and
a memory element connected in series with selector device, the selector device isolating the memory element from a connection in the memory array.
Lam teaches
the first tunneling layer directly contacts a layer of hafnium oxide in the two or more ISM layers [paragraph 0030, “FIGS. lA-1B depict the basic structure of such a resistive memory device 100, including bottom electrode 102, switching layer 104 …”; paragraph 0043, “The material of the switching layer 104 may be a metal oxide … such as … hafnium oxide”; Fig. 3B–3E, paragraph 0033, disclose a select layer (layer 308) such as a tunnel barrier between the switching layer 104 and the top electrode 108; Since the tunnel barrier layer 308 is adjacent to the switching layer 104, and the material of the switching layer 104 is hafnium oxide, therefore, the tunnel barrier layer 308 directly contacts a layer of hafnium oxide of the switching layer 104].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the crested tunnel barrier device of Yang to include the first tunneling layer directly contacts a layer of hafnium oxide in the two or more ISM layers of Lam. Doing so would help increasing non-linear characteristics of the device (Lam, 0033).
Yang, Hashim and Lam do not explicitly teach
a memory element connected in series with selector device, the selector device isolating the memory element from a connection in the memory array.
Parkinson teaches
a memory element connected in series with selector device [abstract, “In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM device, is connected in series with a threshold switching selector”], the selector device isolating the memory element from a connection in the memory array [Col. 18, lines 51-67, “One approach to address this unwanted current leakage is to place a selector element in series with each MRAM or other resistive (e.g., ReRAM, PCM) memory cell … An alternate approach to selector elements is the use of a threshold switching selector element in series with the programmable resistive element to comprise an individual memory cell or bit …”; Fig. 11 shows a selector is placed in series with a memory element (MRAM) to isolate the memory element from connecting to the bit line/word line; Since the claim does not define “a connection in the memory array”, and according to the reciting in paragraph 0051 of the specification of the current Application “To minimize the leakage current through the circuit network 200, and to isolate memory elements connected on the same word/bit lines, the synapse 202c may each include the selector device”, the examiner interprets the limitation “a connection in the memory array” as a connection to the word/bit lines].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the crested tunnel barrier device of Yang to include a memory element connected in series with selector device, the selector device isolating the memory element from a connection in the memory array of Parkinson. Doing so would help reducing current leakage through the circuit (Parkinson, Col. 18, lines 51-67).
As per claim 2, Yang, Hashim, Lam and Parkinson teach the memory cell of claim 1.
Yang further teaches
wherein the first tunneling layer is approximately 10 nm thick [paragraph 0026, “FIG. 2 depicts an example 1-Selector n-Resistor memristive device 200 having a crested tunnel barrier selector 220 with a three-layer structure … selector 220 may include at least three semiconducting or insulating layers 222 that form a tunneling barrier … the thickness of each layer being 0.5-5 nm”; Since the thickness of each layer is 0.5-5nm, then the thickness of all three layers can be approximately 10nm].
As per claim 3, Yang, Hashim, Lam and Parkinson teach the memory of claim 1.
Hashim further teaches
layers in the two or more ISM layers are approximately 1 nm thick [paragraph 0071, “resistive switching layer 304 includes multiple sub-layers. For example, resistive switching layer 304 includes a titanium oxide sub-layer, a hafnium oxide sub-layer, and a silicon oxide sub-layer … In some embodiments, the titanium oxide sub-layer may be disposed in between the hafnium oxide sub-layer and the silicon oxide sub-layer”; paragraph 0071, “the thickness of titanium oxide sub-layer may be between about 5 Angstroms and 15 Angstroms, such as about 8 Angstroms. The thickness of hafnium oxide sub-layer may be between about 25 Angstroms and 100 Angstroms, such as about 50 Angstroms. The thickness of silicon oxide sub-layer may be between about 10 Angstroms and 50 Angstroms, such as about 20 Angstroms”; It can be seen that the thickness of all three sub-layers is about 8 Angstroms + 50 Angstroms + 20 Angstroms = 78 Angstroms = .78nm which is approximately 1 nm thick].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the crested tunnel barrier device of Yang to include layers in the one or more ISM layers are approximately 1 nm thick of Hashim. Doing so would help determining some of the radiation parameters used for creating defects in these layers (Hashim, 0074).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. in view of Hashim et al. in view of Lam et al. in view of Parkinson et al. and further in view of Kim et al. (US Pub. 2014/0042380).
As per claim 4, Yang, Hashim, Lam and Parkinson teach the memory of claim 1.
Yang further teaches
each of the two or more ISM layers comprises material [paragraph 0017, “Memristor 130 may be based on a variety of materials … memristor 130 may be formed based on hafnium oxide … materials of memristor 130 may include silicon dioxide … materials of memristor 130 may include titanium oxide … or other like oxides”; paragraph 0010, “The resistance of a memristor may be changed by applying an electrical stimulus, such as a voltage or a current, through the memristor. Generally, at least one channel may be formed that is capable of being switched between two states one in which the channel forms an electrically conductive path ("ON") and one in which the channel forms a less conductive path ("OFF"). In some other cases, conductive paths represent "OFF" and less conductive paths represent "ON". Conducting channels may be formed by ions and/or vacancies. Some memristors exhibit bipolar switching, where applying a voltage of one polarity may switch the state of the memristor and where applying a voltage of the opposite polarity may switch back to the original state”];
Yang, Hashim, Lam and Parkinson do not explicitly teach
each of the two or more ISM layers comprises material dipoles with polarities that are controlled by a voltage applied across the first electrode and the second electrode.
Kim teaches
each of the two or more ISM layers comprises material dipoles with polarities that are controlled by a voltage applied across the first electrode and the second electrode [Figs. 9-10, paragraphs 0082-0083, “The first material layer 51 of the resistance switching material layer 50 may be formed of a metal oxide … The second material layer 55 may exchange oxygen ions and/or oxygen vacancies with the first material layer 51 and may be a layer inducing resistance switching of the resistance switching material layer 50 … Similarly to the first material layer 51, the second material layer 55 may include oxygen ions and/or oxygen vacancies”; paragraphs 0092-0093, “ resistance switching material elements 100, 200, 30, 400, 500, and 600, during a set operation in which a positive (+) voltage is applied to the first electrode 10 and a negative (-) voltage is applied to the second electrode 70, oxygen vacancies are transferred from the first material layer 51 to the second material layer 55 and thus a current path (not shown) may be formed in the second material layer 55. Accordingly, the resistance of the resistance switching material layer 50 may lower. In other words, the resistance switching material layer 50 may be changed from the OFF state to the ON state. In the set operation, oxygen ions may be transferred in the opposite direction to that of the oxygen vacancies, that is, from the second material layer 55 to the first material layer 51 … during a reset operation in which a negative (-) voltage is applied to the first electrode 10 and a positive (+) voltage is applied to the second electrode 70, oxygen vacancies are transferred from the second material layer 55 to the first material layer 51, that is, oxygen ions are transferred from the first material layer 51 to the second material layer 55 … the resistance switching material layer 50 may be changed from the ON state to the OFF state”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the crested tunnel barrier device of Yang to include each of the two or more ISM layers comprises material dipoles with polarities that are controlled by a voltage applied across the first electrode and the second electrode of Kim. Doing so would help changing the states of the switching element from ON to OFF or vice versa when applying positive or negative voltages to the first electrode and the second electrode (Kim, paragraphs 0092-0093).
Allowable Subject Matter
Claims 5-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 5 is allowable for disclosing
A crested barrier device with interface switching modulation layers, the device comprising:
a first electrode;
a first tunneling layer comprising a first dielectric constant;
two or more interface switching modulation (ISM) layers, wherein the first tunneling layer is between the first electrode and the two or more ISM layers, and wherein each of the two or more ISM layers comprises:
a layer of hafnium oxide;
a layer of silicon oxide comprising a second dielectric constant, wherein the second dielectric constant is at least 1.5 times larger than the first dielectric constant; and
a monolayer of titanium oxide between the layer of hafnium oxide and the layer of silicon oxide;
a second tunneling layer comprising a third dielectric constant, wherein:
the two or more ISM layers are between the first tunneling layer and the second tunneling layer; and
the second dielectric constant is at least 1.5 times larger than the third dielectric constant; and
a second electrode, wherein the second tunneling layer is between the two or more ISM layers and the second electrode, the first tunneling laver directly contacts a laver of hafnium oxide in the two or more ISM layers, and the second tunneling laver directly contacts a laver of silicon oxide in the two or more ISM layers.
The closest references found
Govoreanu (US Pub. 2014/0367631) in Fig. 1, paragraphs 0066 and 0070 discloses [a memory device comprising a first electrode and a second electrode, a multi-layer tunnel stack 14 comprises three dielectric layers, wherein, the multi-layer tunnel stack 14 is provided the resistance-switching element 13 and the bottom electrode, or alternatively between the resistances witching element 13 and the top electrode].
Buckley et al. (NPL: Investigation of SiO2/HfO2 gate stacks for application to non-volatile memory devices) in Fig. 2, abstract and introduction describes [the use of SiO2/HfO2 stacks as tunnel barriers for non-volatile memories].
However, the prior art of record do not teach or suggest, individually or in combination limitations (among others)
the first tunneling layer is between the first electrode and the two or more ISM layers,
the second tunneling layer is between the two or more ISM layers and the second electrode, the first tunneling laver directly contacts a laver of hafnium oxide in the two or more ISM layers, and the second tunneling laver directly contacts a laver of silicon oxide in the two or more ISM layers.
Therefore, the combination of features is considered to be allowable.
Claims 6-13 are considered to be allowable because they are dependent on claim 5.
Claim 14 is considered to be allowable for disclosing the similar subject matter to claim 5.
Claims 15-20 are considered to be allowable because they are dependent on claim 14.
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Brewer et al. (US Pub. 2011/0291067) describes a threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRI T NGUYEN whose telephone number is 571-272-0103. The examiner can normally be reached M-F, 8 AM-5 PM, (CT).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, OMAR FERNANDEZ can be reached at 571-272-2589. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TRI T NGUYEN/Examiner, Art Unit 2128
/OMAR F FERNANDEZ RIVAS/Supervisory Patent Examiner, Art Unit 2128
Prosecution Insights