DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/13/2026 has been entered.
Status of Claims
This is a Non-Final Action for Request for Continued Examination (RCE). Claim(s) 1-6, and 8-21 have been examined and fully considered. Claim(s) 1, 15, and 20 have been amended. Claim(s) 1-6, and 8-21 are pending in Instant Application.
Response to Arguments
Applicant’s arguments, see Remarks, filed 03/13/2026, with respect to the rejection(s) of claim(s) 35 USC § 103 under 1-6, 8-19, and 20-21 have been fully considered and persuasive argument.
a. Tajimi, Anderson, and Murrin do not teach or suggest "at one timepoint, a portion
of the first data elements and a portion of the second data elements are located in
adjacent memory locations of the memory array." as recited in claim 1; and
b. Murrin does not make up for the admitted deficiencies in Tajimi and Anderson in
disclosing "write the second data elements to the memory array using the second
sequence of addresses" as recited in amended claim 1.
As Anderson addresses the difference of first and second sequence of addresses reordering/rearranging processing element of the first and second sequence to be read and/or written and store in the memory array, in which is different from one another, therefore, meeting the scope of the subject matter.
However, a new ground(s) of rejection is made in view of Lee (US 5444545 A).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 1, 15, and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim(s) 1, 15 and 20 are rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, because the claim purports to invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, but fails to recite a combination of elements as required by that statutory provision and thus cannot rely on the specification to provide the structure, material or acts to support the claimed function. As such, the claim recites a function that has no limits and covers every conceivable means for achieving the stated function, while the specification discloses at most only those means known to the inventor. Accordingly, the disclosure is not commensurate with the scope of the claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1, 15, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim(s) 1, 15, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
For the claim feature "at one timepoint, a portion of the first data elements and a portion of the second data elements are located in adjacent memory locations of the memory array.", where there is no clear structure in the specification referring this specifically. After review of the specification, there is no clear distinction in the specification detailing what is "at one timepoint, a portion of the first data elements and a portion of the second data elements are located in adjacent memory locations..." are referred to as, therefore making the claim indefinite.
All dependent claims are also rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, due to their dependency of the rejected claim(s) 1, 15, and 20.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 8-13, 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tajimi (US 2020/0036927; previously recorded) in view of Anderson et al. (US 2017/0068616; previously recorded), hereinafter, referred to as “Anderson”, and in view of Lee (US 5444545 A)..
Regarding claim 1, Tajimij discloses an apparatus (see at least Paragraph [0026]: “an imaging apparatus 100”) for rearranging image data of a stream (see at least Abstract) comprising: a memory array (see at least Paragraph [0035]: “The auxiliary memory unit 130 assumes an auxiliary role for the main memory unit 140” );
control circuitry (see at least “A central processing unit 128”) coupled to the memory array (see at least Paragraph [0036]: “the auxiliary memory unit 130 serves as a memory for storing a computer program necessarily used by the information processing unit 120 for controlling the image sensor 110”), the control circuitry (see at least Paragraph [0040]: “A central processing unit 128 serves as a computer for performing an operation necessary for controlling the image sensor 110, for instructing peripheral circuits or other apparatuses to operate, and for sending a variety of control signals to other circuits”) configured to:
receive the image data of the stream, the image data including a first image comprising first data elements organized in a row-wise format or a column-wise format (see at least Paragraph [0040]: “the central processing unit 128 controls rearranging image signals with the first rearrangement circuit when simultaneously reading out plural rows of image signals from the pixel unit. Then, the central processing unit 128 controls other rearranging with the second rearrangement circuit so that an order of the two-dimensional arrangement of the pixels in the pixel unit is restored. For that purpose, the drive control signal 101 includes a signal for instructing the number of rows of image signals to be simultaneously read out and control signals for controlling the operation of the first memory and the first rearrangement circuit.”) and a second image comprising second data elements organized in a row-wise format or a column-wise format (see at least Paragraph [0046]: “according to an instruction from the central processing unit 128, the second rearrangement circuit 121 is used to rearrange image information to restore an order corresponding to the physical pixel arrangement.”);
…
Tajimij does not disclose
write the first data elements to the memory array in a first order using a first sequence of addresses;
read the first data elements from the memory array in a second order using a second sequence of addresses, wherein the second sequence of addresses is different than the first sequence of addresses; and
write the second data elements to the memory array using the second sequence of addresses.
However, Anderson teaches
write the first data elements to the memory array in a first order using a first sequence of addresses (see at least Paragraph [0037]: “By generating sequences of read and/or write addresses, the address generator can perform non-linear reordering of data items stored on a memory connected to one of the ports of the DMA controller 106. For example, FIG. 2 illustrates how a first sequence 212 of data items stored on the on-chip memory 102 can be reordered during a transfer to the paged memory device 112.”);
read the first data elements from the memory array in a second order using a second sequence of addresses, wherein the second sequence of addresses is different than the first sequence of addresses see at least Paragraph [0037]: “In the example of FIG. 2, there are eight data items on the on-chip memory 102, which are stored at memory addresses denoted 0 to 7. In other examples, the memory addresses can start from a base address other than zero, and/or each individual data item can be larger than a single memory location on the memory device. In this example, these data items are transferred to the paged memory device, but are ordered in a second sequence 214 that is different to the first sequence 212. For clarity, the data items in the second sequence 214 are stored at memory addresses denoted 0 to 7 on the paged memory device 112, although in other examples these addresses can start from a base address other than zero” and [0038]: “In a first example, the address generator 210 can generate a linear read sequence of 0, 1, 2, 3, 4, 5, 6, 7 and provide this read sequence to the internal port 202. The address generator 210 can also generate a non-linear write sequence of 3, 6, 4, 1, 2, 7, 0, 5 and provide this to the external port 204. This causes the internal port 202 to firstly read the data item from the first address in the read sequence (address 0), which is data item “A” in this example.”… “This operation repeats with each subsequent data item addressed in the read sequence, each of which is written to the corresponding address in the write sequence. As a result of this, the data items from the first sequence (denoted A, B, C, D, E, F, G) are now stored on the paged memory in the second sequence (G, D, E, A, C, H, B, F).” ); and…
*** Examiner notes Anderson was brought in as pertinent art to teach the processing element of the first and second sequence to be read and/or written and store in the memory array, in which is different from one another. By combining the data processing function with the rearranging image data of a stream of Tajimi, it could understood that the use of the prior art references would satisfy the subject matter in the case of graphics processing to rearrange or reorder the image data.***
Accordingly, it would have been obvious to one of ordinary skill in the art before the filing of the invention to further incorporate the memory address generation for digital signal processing of Anderson, and combining an apparatus for rearranging image data as taught by Tajimij. One would be motivated to make this modification in order processing system is to be flexible enough to be used with different standards, then the dedicated memory device used for interleaving/deinterleaving must be sufficiently large to handle the standard with the largest memory demands (see at least Paragraph [0004]).
Neither Tajimij nor Anderson does not clearly recite
…write the second data elements to the memory array using the second sequence of addresses, wherein, at one timepoint, a portion of the first data elements and a portion of the second data elements are located in adjacent memory locations of the memory array.
However, Lee teaches
…write the second data elements to the memory array using the second sequence of addresses, wherein, at one timepoint, a portion of the first data elements and a portion of the second data elements are located in adjacent memory locations of the memory array (see columns 3, “The above memory means comprises a first memory for storing the picture data supplied from the inner decoder in a region which is assigned by the write ad dress supplied from the first selector, or generating the picture data stored in a region which is assigned by the read address, in response to one read/write enable signal supplied from the second selector, and a second memory for storing the picture data supplied from the inner decoder in a region which is assigned by the write address supplied from the first selector or generating the picture data stored in a region which is assigned by the read address, in response to the other read/write enable signal supplied from the second selector.”; and 5-6, “On the other hand, data processor 110 comprises: first and second memories 615 and 616 which are memory means for storing the data supplied from inner decoder 100 (FIG. 1); a write address generator 601 which generates an address for assigning memory access location for writing the data into first and second memories 615 and 616; a read address generator 602 which generates an address for assigning a memory access location for reading the stored data; a first multiplexer 612 for selecting one among the address signals supplied from write address generator 601 and read address generator 602, according to the field selection signal, and supplying the selected address signal to first memory 615; a second multiplexer 613 for performing the same function as that of first multiplexer 612, and supplying the selected address signal to second memory 616 according to the inverted field selection signal; a first AND gate 603 for logically multiplying the field selection signal by the output of frequency divider 220; a second AND gate 604 for logically multiplying the field selection signal by the output of comparator 210; first and second inverters 605 and 606 for inverting the outputs of first and second AND gates 603 and 604; …, according to a control signal D corresponding to the mode selection of mode selector 200, and supplying the selected signal to first memory 615 as a read/write enable signal; a third inverter 614 for inverting the field selection signal; a fourth multiplexer 610 for selecting one among the inverted field selection signal (the output of third inverter 614) and the outputs of third and fourth AND gates 607 and 608, according to a control signal D corresponding to the mode selection of mode selector 200, and supplying the selected signal to second memory 616 as another read/write enable signal; and a fifth multiplexer 617 for selecting one among the output data signals of first and second memories 615 and 616, according to the field selection signal, and supplying the selected signal to outer decoder 120 (FIG. 1).” *** Examiner notes that Lee teaches writing allocation of data into first and second, such as, “writing the data into first and second memories 615 and 616” ***).
Accordingly, it would have been obvious to one of ordinary skill in the art before the filing of the invention to imply writing the second data elements to the memory array as taught by Murrin, and by combining Tajimij in view of Anderson with a reasonable expectation of success.
As to [claim 2], the combination of Tajimij, Anderson and Lee teaches the apparatus of claim 1. Tajimij discloses wherein the first order comprises a row-major order, and wherein the second order comprises a column-major order (see at least Paragraph [0045]: “A second rearrangement circuit 121 is for rearranging rows or columns of data. As explained below, there is a case in which image information read out from the image sensor 110 cannot be read out in the order of physical pixel arrangement when more than a predetermined number of rows are simultaneously read out and when there is a structural limitation on a read-out circuit. Therefore, in order to form a proper image viewable by users based on image information read out from the image sensor”; (see at least Paragraph [0109]: “Next, in the second H period, the 2, 4, 6, 8, 10 and 12th row signals of the pixel unit 113 together with the 13, 15, 17, 19, 21 and 23rd row signals are read out through the AID conversion unit 114. At this time, the first row signal stored in the first memory unit 112 is read out first, then the second row signal is read out from the pixel unit 113 via the AID conversion unit 114”).
As to claim 3, the combination of Tajimij, Anderson and Lee teaches the apparatus of claim 1. Tajimij discloses further wherein the first data elements are received in row-major order, and wherein the second data elements are received in the row-major order (see at least Paragraph [0138]: “FIG. 10, after the first memory unit 112 and the first rearrangement circuit 111 perform the rearrangement process for restoring pixel arrangement in a column direction, all the pixel signals in row direction are transferred to the information processing unit 120. Next, the second memory unit 122 and the second rearrangement circuit 121 perform the rearrangement process for restoring original row orders”).
As claim 4, the combination of Tajimij, Anderson and Lee teaches the apparatus of claim 1. Tajimij discloses further wherein the second data elements are written to a series of memory locations in a row-major order, where at least two memory locations of the series of memory locations are non-successive memory locations (see at least Paragraph [0147]: “it is preferable that all pixel data in a row direction has been already rearranged for restoring. In other words, if odd pixel signals and even pixel signals are already rearranged to restore the original order by the first rearrangement circuit 111 and the first memory unit 112, the restored signals can be used for performing such operations disclosed above while the second rearrangement circuit 121 is rearranging pixel signals to restore the original row order”).
As to claim 5, the combination of Tajimij, Anderson and Lee teaches the apparatus of claim 1. Tajimij discloses further wherein the control circuitry is further configured to read the second data elements from the memory array according to a third addressing sequence (see at least Paragraph [0155]: “a third rearrangement circuit for rearranging digital data received by a third receiving circuit 138. 132 denotes a third memory unit for temporarily storing data for realizing a part of the rearrangement process by the third rearrangement circuit 131”).
As to claim 6, the combination of Tajimij, Anderson and Lee teaches the apparatus of claim 1. Tajimij discloses further wherein the control circuitry is further configured to read the second data elements from the memory array using a third sequence of addresses (see at least Paragraph [0133]: “Additionally, as mentioned before, odd column pixels are read out to be supplied to the first ADC 1303 and even pixels are read out to be supplied to the second ADC 1301, and respectively AID converted. Therefore, as shown in FIG. 10, a group of odd column signals and a group of even column signals are respectively read out at different timings.”…” a sequence of reading out rows has a particular feature. For example, in FIG. 10, in a first H period, the 1, 3, 4 and 6th row signals of odd columns and even columns are read out, and in the second H period, the 0, 2, 5 and 7th row signals of odd columns and even columns are read out.”).
As to claim 8, the combination of Tajimij, Anderson and Lee teaches the apparatus of claim 1. Tajimij discloses wherein the second data elements are written to a first series of memory locations in an order (see at least Paragraph [0050]: “it is possible to perform control for switching the number of rows to be simultaneously read out and a number of rows rearranged in the first rearrangement circuit 111, and the like in accordance with an operation of the imaging apparatus 100. In addition, according to a control from the central processing unit 128, the first rearrangement circuit 111 and the first memory unit 112”) that the first data elements are read from the first series of the memory locations (see at least Paragraph [0112]: “By the above sequence, 5 to 12th row signals are rearranged to restore the original pixel arrangement (row order) in the pixel unit 113. Accordingly, four row signals (5, 7, 9 and 11th row signals) read out from the second memory unit 122 are alternately combined with the 6, 8, 10 and 12th row signals read out from the AID conversion unit 114. As a result, 1st to 12th row signals are rearranged to restore the original pixel arrangement (row order) in the pixel unit 113”).
As to claim 9, the combination of Tajimij, Anderson and Lee teaches the apparatus of claim 1. Tajimij further discloses wherein the control circuitry is further determine the second sequence of addresses so as to read the first data elements from the memory array in a configured to column-major order (see at least Paragraph [0137]: “In FIG. 10, as the information processing unit 120 performs the rearrangement process regarding row and column directions, the rearrangement process becomes complicated and the second memory unit 122 needs to store pixel signals of eight rows at the same time”).
As to claim 10, the combination of Tajimij, Anderson and Lee teaches the apparatus of claim 1. Tajimij discloses further comprising an image capture device configured to capture the first data elements and the second data elements in a row-by-row format (see at least Paragraph [0135]: “first, ol, o3, o4 and 06 row signals are stored in the second memory unit, then e 1, e3, e4 and e6 row signals are stored in the second memory unit.”; and [0136]: “Thereafter, o0, o2, o5 and o7 row signals are stored in the second memory unit, and then e0, e2, e5 and e7 row signals are stored in the second memory unit, so that they are rearranged to restore the original pixel arrangement order”), wherein the first data elements being representative of pixel values of the first image and the second data elements being representative of pixel values of the second image (see at least Paragraph [0138]: “in contrast to FIG. 10, after the first memory unit 112 and the first rearrangement circuit 111 perform the rearrangement process for restoring pixel arrangement in a column direction, all the pixel signals in row direction are transferred to the information processing unit 120. Next, the second memory unit 122 and the second rearrangement circuit 121 perform the rearrangement process for restoring original row orders”).
As to claim 11, the combination of Tajimij, Anderson and Lee teaches the apparatus of claim 1. Tajimij discloses wherein the control circuitry is further configured to: read the second data elements from the memory array using a third sequence of addresses (see at least Paragraph [0155]: “First, the digital front-end circuit 135 is explained. 131 denotes a third rearrangement circuit for rearranging digital data received by a third receiving circuit 138. 132 denotes a third memory unit for temporarily storing data for realizing a part of the rearrangement process by the third rearrangement circuit 131.”); write third data elements of a third image in the memory locations in a row-major order using the third sequence of addresses (see at least Paragraph [0156]: “139 denotes a third transmitting circuit for converting digital data rearranged by the third rearrangement circuit 131 for transmission to the information processing unit 120 via a second I/F 202”); and read the third data elements in a column-major order from the memory array using a fourth sequence of addresses (see at least Paragraph [0157]\: “The second I/F 202 is an interface for transferring signals converted by the third transmitting circuit 139 to the information processing unit 120”; and [0158]: “According to the structure of FIG. 14, the rearrangement process is allotted to the first rearrangement circuit 111, the second rearrangement circuit 121, and the third rearrangement circuit 131. That is, compared to the imaging apparatus 100, the workload for the rearrangement process is more divided, and this embodiment has further merit when the digital front-end circuit 135 is formed with the image sensor in multi-layer arrangement”).
As to claim 12, the combination of Tajimij, Anderson and Lee teaches the apparatus of claim 1. Tajimij discloses further comprising an optical system configured to receive light at an image sensor, wherein the image sensor comprises a plurality of pixel elements aligned in a plurality of horizontal rows and a plurality of vertical columns (see at least Paragraph [0088]: “the plurality of pixel signals of the second pixel row of every column is AID converted by the ADC row by row to be read out in one horizontal period. Similarly, in response to N+2nd timing of H sync signal, the third pixel row of each column is simultaneously read out, and in response to N+3rd timing, the fourth pixel row of each column is simultaneously read out”).
As to claim 13, the combination of Tajimij, Anderson and Lee teaches the apparatus of claim 12. Tajimij discloses wherein the control circuitry is further configured to obtain image data from the image sensor by sampling one or more pixel elements of the image sensor (see at least Paragraphs [0066]: “FIG. 2 shows a structure of a pair of pixels in the pixel unit 113 of the image sensor 110, and FIG. 3 shows an example of pixel arrangement in the pixel unit 113”; and [0148]: “the first rearrangement circuit rearranges pixel signals of predetermined rows or columns necessary for advancing processing in the information processing unit, which is external to the image sensor, and in parallel with the rearrangement process by the second rearrangement circuit”).
Regarding claim 15, recites analogous limitations that are present in claim 1, therefore claim 15 would be rejected for the same/similar reasons above.
As to claim 16, recites analogous limitations that are present in claim 2, therefore claim 16 would be rejected for the same/similar reasons above.
As to claim 17, recites analogous limitations that are present in claim 3, therefore claim 17 would be rejected for the same/similar reasons above.
As to claim 18, recites analogous limitations that are present in claim 8, therefore claim 18 would be rejected for the same/similar reasons above.
As to claim 19, recites analogous limitations that are present in claim 11, therefore claim 19 would be rejected for the same/similar reasons above.
Regarding claim 20, recites analogous limitations that are present in claim 1, therefore claim 20 would be rejected for the same/similar reasons above.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Tajimij, Anderson and Lee, and in view of Adenwala et al. (US 2019/0079659l; previously recorded), hereinafter, referred to as “Adenwala”.
As to claim 14, the combination of Tajimij, Anderson and Lee teaches the apparatus of claim 1. Tajimij in view of Anderson teaches …the memory array and the control circuitry, however, neither Tajimij nor Anderson or Lee explicitly teaches a vehicle, wherein the vehicle includes the memory array and the control circuitry.
However, pertinent art reference, Adenwala teaches
a vehicle, wherein the vehicle includes the memory array and the control circuitry (see at least Paragraph [0221]: “vehicle comprise: processor circuitry, memory circuitry, the communication system, the one or more sensors, the one or more DCUs, and an interconnect technology that couples the one or more hardware elements to one another”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the filing of the invention to further modify Tajimij in view of Anderson and Murrin by combining a vehicle, wherein the vehicle includes the memory array and the control as taught by Adenwala. One would be motivated to make this modification in order to perform similar results.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Tajimij, Anderson and Lee, and in view of Wyld et al. (US 2008/0167083; previously recorded), hereinafter, referred to as “Wyld”.
As to claim 21, the combination of Tajimij, Anderson and Murrin teaches the apparatus of claim 1. Neither Tajimij nor Anderson or Murrin teaches wherein the stream includes a sequence of images, and wherein the first image and the second image comprise sequential images in the stream.
However, Wyld teaches
wherein the stream includes a sequence of images (see at least Paragraph [0056]: “the optical sensor(s) 164, the imaging module 142 may be used to capture still images or video (including a video stream) and store them into memory 102, modify characteristics of a still image or video, or delete a still image or video from memory 102”), and wherein the first image and the second image comprise sequential images in the stream (see at least Paragraph [0083]: “prior to sending an address message corresponding to the second sequence of symbols, information is displayed (310) which indicates that an address message that corresponds to a sequence of symbols different from the first sequence of symbols will be sent to the communications network (FIG. 5L)”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the filing of the invention to further modify Tajimij in view of Anderson and Murrin by combining wherein the stream includes a sequence of images, and wherein the first image and the second image comprise sequential images in the stream as taught by Wyld. One would be motivated to make this modification in order to convey where it will be appreciated by those of ordinary skill in the art that one or more of the acts described may be performed by hardware, software, or a combination thereof. In addition, it will be appreciated by those of ordinary skill in the art that some of the processes shown in FIG. 4 (or subsets or supersets thereof) can be performed in a different order (see at least Paragraph [0068]).
Conclusion
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/B.U./Examiner, Art Unit 3663
/JAMES M MCPHERSON/Examiner, Art Unit 3663
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