DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-21 are pending.
Claims 8-21 are withdrawn.
Claim 1 is currently amended.
Claims 2 and 3 are original.
Claims 4-7 are previously presented.
Claims 1-7 are rejected herein.
Response to Arguments
Applicant's arguments filed 09/12/2025 have been fully considered but they are not persuasive.
Applicant has amended claim 1 to include the limitation that “the first one of the bitlines is between the first one of the wordlines and the two or more ferroelectric capacitors along a vertical direction orthogonal to the first direction and the second direction” and argues that Pan does not disclose the foregoing. Remarks, pages 10. This argument is not persuasive.
Notably, Applicant’s amendment to claim 1 has necessitated the new grounds of rejection herein. In particular, while the same prior art is being applied, the manner in which Pan has been applied to claim 1 has been modified.
Specifically, Pan discloses an array of lower ferroelectric memory cells (304) similar to the array of upper ferroelectric memory cells (306). See, e.g., FIG. 3 and paragraphs [0104]-[0106]. Accordingly, in the array of lower ferroelectric memory cells (304), when the memory device (300) of Pan is oriented to be inverted: the series of alternating plate lines (328’, 329’) and insulating material (326’, 330’, 327’, 331’) are “over” the access transistor (314), as claimed; the two or more ferroelectric capacitors (316-1’, 316-2’) are “over” the access transistor (314), as claimed; and, the first one (308’) of the bitlines (308) is between the first one (322’) of the wordlines (322) and the two or more ferroelectric capacitors (316-1’, 316-2’) along a vertical direction (z) orthogonal to the first direction (y) and the second direction (x), as claimed. See generally, e.g., FIG. 3 of Pan as annotated herein. For a full discussion of how Pan has been applied to claim 1, see the rejection of claim 1 herein below.
Applicant has once again not amended the Abstract or traversed the objection thereto. Accordingly, the objection to the Abstract is still maintained.
Specification
The abstract of the disclosure is objected to because it exceeds 150 words in length. Correction is required. See MPEP § 608.01(b).
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Pan (US 20200051607 A1) in view of Morris (US 20200091162 A1).
[AltContent: textbox (316-1’)][AltContent: textbox (316-2’)][AltContent: textbox (331’)][AltContent: textbox (327’, 330’)][AltContent: textbox (326’)][AltContent: textbox (328’)][AltContent: textbox (329’)][AltContent: textbox (322’)][AltContent: textbox (308’)]
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ANNOTATED FIG. 3 OF PAN
Regarding claim 1, Pan discloses (see generally, e.g., FIG. 1A and FIG. 3 as annotated herein):
a memory device (300), comprising:
a plurality of bitlines (308) along a first direction (y) (see also, e.g., paragraph [0072]);
a plurality of wordlines (322) along a second direction (x) orthogonal to the first direction (y) (see also, e.g., paragraph [0072]);
an access transistor (314) at an intersection of a first one (308’) of the bitlines (308) and a first one (322’) of the wordlines (322);
a series of alternating plate lines (328’, 329’) and an insulating material (326’, 330’, 327’, 331’) over the access transistor (314), wherein each of the plate lines (328’, 329’) comprises a single plate (see, e.g., FIGS. 1A and 3);
two or more ferroelectric capacitors (316-1’, 316-2’) over the access transistor (314) and through the series of alternating plate lines (328’, 329’) and the insulating material (326’, 330’, 327’, 331’) such that a first one of the ferroelectric capacitors (316-1’) is coupled to and completely laterally surrounded by a first one of the plate lines (329’) and a second one of the ferroelectric capacitors (316-2’) is coupled to and completely laterally surrounded by a second one of the plate lines (328’), wherein the two or more ferroelectric capacitors (316-1’, 316-2’) are each coupled to and controlled by the access transistor (314).
Pan further discloses wherein the first one (308’) of the bitlines (308) is between the first one (322’) of the wordlines (322) and the two or more ferroelectric capacitors (316-1’, 316-2’) along a vertical direction (z) orthogonal to the first direction (y) and the second direction (x).
Note, when the memory device (300) of Pan is inverted: the series of alternating plate lines (328’, 329’) and insulating material (326’, 330’, 327’, 331’) are “over” the access transistor (314); the two or more ferroelectric capacitors (316-1’, 316-2’) are “over” the access transistor (314); and the first one (308’) of the bitlines (308) is between the first one (322’) of the wordlines (322) and the two or more ferroelectric capacitors (316-1’, 316-2’) along a vertical direction (z) orthogonal to the first direction (y) and the second direction (x).
Pan does not explicitly disclose the access transistor comprising a fin channel structure and a gate electrode, wherein the gate electrode is over a top of the fin channel structure.
However, in analogous art, Morris discloses an access transistor (110) comprising a fin channel structure (202) and a gate electrode (212), wherein the gate electrode (212) is over a top of the fin channel structure (202). See generally, e.g., FIG. 2.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted and/or used an access transistor comprising a fin channel structure and a gate electrode, wherein the gate electrode is over a top of the fin channel structure as taught by Morris for the access transistor (314) of Pan according to known methods to yield predictable results, for example, to employ a known type of field-effect transistor (i.e., a FinFET) for its intended purpose (i.e., as an access transistor in a FeRAM device). Additionally, in a FinFET, having the gate wrap around three sides of the channel increases the surface area of interaction between the gate and channel, thereby improving control of the channel’s electric state and providing better performance. FinFETs further generally benefit from reduced current leakage, lower switching voltages which contribute to improved energy efficiency, higher drive current and faster switching speeds, etc.
Regarding claim 2, Pan in view of Morris as applied to claim 1 discloses the memory device of claim 1.
Pan further discloses, wherein each of the two or more ferroelectric capacitors (316-1’, 316-2’) comprise a bit cell (304), and wherein a voltage (e.g., 0 V) across bit cells that are not being written is up to 75% of a voltage (e.g., Vdd) applied to the bit cells being written to along a same plate line (328’, 329’) (see also, e.g., FIGS. 10 and 12A and paragraphs [0152]-[0157]). Note, 0 V is “up to 75%” of Vdd.
Note, during a read operation a cell is not being written and 1 V is applied across the cell (see, e.g., paragraph [0056]); and during a write operation a cell is being written to and 5 V is applied across the cell (see, e.g., paragraph [0057]). 1 V is “up to 75%” of 5 V as claimed.
Regarding claim 3, Pan in view of Morris as applied to claim 1 discloses the memory device of claim 1.
Pan further discloses, wherein the two or more ferroelectric capacitors (316-1’, 316-2’) are formed in a hole (620) (see additionally, e.g., FIG. 6D) through the series of alternating plate lines (328’, 329’) and an insulating material (326’, 330’, 327’, 331’), and wherein the hole (620) is lined with a ferroelectric material (334, 624) (see additionally, e.g., FIG. 6E) and filled with a conductive material (332, 626) to form a node.
Regarding claim 7, Pan in view of Morris as applied to claim 1 discloses the memory device of claim 1.
Pan further discloses, wherein the ferroelectric material comprises a combination of hafnium, zirconium and oxygen (see, e.g., paragraph [0083]).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Pan in view of Morris as applied to claim 3, and further in view of Peng (US 20160118404 A1).
Regarding claim 4, Pan in view of Morris as applied to claim 3 discloses the memory device of claim 3.
Pan does not explicitly disclose wherein the hole is 40-200 nm in diameter.
However, Peng, in analogous art, discloses a hole that is 40-200 nm in diameter. In particular, Peng discloses a width (i.e., diameter) of the hole is “preferably from 1 nm to 100 nm although it can be varied further depending on the device performance.” Paragraph [0031].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have made the hole (620) of Pan 40-200 nm in diameter as taught by Peng according to known methods to yield predictable results, for example, in order to achieve a desired device performance and/or have a hole sufficiently large to readily enable the depositing and/or forming therein of the respective layers and/or elements contained within the hole while still maintaining a suitably compact device. Moreover, changes in size normally require only ordinary skill in the art and hence are considered routine expedients. Indeed, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is generally not patentably distinct from the prior art device. See, e.g., MPEP §2144.04(IV)(A). In the present case, there is no evidence on the record that a device having the claimed dimensions would perform differently than the prior art device.
Regarding claim 5, Pan in view of Morris as applied to claim 3 discloses the memory device of claim 3.
Pan does not explicitly disclose wherein the hole is 150 nm in diameter.
However, Peng, in analogous art, discloses a hole that is approximately 150 nm in diameter. In particular, Peng discloses a width (i.e., diameter) of the hole is “preferably from 1 nm to 100 nm although it can be varied further depending on the device performance.” Paragraph [0031].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have made the hole (620) of Pan 150 nm in diameter as taught by Peng according to known methods to yield predictable results, for example, in order to achieve a desired device performance and/or have a hole sufficiently large to readily enable the depositing and/or forming therein of the respective layers and/or elements contained within the hole while still maintaining a suitably compact device. Moreover, changes in size normally require only ordinary skill in the art and hence are considered routine expedients. Indeed, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is generally not patentably distinct from the prior art device. See, e.g., MPEP §2144.04(IV)(A). In the present case, there is no evidence on the record that a device having the claimed dimensions would perform differently than the prior art device.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Pan in view of Morris as applied to claim 1, and further in view of Sel (US 20190034125 A1).
Regarding claim 6, Pan in view of Morris as applied to claim 1 discloses the memory device of claim 1.
Pan does not explicitly disclose wherein the plate lines are up to 350 nm in thickness, and the insulating material are up to 50 nm in thickness.
However, in analogous art, Sel discloses plate lines (WL10, WL20, WL30, WL40, WL50) that are up to 350 nm in thickness (see, e.g., paragraph [0131] disclosing that the “conductive material layer 322 is between about 5 nm and about 30 nm” – note, material layer 322 corresponds to the plate lines (WL10, WL20, WL30, WL40, WL50)), and insulating material (318) that are up to 50 nm in thickness (see, e.g., paragraph [0117] disclosing that the “dielectric material layer 318 may be between about 5 nm and about 25 nm”).
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have made the memory device (300) of Pan such that the plate lines (328, 329) are up to 350 nm in thickness, and the insulating material (326, 330, 327, 331) are up to 50 nm in thickness as taught by Sel according to known methods to yield predictable results, for example, in order to achieve a device with layers sufficiently thin to keep the device suitably compact. Moreover, changes in size normally require only ordinary skill in the art and hence are considered routine expedients. Indeed, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is generally not patentably distinct from the prior art device. See, e.g., MPEP §2144.04(IV)(A). In the present case, there is no evidence on the record that a device having the claimed dimensions would perform differently than the prior art device.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P CORNELY whose telephone number is (571)272-4172. The examiner can normally be reached Monday - Thursday 8:30 AM - 4:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JOHN P. CORNELY
Examiner
Art Unit 2812
/J.P.C./Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812