DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 12/10/2025 have been fully considered but they are not persuasive. Regarding the arguments on pages 7-12, Shin (US20220037287A1) teaches the single, nitrogen-free tantalum (Ta) barrier layer has a concave bottom surface at the bottom of the conductive via (para [0074-0076], recessed portion 403R of the barrier layer 403R).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Shin (US20220037287A1), and further in view of Cheng (US6086777A).
Regarding claim 1, Shin teaches an integrated circuit structure (Fig. 10, semiconductor device 1A), comprising:
a first conductive interconnect line (pad layer 303) in a first inter-layer dielectric (ILD) layer (first dielectric layer 103) above a substrate (first substrate 101), the first conductive line having a cobalt fill (para [0052], conductive material, copper alloy which contains cobalt);
a second conductive interconnect line (upper portion 405U of the filler layer 405) in a second ILD layer above the first interlayer dielectric (ILD) layer (bonding layer 105); and
a conductive via coupling the first conductive interconnect line and the second conductive interconnect line (recessed portion 405R),
wherein the second conductive interconnect line and the conductive via comprise a copper fill (para [0080-0081], conductive material, copper) directly on a single, nitrogen-free tantalum (Ta) barrier layer (para [0075], barrier layer 403 is formed of tantalum), and
wherein the single, nitrogen-free tantalum (Ta) barrier layer is directly on the cobalt fill of the first conductive line (Fig. 10), and
wherein the single, nitrogen-free tantalum (Ta) barrier layer has a concave bottom surface at the bottom of the conductive via (para [0074-0076], recessed portion 403R of the barrier layer 403R).
But does not specify wherein the single, nitrogen-free tantalum (Ta) barrier layer has a thickness a bottom of the conductive via greater than a thickness along a side of the conductive via.
However, Cheng teaches the single, nitrogen-free tantalum (Ta) barrier layer has a thickness along a bottom of the conductive via greater than a thickness along a side of the conductive via (Fig. 10, tantalum barrier layer 32 has a thickness along a bottom of the conductive layer 34 greater than a thickness along a side of the conductive layer 34).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the method for manufacturing a semiconductor device of Shin (US20220037287A1) by further integrating the method of etching tantalum disposed over a dielectric layer disclosed by Cheng (US6086777A). The combination of these familiar elements can improve the circuit density and increase speeds of semiconductor devices (Cheng, Col. 1, lines 25-30).
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Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Shin (US20220037287A1) in view of Cheng (US6086777A) as applied to claim 1 above, and further in view of Cheng546 (US20200058546A1).
Regarding claim 2, Shin in view of Cheng teaches the integrated circuit structure of claim 1, but does not disclose single, nitrogen-free tantalum (Ta) barrier layer has a thickness in a range of 1-5 nanometers.
However, Cheng546 teaches the single, nitrogen-free tantalum (Ta) barrier layer has a thickness in a range of 1-5 nanometers (Chang 546 disclosed in Para [0042] and Fig. 13, diffusion barrier layer 242 is embedded within the etch stop layer 210, which has a thickness of less than 3 nm. Therefore, the thickness of element 242 is also less than 3 nm).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the method for manufacturing a semiconductor device of Shin (US20220037287A1) by further integrating the method of manufacturing an IC device disclosed by Cheng546 (US20200058546A1). The combination of these familiar elements can reduce the parasitic capacitance and increase the operation speed of the ICs (Cheng546, para [0047]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAHAE KIM whose telephone number is (571)270-1844. The examiner can normally be reached M-F 9-5.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JAHAE KIM/Examiner, Art Unit 2897