Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsu et al. (Pub No. US 2021/0335753 A1, hereinafter Hsu).
With regards to claim 1, Hsu teaches a method of efficient chip manufacturing, the method comprising:
assembling at least two chips on a layer (see Fig. 13, two chips 50A/50B shown on a layer 140 for example); and
applying mold compound to the at least two chips including flowing around interconnects between the at least two chips and a redistribution layer in a single step, thereby leaving a top of each of the at least two chips exposed, wherein the mold compound surrounds at least two lateral sides of each of the at least two chips, and is disposed between the at least two chips and the redistribution layer (see Fig. 13, underfill 150 between chips 50A/50B, tops of chips exposed, underfill 150 surrounds lateral sides of 50A/50B, disposed between 50A/50B and redistribution layer 120 (i.e. sans layer 140)).
With regards to claim 2, Hsu teaches the method of claim 1, further comprising: attaching a substrate (see Fig. 13, substrate 102).
With regards to claim 3, Hsu teaches the method of claim 1, wherein the at least two chips are heterogenous chips (see ¶49).
With regards to claim 4, Hsu teaches the method of claim 1, wherein the at least two chips are chips of the same type (see Fig. 13, chips 50A/50B are same type).
With regards to claim 5, Hsu teaches the method of claim 1, wherein the at least two chips are a two dimensional (2.5d) package (see Fig. 13, multiple chips arranged side by side and all part of one package).
Claim(s) 8, 9, 11, 13, 14, 15, 17, and 19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsu et al. (Pub No. US 2021/0296220 A1, hereinafter Hsu ‘220).
With regards to claim 8, Hsu ‘220 teaches an apparatus with efficient chip manufacturing, the apparatus formed by steps comprising:
An interposer (see Fig. 14, interposer 66);
at least two chips coupled to the interposer (see Fig. 14, two chips 52A/52B on interposer 66); and
a plurality of interconnects between the at least two chips and the interposer (see Fig. 14, plurality of interconnects 53);
a uniform mold compound layer surrounding at least two lateral sides of each of the at least two chips and extending between at least two chips and the interposer to underfill around the plurality of interconnects thereby leaving a top of each of the at least two chips exposed (see Fig. 14, uniform mold compound 56 surrounding lateral sides of each side of 52A/52B, underfill around 42, tops of 52A/52B exposed; product by process claims not afforded significant patentable weight).
With regards to claim 9, Hsu ‘220 teaches the apparatus of claim 8, further comprising a substrate (see Fig. 14, substrate can be construed as 48).
With regards to claim 11, Hsu ‘220 teaches the apparatus of claim 8, wherein the apparatus comprises at least one of a two dimensional (2.5d) package, a die-last wafer-level fanout package, and a die-first wafer-level fanout package (see Fig. 14, multiple chips arranged side by side and all part of one package).
With regards to claim 13, Hsu ‘220 teaches the apparatus of claim 8, wherein the top of each of the at least two chips is exposed via applying of the uniform mold compound layer and not by a grinding process (product by process claims are not afforded significant patentable weight).
With regards to claim 14, Hsu ‘220 teaches an apparatus with efficient chip manufacturing, the apparatus formed by steps comprising:
a redistribution layer (see Fig. 14, redistribution layer 48);
at least two chips coupled to the redistribution layer (see Fig. 14, 52A/52B, two chips on redistribution layer 48); and
a plurality of interconnects between the at least two chips and the redistribution layer (see Fig. 14, plurality of interconnects 53): and
a uniform mold compound layer surrounding at least two lateral sides of each of the at least two chips and extending between at least two chips and the redistribution layer to underfill around the plurality of interconnects thereby leaving a top of each of the at least two chips exposed (see Fig. 14, uniform mold compound 56 surrounding lateral sides of each side of 52A/52B, underfill around 42, tops of 52A/52B exposed; product by process claims not afforded significant patentable weight).
With regards to claim 15, Hsu ‘220 teaches the apparatus of claim 14, further comprising: a substrate (see Fig. 14, substrate 66).
With regards to claim 17, Hsu ‘220 teaches the apparatus of claim 14, wherein the apparatus comprises a two dimensional (2.5d) package (see Fig. 14, multiple chips arranged side by side and all part of one package).
With regards to claim 19, Hsu ‘220 teaches the apparatus of claim 14, wherein the top of each of the at least two chips is exposed via applying of the uniform mold compound layer and not by a grinding process (product by process claims are not given significant patentable weight).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 10 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu ‘220 as applied to claim 1 above, and further in view of Hsu.
With regards to claim 10, Hsu ‘220 is silent teaching the apparatus of claim 8, wherein the at least two chips are heterogeneous chips.
In the same field of endeavor, Hsu teaches how two chips on a substrate can be heterogeneous (see ¶49).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time of filing for the two chips to be heterogeneous in order to incorporate more functionality to the package as taught by Hsu.
With regards to claim 16, Hsu ‘220 is silent teaching the apparatus of claim 14, wherein the at least two chips are heterogenous chips.
In the same field of endeavor, Hsu teaches how two chips on a substrate can be heterogeneous (see ¶49).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time of filing for the two chips to be heterogeneous in order to incorporate more functionality to the package as taught by Hsu.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu ‘220 as applied to claim 8 above, and further in view of Chen et al. (USP# 11,854,961 B2, hereinafter Chen).
With regards to claims 12, Hsu ‘220 is silent teaching the apparatus of claim 8, further comprising:
a redistribution layer; and
a plurality of pillars extending through the interposer connecting the at least two chips and the redistribution layer.
In the same field of endeavor, Chen teaches a configuration of a packaging with a redistribution layer and a plurality of pillars passing through an interposer connecting a chip and the redistribution layer (see Fig. 2A, 10B for example, interposer identified as 22 shown in Fig. 10B as well, redistribution layer identified as 110, interposer 22 with plurality of pillars within that connects chip 10 to redistribution layer 110).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time of filing to incorporate a redistribution layer with an interposer and pillars connecting the redistribution layer with the chip in order to properly route signals to their desired locations as taught by Chen.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu ‘220 as applied to claim 15 above, and further in view of Yu (Pub No. US 2018/0366403 A1, hereinafter Yu).
With regards to claim 18, Hsu ‘220 is silent teaching the apparatus of claim 15, wherein the at least two chips are disposed on an embedded silicon bridge fan-out.
In the same field of endeavor, Yu teaches how embedded silicon fan-out structures are beneficial because it solves warpage problems or mismatch of thermal expansion coefficients (see ¶8).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time of filing to utilize an embedded silicon fan-out structure because it solves warpage problems or mismatch of thermal expansion coefficients as taught by Yu.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu ‘220 as applied to claim 1 above, and further in view of Min et al. (Pub No. US 2020/0294964 A1, hereinafter Min).
With regards to claim 20, Hsu ‘220 is silent teaching the method of claim 1, wherein the apparatus comprises at least one of a die-last wafer-level fanout package and a die-first wafer-level fanout package.
In the same field of endeavor, Min teaches how a chip last fan out process is beneficial because its developed to improve the yield rate (see ¶26).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time of filing to utilize a die-last wafer-level fanout package due to increased yield rates as taught by Min.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/JAE LEE/Primary Examiner, Art Unit 2899
JML
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