Office Action Predictor
Last updated: April 17, 2026
Application No. 17/139,715

QUANTUM COMPUTING CIRCUIT COMPRISING A PLURALITY OF CHIPS AND METHOD FOR MANUFACTURING THE SAME

Non-Final OA §102§103
Filed
Dec 31, 2020
Examiner
VU, HUNG K
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Iqm Finland Oy
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
97%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
861 granted / 984 resolved
+19.5% vs TC avg
Moderate +9% lift
Without
With
+9.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
30 currently pending
Career history
1014
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
42.0%
+2.0% vs TC avg
§102
40.0%
+0.0% vs TC avg
§112
11.4%
-28.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 984 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Invention of Group I, Claims 1-16, Embodiment 3 of Figure 6, Claims 1-6 and 11-16, in the reply filed on 11/11/2024 is acknowledged. The traversal is on the ground(s) that the Office Action has not shown that a serious burden would be required to examine all of the claims and that the examination of all species would not be a burden to the Examiner. This is not found persuasive because the fields of search for device and method claims are not coextensive and the determinations of patentability of method and device claims are different, that is device limitations and method limitations are given weight differently in determining the patentability of the claimed inventions. Also, the strategies for doing text searching of the device claims, the method claims, and their species are different. Thus, separate searches are required. The requirement is still deemed proper and is therefore made FINAL. Claims 7-10 and 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 11/11/2024. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-6 and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by White (US 2019/0229094). White discloses, as shown in Figures 1-3, a quantum computing circuit comprising: a first chip (102) including at least one qubit [0035]; and a second chip (104) including at least other quantum circuit elements other than qubits [0040], wherein the first chip and the second chip are stacked together in a flip-chip configuration and attached to each other via bump bonding that includes bonding bumps (106). Regarding claim 2, White discloses the first chip is made of a first set of constituent materials, the second chip is made of a second set of constituent materials, and the first and second sets consist of at least partly different constituent materials [0037]-[0045], [0049], [0051]. Regarding claim 3, White discloses the second set of constituent materials includes at least one material that is not present in the first set of constituent materials and is one of aluminum oxide, copper, palladium, or another non-superconductive metal [0037]-[0045], [0049], [0051]. Regarding claim 4, White discloses the first chip and the second chip are different [0035]-[0045], [0049], [0051]. Note that the term “the first chip is manufactured in a first manufacturing process that includes a first sequence of manufacturing steps, the second chip is manufactured in a second manufacturing process that includes a second sequence of manufacturing steps, and the first and second sequences are at least partly different sequences of manufacturing steps” is method recitation in a device claimed. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Regarding claim 5, White discloses at least some of the bonding bumps are galvanically conductive and constitute galvanically conductive contacts between the first and second chips (see Figures 1-3) [00. Regarding claim 6, White discloses one of the first and second chips is a larger chip and the other of the first and second chips is a smaller chip that covers only a part of the larger chip in the flip-chip configuration (see Figures 1-3). Regarding claim 16, White discloses a separating distance between the first and second chips is between 1 and 100 micrometers [0043]. Claim(s) 1-6, 11-13 and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kelly et al. (WO2018/169585, of record). Kelly et al. discloses, as shown in Figures 1A-2B, a quantum computing circuit comprising: a first chip (102,202) including at least one qubit [0041], [0048]; and a second chip (104,204) including at least other quantum circuit elements other than qubits [0042], [0049], wherein the first chip and the second chip are stacked together in a flip-chip configuration and attached to each other via bump bonding that includes bonding bumps (106). Regarding claim 2, Kelly et al. discloses the first chip is made of a first set of constituent materials, the second chip is made of a second set of constituent materials, and the first and second sets consist of at least partly different constituent materials [0047]-[0049]. Regarding claim 3, Kelly et al. discloses the second set of constituent materials includes at least one material that is not present in the first set of constituent materials and is one of aluminum oxide, copper, palladium, or another non-superconductive metal [0047]-[0049]. Regarding claim 4, Kelly et al. discloses the first chip and the second chip are different [0047]-[0049]. Note that the term “the first chip is manufactured in a first manufacturing process that includes a first sequence of manufacturing steps, the second chip is manufactured in a second manufacturing process that includes a second sequence of manufacturing steps, and the first and second sequences are at least partly different sequences of manufacturing steps” is method recitation in a device claimed. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Regarding claim 5, Kelly et al. discloses at least some of the bonding bumps are galvanically conductive and constitute galvanically conductive contacts between the first and second chips (see Figures 1A-2B). Regarding claim 6, Kelly et al. discloses one of the first and second chips is a larger chip and the other of the first and second chips is a smaller chip that covers only a part of the larger chip in the flip-chip configuration (see Figures 1A-1B). Regarding claim 11, Kelly et al. discloses the circuit further comprising a non-galvanic connection for conveying signals between the first and second chips, wherein the non-galvanic connection includes matching non-galvanic connector structures on surfaces of the first and second chips that face each other. Regarding claim 12, Kelly et al. discloses the matching non-galvanic connector structures include mutually aligned conductive areas on the surfaces of the first and second chips facing each other for making a capacitive connection. Regarding claim 13, Kelly et al. discloses the matching non-galvanic connector structures include mutually aligned inductive elements for making a magnetic connection. Regarding claim 16, Kelly et al. discloses a separating distance between the first and second chips is between 1 and 100 micrometers [0044]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over White (US 2019/0229094) in view of Kelly et al. (WO2020/231378). White discloses the claimed invention including the circuit as explained in the above rejection. White does not disclose the second chip includes a quantum circuit refrigerator and the quantum computing circuit includes a controllable connection between the quantum circuit refrigerator and at least one qubit on the first chip to enable the quantum circuit refrigerator to be controllably used to reset a state of the at least one qubit. However, Kelly et al. discloses the second chip includes a quantum circuit refrigerator and the quantum computing circuit includes a controllable connection between the quantum circuit refrigerator and at least one qubit on the first chip to enable the quantum circuit refrigerator to be controllably used to reset a state of the at least one qubit. Note Figures 1 and 2 of Kelly et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the second chip of White including a quantum circuit refrigerator and the quantum computing circuit includes a controllable connection between the quantum circuit refrigerator and at least one qubit on the first chip, such as taught by Kelly et al. in order to enable the quantum circuit refrigerator to be controllably used to reset a state of the at least one qubit. Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kelly et al. (WO2018/169585, hereafter, Kelly et al.’585, of record) in view of Kelly et al. (WO2020/231378, hereafter, Kelly et al.’378). Kelly et al.’585 discloses the claimed invention including the circuit as explained in the above rejection. Kelly et al.’585 does not disclose the second chip includes a quantum circuit refrigerator and the quantum computing circuit includes a controllable connection between the quantum circuit refrigerator and at least one qubit on the first chip to enable the quantum circuit refrigerator to be controllably used to reset a state of the at least one qubit. However, Kelly et al.’378 discloses the second chip includes a quantum circuit refrigerator and the quantum computing circuit includes a controllable connection between the quantum circuit refrigerator and at least one qubit on the first chip to enable the quantum circuit refrigerator to be controllably used to reset a state of the at least one qubit. Note Figures 1 and 2 of Kelly et al.’378. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the second chip of Kelly et al.’585 including a quantum circuit refrigerator and the quantum computing circuit includes a controllable connection between the quantum circuit refrigerator and at least one qubit on the first chip, such as taught by Kelly et al.’378 in order to enable the quantum circuit refrigerator to be controllably used to reset a state of the at least one qubit. Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kelly et al. (WO2018/169585, of record) in view of de Rochemont (WO2019/236734). Kelly et al. discloses the claimed invention including the circuit as explained in the above rejection. Kelly et al. further discloses the second chip includes at least one of a capacitor and/or an inductor. It is known that the capacitor and/or inductor is used as part of the filter. Kelly et al. does not disclose the filter comprises at least one of: a non-superconductive metal, or a lossy dielectric. However, de Rochemont disclose a filter (302) comprises at least one of: a non-superconductive metal, or a lossy dielectric. Note page 55, line 13 – page 56, line 9 and Figures 7A-9F of de Rochemont. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the filter of Kelly et al. comprises at least one of: a non-superconductive metal, or a lossy dielectric, such as taught by de Rochemont in order to perform the desired function. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG K VU whose telephone number is (571)272-1666. The examiner can normally be reached Monday - Friday: 7am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ANDRES MUNOZ can be reached on (571) 270-3346. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HUNG K VU/ Primary Examiner, Art Unit 2897
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Prosecution Timeline

Dec 31, 2020
Application Filed
Feb 08, 2025
Non-Final Rejection — §102, §103
May 02, 2025
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
97%
With Interview (+9.3%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 984 resolved cases by this examiner. Grant probability derived from career allow rate.

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