DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/2/2026 has been entered.
Response to Arguments
(Submitted 4/2/2026)
Examiner’ Note:
The applicant made amendments to the claims on 4/2/26 . Applicant’s arguments with respect to claim 1, 5 and 13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The examiner has used two new references “”Cao” and “Hamze” to teach claim 1, and claim 13 and has used new reference “Chen” to teach claim 5. A new reference “Berch” teaches the dependent claims 3-4, 7-8 and 15-16.
In CONCLUSION, the examiner as a result of the arguments provided above, rejects claims 1-5, 7-
13 and 15-20 as NON-FINAL REJECTION (RCE) under 103.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 13 and 17-20 is rejected under 35 U.S.C. 103 as being unpatentable over
Alexander Papageorge et.al. (hereinafter George) US 10540604 B1,
in view of Yudong Cao et.al. (hereinafter Cao) US 20200104740 A1,
in view of Firas Hamze et.al. (hereinafter Hamze) US 2015/0269124 A1.
In regard to claim 1: (Currently Amended)
George discloses:
- An apparatus, comprising: a superconducting quantum processor that:
[Col 12, lines 64-67, Col 4, line 1])
In some aspects, by matching the qubit device form to function, a quantum computing apparatus can be constructed that can more efficiently use the various types of non-linear and linear quantum devices in a quantum computer
[Col 6, lines 1-3]:
In some cases, the quantum processor 102 includes a superconducting circuit, and the qubit devices are implemented as circuit devices,
[Col 4, lines 15-18]:
In some implementations, distinct clusters of qubits in an individual layer can be topologically connected in a tree structure topology irrespective of the physical placement of the qubit devices across and within the layer.
- delineates connections between superconducting qubits,
[Col 1, lines 43-58]:
In some aspects of what is described here, a quantum processor includes qubit devices arranged in a three-dimensional integrated multilayer architecture. The three-dimensional integration can include three-dimensional spatial connectivity between qubit devices distributed along three spatial dimensions,
In some cases, a three-dimensional integration of qubit devices permits or otherwise facilitates qubits to be arranged more densely (i.e., higher spatial density of qubits in the quantum processor) and with higher connectivity, which may lead to improved performance and other advantages,
in [Col 2, lines 6-28]:
In some cases, design and fabrication complexity for three-dimensional integration can be reduced by using an architecture that utilizes qubits and clusters of qubits in individual layers to indirectly couple with other qubits and clusters of qubits within the same individual layer. In some aspects, such an indirect coupling can be realized by coupling the qubits through intermediary connections (e.g., between resonators and ancilla qubits) in one or more other layers (e.g., utilizing the third dimension of the quantum processor). In some implementations, distinct clusters of qubits in an individual layer can be topologically connected in a tree structure topology irrespective of the physical placement of the qubit devices across and within the layer. Accordingly, the complexity of fabricating each successive layer can be reduced.
in [Col 6, lines 1-3]:
In some cases, the quantum processor 102 includes a superconducting circuit, and the qubit devices are implemented as circuit devices .
[BRI: the indirect coupling of qubits reduces the number of connections which leads to such connections less than the number of qubits].
George does not explicitly disclose:
- and enables execution of complex variational quantum eigensolver (VQE) algorithms
that are mapped onto sparsely-connected superconducting quantum processor architectures,
However, Cao discloses:
- and enables execution of complex variational quantum eigensolver (VQE) algorithms
that are mapped onto sparsely-connected superconducting quantum processor architectures,
[0047]:
One well-known technique within the field of quantum computing is the variational quantum eigensolver (VQE), which requires only shallow quantum circuits to prepare an ansatz state |ψ({right arrow over (θ)}) determined by classical parameters {right arrow over (θ)} in conjunction with a classical computer running black-box optimization to find the optimal {right arrow over (θ)}. A common application of VQE is to approximate the ground state of a given Hamiltonian.
[0048]:
Embodiments of the present invention use an approach that is analogous to VQE for linear systems or least-squares fitting, which is referred to herein as the variational quantum linear systems solver (VQLSS). The problem of solving linear systems entails finding a vector {right arrow over (x)} such that A{right arrow over (x)}={right arrow over (b)} for some matrix A and a vector {right arrow over (b)}.
[0093] :
certain descriptions of qubits herein may describe such qubits in terms of their mathematical properties, each such qubit may be implemented in a physical medium in any of a variety of different ways. Examples of such physical media include superconducting material, trapped ions, photons, optical cavities,
[0108]:
The qubits 104 may be interconnected in any graph pattern. For example, they be connected in a linear chain, a two-dimensional grid, an all-to-all connection, any combination thereof, or any subgraph of any of the preceding. [BRI: A qubit layout is sparse if the connectivity graph has relatively few edges compared to the total possible. If the graph is connected (so all qubits can be reached via some path), the circuit depth and size can still be bounded, but sparse topologies often require more SWAP or routing operations to move qubits into position for gate. qubits arranged in any of the graph patterns such as linear chain, 2D grid, or any subgraph of these — the sparsity depends on the actual number of edges in the graph relative to the total possible. For example, linear is sparse- only 2 edges, any subgraph- any combination of subsets creates a sparse connection, 2D grid—4 edges in the center, still far fewer than all possible. A shallow circuit on sparsely connected qubits together form a hardware-aware VQE strategy that balances expressibility, noise resilience, and hardware compatibility]
[0098]:
Quantum computers implemented using such quantum circuits are referred to herein as implementing “measurement feedback.” For example, a quantum computer implementing measurement feedback may execute the gates in a quantum circuit and then measure only a subset (i.e., fewer than all) of the qubits in the quantum computer, and then decide which gate(s) to execute next based on the outcome(s) of the measurement(s). [BRI: within the context of sparsely connected qubits, the execution of the subset of qubits represents the execution of sparse connected qubits]
[0022] :
In a second aspect, a hybrid quantum-classical computing system, for preparing a quantum state that approximates a solution x to a linear system of equations A{right arrow over (x)}={right arrow over (b)} for a matrix A and a vector {right arrow over (b)}, includes a quantum computing component having a plurality of qubits and a qubit controller that manipulates the plurality of qubits
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine George, and Cao.
George teaches superconducting quantum processor topology.
Cao teaches VQE and sparse connections of qubits.
One of ordinary skill would have motivation to combine George, and Cao optimize the estimation of an objective function within context of a hybrid quantum-classical system using a convergence criterion (Cao [0089]).
(Note: The examiner notes that Spec [0053] cites the concept of hybrid quantum-classical computing]
George and Cao do not explicitly disclose:
- wherein at least one of the sparsely-connected superconducting quantum processor architectures is an X-tree architecture and wherein the X-tree architecture is sparsely-connected based on the X-tree architecture having sparse qubit connections
- such that the X-tree architecture has a first number of qubit-to-qubit connections that is one less than a second number of the superconducting qubits.
However, Hamze discloses:
- wherein at least one of the sparsely-connected superconducting quantum processor architectures is an X-tree architecture and wherein the X-tree architecture is sparsely-connected based on the X-tree architecture having sparse qubit connections
[0016]:
Adiabatic quantum computation typically involves evolving a system from a known initial Hamiltonian (the Hamiltonian being an operator whose eigenvalues are the allowed energies of the system) to a final Hamiltonian by gradually changing the Hamiltonian. A simple example of an adiabatic evolution is a linear interpolation between initial Hamiltonian and final Hamiltonian.
[0018]:
Quantum annealing is a computation method that may be used to find a low-energy state, typically preferably the ground state, of a system.
[0018]:
adiabatic quantum computation may be considered a special case of quantum annealing [0018]:
Thus, those of skill in the art will appreciate that quantum annealing systems and methods may generally be implemented on an adiabatic quantum computer.
[0015]:
A quantum processor may take the form of a superconducting quantum processor. A superconducting quantum processor may include a number of qubits [0015]:
A superconducting quantum processor may also employ coupling devices (i.e., "couplers") providing communicative coupling between qubits.
[0198]:
An example of a tree is shown in FIG. 18. The root node of the tree is a placeholder with a null value. The non-terminal nodes of the tree are partial configurations of the variables for the objective function. The terminal nodes represent full configurations, or states, for the objective function. The edges between nodes represent probabilities. The probabilities are arranged such that the product of probabilities from a terminal node, also called a leaf node, to the root node is the probability of the state defined at the terminal node. The probability of a partial configuration is the product of the probabilities from the node representing the partial configuration to the root note. The probability of a partial configuration is a conditional probability.
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- such that the X-tree architecture has a first number of qubit-to-qubit connections that is one less than a second number of the superconducting qubits.
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[BRI: Fig 18 is an exemplary example of a X-tree. Perhaps well known to a POSITA, that in a tree structure, the number of edges is always one less than the number of nodes. In Fig 18, there are 15 nodes and 14 edges]
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine George, Cao and Hamze.
George teaches superconducting quantum processor topology.
Cao teaches VQE and sparse connections of qubits.
Hamze teaches X-tree representation in which each node is a qubit and each edge is connection between the related qubits.
One of ordinary skill would have motivation to combine George, , Cao and Hamze to improve the diversity and sparsity (Hamze [0293]).
In regard to claim 2: (Original)
George and Cao do not explicitly disclose:
- the superconducting qubits are represented in the X- tree architecture as at least one member selected from the group consisting of a root node and a leaf node.
However, Hamze discloses:
- the superconducting qubits are represented in the X- tree architecture as at least one member selected from the group consisting of a root node and a leaf node.
[0140]:
FIG. 9 is a block-diagram showing a process 900 for performing the above techniques on blocks of variables in a multiway recursion. Shown is an example of how to exploiting conditional independence to accelerate sampling on a grid of qubits or groups of qubits.
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(BRI: In Fig 18, root node shown at the level 1802 and leaf nodes shown at 1816 and 1818]
In regard to claim 13: (Currently Amended)
George discloses:
- to a superconducting quantum processor that includes qubit connectivity characterized by a multilevel hierarchical tree architecture, wherein the superconducting quantum processor comprises one or more quantum hardware devices that facilitate computational processing
[Col 12, lines 64-67, Col 4, line 1])
In some aspects, by matching the qubit device form to function, a quantum computing apparatus can be constructed that can more efficiently use the various types of non-linear and linear quantum devices in a quantum computer
[Col 6, lines 1-3]:
In some cases, the quantum processor 102 includes a superconducting circuit, and the qubit devices are implemented as circuit devices,
[Col 4, lines 15-18]:
In some implementations, distinct clusters of qubits in an individual layer can be topologically connected in a tree structure topology irrespective of the physical placement of the qubit devices across and within the layer.
[Col 11, lines 11-18]:
In some implementations, the control system 110 includes a classical computing system that executes software to compile instructions for the quantum processor 102. For example, the control system 110 may decompose a quantum logic circuit or quantum computing program into discrete control operations or sets of control operations that can be executed by the hardware in the quantum computing system 100.
- and generating, by the system, an initial hierarchical layout that assigns physical qubits of the superconducting quantum processor to logical qubits
in [Col 6, lines 1-3]:
In some cases, the quantum processor 102 includes a superconducting circuit, and the qubit devices are implemented as circuit devices”,
[Col 5, lines 35-37] :
In some implementations, the quantum processor 102 can operate using gate-based models for quantum computing. For example, the qubits can be initialized in an initial state, and a quantum logic circuit comprised of a series of quantum logic gates can be applied to transform the qubits and extract measurements representing the output of the quantum computation,
[Col 2, line 32-54]:
In some implementations, a tree representing the topological connections of the qubit devices can include clusters of child qubit devices connected to parent qubit devices, where each child qubit device in a cluster is connected to a common parent qubit device. The child qubit devices may be in the same physical layer of the quantum processor, or they may be distributed across multiple physical layers. The tree structure can include leaves representing quantum devices that are not parent qubit devices (and therefore do not have child qubit devices). In some implementations, each child qubit device representing a leaf in the tree structure can operate as an individual (e.g., single) qubit. Alternatively or additionally, multiple child qubit devices corresponding to leaves in the tree structure can operate collectively as a logical qubit. The operational qubits of a layer (e.g., the first layer) in a tree structure topology can be partially or fully coupled to one another through the mediation of ancilla qubit devices that can be in additional (e.g., second or higher) layers of the tree structure topology. In some cases, one or more child qubit devices can operate collectively with one or more ancilla qubit devices (which are above the child qubit devices in the tree structure topology) as a logical qubit. In some implementations, the three-dimensional topology can be described by a graph having the unit structure shown and described in connection with FIG. 2,
in [Col 5, lines 62-67] :
In some implementations, the quantum processor 102 includes devices in multiple physical layers, and connections between the devices that define a tree structure topology. For instance, the quantum processor 102 may be implemented and operated as shown and described with respect to FIGS. 2, 3 and 4, or otherwise,
[Col 2, lines 15-18]:
in some implementations, distinct clusters of qubits in an individual layer can be topologically connected in a tree structure topology irrespective of the physical placement of the qubit devices across and within the layer.
- on sparsely-connected superconducting quantum processor architectures.
[Col 6, lines 1-3]:
In some cases, the quantum processor 102 includes a superconducting circuit, and the qubit devices are implemented as circuit devices,
[Col 2, lines 6-10]:
In some cases, design and fabrication complexity for three-dimensional integration can be reduced by using an architecture that utilizes qubits and clusters of qubits in individual layers to indirectly couple with other qubits and clusters of qubits within the same individual layer
(BRI: A dimensional reduction integration is a “sparsely” connected)
George does not explicitly disclose:
- A computer-implemented method, comprising: mapping, by a system operatively coupled to a processor, a variational quantum eigensolver algorithm to a superconducting quantum processor
- logical qubits included in a plurality of Pauli strings employed by the variational quantum eigensolver algorithm.
- enabling, by the system, execution of complex variational quantum eigensolver (VQE) algorithms
However, Cao discloses:
- A computer-implemented method, comprising: mapping, by a system operatively coupled to a processor, a variational quantum eigensolver algorithm to a superconducting quantum processor
[0100]:
FIG. 2B shows a diagram illustrating operations typically performed by a computer system 250 which implements quantum annealing
[0101]:
the quantum computer 252 starts in the initial state 266, and evolves its state according to the annealing schedule 270 following the time-dependent Schrodinger equation, a natural quantum-mechanical evolution of physical systems
[0128]:
The techniques described above may be implemented in one or more computer programs executing on (or executable by) a programmable computer (such as a classical computer, a quantum computer, or an HQC computer system) including any combination of any number of the following: a processor, a storage medium readable and/or writable by the processor
[0047]:
One well-known technique within the field of quantum computing is the variational quantum eigensolver (VQE),
[0093]:
each such qubit may be implemented in a physical medium in any of a variety of different ways. Examples of such physical media include superconducting material
- logical qubits included in a plurality of Pauli strings employed by the variational quantum eigensolver algorithm.
[0047]:
One well-known technique within the field of quantum computing is the variational quantum eigensolver (VQE), which requires only shallow quantum circuits to prepare an ansatz state |ψ({right arrow over (θ)}) determined by classical parameters {right arrow over (θ)} in conjunction with a classical computer running black-box optimization to find the optimal {right arrow over (θ)}. A common application of VQE is to approximate the ground state of a given Hamiltonian.
[0048]:
Embodiments of the present invention use an approach that is analogous to VQE for linear systems or least-squares fitting, which is referred to herein as the variational quantum linear systems solver (VQLSS).
[0006] :
In a first aspect, a method for preparing a quantum state that approximates a solution x to a linear system of equations A{right arrow over (x)}={right arrow over (b)} for a matrix A and a vector {right arrow over (b)}
[0006]:
obtaining a measured sample, the measured sample being one of: (i) a bit-string of binary values obtained by measuring the plurality of qubits according to a Pauli string derived from the matrix A, and (ii) a measurement of overlap between the quantum state |ψ({right arrow over (θ)}) and a quantum b-state |b that encodes the vector {right arrow over (b)} on the quantum computer;
- enabling, by the system, execution of complex variational quantum eigensolver (VQE) algorithms
[0047]:
One well-known technique within the field of quantum computing is the variational quantum eigensolver (VQE), which requires only shallow quantum circuits to prepare an ansatz state |ψ({right arrow over (θ)}) determined by classical parameters {right arrow over (θ)} in conjunction with a classical computer running black-box optimization to find the optimal {right arrow over (θ)}. A common application of VQE is to approximate the ground state of a given Hamiltonian.
[0048]:
Embodiments of the present invention use an approach that is analogous to VQE for linear systems or least-squares fitting, which is referred to herein as the variational quantum linear systems solver (VQLSS). The problem of solving linear systems entails finding a vector {right arrow over (x)} such that A{right arrow over (x)}={right arrow over (b)} for some matrix A and a vector {right arrow over (b)}.
[0093] :
certain descriptions of qubits herein may describe such qubits in terms of their mathematical properties, each such qubit may be implemented in a physical medium in any of a variety of different ways. Examples of such physical media include superconducting material, trapped ions, photons, optical cavities,
[0108]:
The qubits 104 may be interconnected in any graph pattern. For example, they be connected in a linear chain, a two-dimensional grid, an all-to-all connection, any combination thereof, or any subgraph of any of the preceding. [BRI: A qubit layout is sparse if the connectivity graph has relatively few edges compared to the total possible. If the graph is connected (so all qubits can be reached via some path), the circuit depth and size can still be bounded, but sparse topologies often require more SWAP or routing operations to move qubits into position for gate. qubits arranged in any of the graph patterns such as linear chain, 2D grid, or any subgraph of these — the sparsity depends on the actual number of edges in the graph relative to the total possible. For example, linear is sparse- only 2 edges, any subgraph- any combination of subsets creates a sparse connection, 2D grid—4 edges in the center, still far fewer than all possible. A shallow circuit on sparsely connected qubits together form a hardware-aware VQE strategy that balances expressibility, noise resilience, and hardware compatibility]
[0098]:
Quantum computers implemented using such quantum circuits are referred to herein as implementing “measurement feedback.” For example, a quantum computer implementing measurement feedback may execute the gates in a quantum circuit and then measure only a subset (i.e., fewer than all) of the qubits in the quantum computer, and then decide which gate(s) to execute next based on the outcome(s) of the measurement(s). [BRI: within the context of sparsely connected qubits, the execution of the subset of qubits represents the execution of sparse connected qubits]
[0022] :
In a second aspect, a hybrid quantum-classical computing system, for preparing a quantum state that approximates a solution x to a linear system of equations A{right arrow over (x)}={right arrow over (b)} for a matrix A and a vector {right arrow over (b)}, includes a quantum computing component having a plurality of qubits and a qubit controller that manipulates the plurality of qubits
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine George, and Cao.
George teaches superconducting quantum processor topology.
Cao teaches VQE and sparse connections of qubits.
One of ordinary skill would have motivation to combine George, and Cao optimize the estimation of an objective function within context of a hybrid quantum-classical system using a convergence criterion (Cao [0089]).
George and Cao do not explicitly disclose:
- wherein a sparsely-connected superconducting quantum processor architecture of the sparsely-connected superconducting quantum processor architectures is sparsely-connected based on the multilevel hierarchical tree architecture
- having a first number of qubit-to-qubit connections that is one less than a second number of superconducting qubits.
However, Hamze discloses:
- wherein a sparsely-connected superconducting quantum processor architecture of the sparsely-connected superconducting quantum processor architectures is sparsely-connected based on the multilevel hierarchical tree architecture
[0016]:
Adiabatic quantum computation typically involves evolving a system from a known initial Hamiltonian (the Hamiltonian being an operator whose eigenvalues are the allowed energies of the system) to a final Hamiltonian by gradually changing the Hamiltonian. A simple example of an adiabatic evolution is a linear interpolation between initial Hamiltonian and final Hamiltonian.
[0018]:
Quantum annealing is a computation method that may be used to find a low-energy state, typically preferably the ground state, of a system.
[0018]:
adiabatic quantum computation may be considered a special case of quantum annealing [0018]:
Thus, those of skill in the art will appreciate that quantum annealing systems and methods may generally be implemented on an adiabatic quantum computer.
[0015]:
A quantum processor may take the form of a superconducting quantum processor. A superconducting quantum processor may include a number of qubits [0015]:
A superconducting quantum processor may also employ coupling devices (i.e., "couplers") providing communicative coupling between qubits.
[0198]:
An example of a tree is shown in FIG. 18. The root node of the tree is a placeholder with a null value. The non-terminal nodes of the tree are partial configurations of the variables for the objective function. The terminal nodes represent full configurations, or states, for the objective function. The edges between nodes represent probabilities. The probabilities are arranged such that the product of probabilities from a terminal node, also called a leaf node, to the root node is the probability of the state defined at the terminal node. The probability of a partial configuration is the product of the probabilities from the node representing the partial configuration to the root note. The probability of a partial configuration is a conditional probability.
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- having a first number of qubit-to-qubit connections that is one less than a second number of superconducting qubits.
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[BRI: Fig 18 is an exemplary example of a X-tree. Perhaps well known to a POSITA, that in a tree structure, the number of edges is always one less than the number of nodes. In Fig 18, there are 15 nodes and 14 edges]
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine George, Cao and Hamze.
George teaches superconducting quantum processor topology.
Cao teaches VQE and sparse connections of qubits.
Hamze teaches X-tree representation in which each node is a qubit and each edge is connection between the related qubits.
One of ordinary skill would have motivation to combine George, , Cao and Hamze to improve the diversity and sparsity (Hamze [0293]).
In regard to claim 17: (Previously Presented)
George discloses:
- a mapping component that determines how many of the quantum computations
employ a first logical qubit from the logical qubits, and how many of the quantum computations employ a second logical qubit from the logical qubits.
[Col 2, lines 41-43]:
multiple child qubit devices corresponding to leaves in the tree structure can operate
collectively as a logical qubit.
[Col 6, lines 34-45]:
The control signals can be configured to encode information in the qubit devices, to process the information by performing logical gates or other types of operations, or to extract information from the qubit devices. In some examples, the operations can be expressed as single-qubit gates, two-qubit gates, or other types of logical gates that operate on one or more qubits. A sequence of operations can be applied to the qubits to perform a quantum algorithm. The quantum algorithm may correspond to a computational task, a quantum error correction procedure, a quantum state distillation procedure, or a combination of these and other types of operations.
George does not explicitly disclose:
- wherein the variational quantum eigensolver algorithm defines quantum computations executable by the superconducting quantum processor, and wherein the system further comprising:
- wherein the execution of the variational eigensolver algorithm performs a chemistry simulation.
However, Cao discloses:
- wherein the variational quantum eigensolver algorithm defines quantum computations executable by the superconducting quantum processor, and wherein the system further comprising:
[0111]:
in embodiments in which some or all of the qubits 104 are implemented as superconducting circuits
[0047]:
One well-known technique within the field of quantum computing is the variational quantum eigensolver (VQE), which requires only shallow quantum circuits to prepare an ansatz state
[0101]:
Quantum annealing starts with the classical computer 254 generating an initial Hamiltonian 260 and a final Hamiltonian 262 based on a computational problem 258 to be solved, and providing the initial Hamiltonian 260, the final Hamiltonian 262 and an annealing schedule 270 as input to the quantum computer 252
- wherein the execution of the variational eigensolver algorithm performs a chemistry simulation.
[0090]:
Embodiments herein may be applied to problems in quantum chemistry, such as inverse iteration to approximate the ground state
|
g
of a quantum system of interest.
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine George, and Cao.
George teaches superconducting quantum processor topology.
Cao teaches VQE and sparse connections of qubits.
One of ordinary skill would have motivation to combine George, and Cao optimize the estimation of an objective function within context of a hybrid quantum-classical system using a convergence criterion (Cao [0089]).
In regard to claim 18: (Original)
George discloses:
- wherein the first logical qubit is mapped to a more central level of the multilevel hierarchical tree architecture than the second logical qubit in the initial hierarchical layout based on the first logical qubit being employed in more of the quantum computations than the second logical qubit.
in [Col 2, lines 35-46]:
the tree structure can include leaves representing quantum devices that are not parent qubit devices (and therefore do not have child qubit devices). In some implementations, each child qubit device representing a leaf in the tree structure can operate as an individual (e.g., single) qubit. Alternatively or additionally, multiple child qubit devices corresponding to leaves in the tree structure can operate collectively as a logical qubit,
in [Col 4, lines 4-7]:
In some implementations, the base layer (the first or lowest layer) of the tree structure topology can include computational qubits, while the higher layers (second layer and greater) of the tree structure can include ancilla qubits.
In regard to claim 19: (Original)
George discloses:
- synthesizing, by the system, a quantum circuit
[Col 7, line 11-17]:
In some implementations, the control system 110 includes a classical computing system that executes software to compile instructions for the quantum processor 102. For example, the control system 110 may decompose a quantum logic circuit or quantum computing program into discrete control operations or sets of control operations that can be executed by the hardware in the quantum computing system 100.
- wherein the synthesis component selects a qubit connection between the logical qubits based on an effect of a previously selected qubit connection on a mapping of the physical qubits with the logical qubits;
[Col 13, lines 61-67, Col 14, lines 1-3]:
A quantum control sequence is applied to at least one of the plurality of devices to transform the computational state in the quantum processor. Applying the quantum control sequence includes using one or more parent qubit devices in a second layer of the tree structure topology to mediate between child qubit devices (e.g., between pairs of qubit devices or between larger clusters of qubit devices) in the first layer of the tree structure topology. A readout of the transformed computational state is performed.
[Col 14, lines 8-11]:
At least one of the logical qubits may be defined by multiple child qubit devices. At least one of the logical qubits may be defined by at least one child qubit device and at least one parent qubit device”,
[Col 14, lines 29-31]:
Applying the quantum control sequence may include transferring one or more qubit states between devices in different layers of the tree structure topology,
[Col 2, lines 29-35]:
In some implementations, a tree representing the topological connections of the qubit devices can include clusters of child qubit devices connected to parent qubit devices, where each child qubit device in a cluster is connected to a common parent qubit device. The child qubit devices may be in the same physical layer of the quantum processor, or they may be distributed across multiple physical layers.
- and a routing component that alters a position of a logical qubit on the multilevel hierarchical tree architecture based on the qubit connection.
[Col 3, lines 2-18]:
In some implementations, the qubit devices in the first (lowest) layer of the tree structure are coupled (e.g., capacitively, inductively, or galvanically coupled) to qubit devices in the second layer. For example, the qubit devices in the second layer can include tunable-frequency transmon qubit devices, and the qubit devices in the first layer can be coupled to a resonator bus in the second layer, with the resonator bus coupled to a tunable-frequency transmon qubit device in the second layer. The resonator bus can be implemented by a circuit device or other physical structure that can support a collection of resonant modes. For instance, the resonator bus may include an array of resonator devices, an array of inductor and capacitor structures, one or more multimode resonators that can carry multiple frequencies, or other types of elements.
[Col 1, lines 59-67, Col 2 lines 1-4]:
In some implementations, a three-dimensional integration can enable more efficient interconnect routing to large arrays of qubits, e.g., in a given layer of a quantum processor. This can allow for denser qubit-qubit coupling geometries and increased connectivity between qubits, including increased connectivity beyond nearest-neighbor interactions,
[Col 2, lines 35-47]:
The tree structure can include leaves representing quantum devices that are not parent qubit devices (and therefore do not have child qubit devices). In some implementations, each child qubit device representing a leaf in the tree structure can operate as an individual (e.g., single) qubit. Alternatively or additionally, multiple child qubit devices corresponding to leaves in the tree structure can operate collectively as a logical qubit. The operational qubits of a layer (e.g., the first layer) in a tree structure topology can be partially or fully coupled to one another through the mediation of ancilla qubit devices that can be in additional (e.g., second or higher) layers of the tree structure topology,
[Col 4, lines 45-67]:
In some implementations, a quantum processor does not provide direct coupling between qubit devices within the first (lowest) layer of the three-dimensional device topology. For example, the qubit devices in the first layer can be coupled to each other indirectly, through devices (e.g., other qubit devices) in one or more other layers (above the first layer). In some implementations, the quantum processor does provide direct coupling between qubit devices within the first layer. For example, the qubit devices within one or more layers may be organized in clusters, with direct connections between pairs of qubit devices within each cluster. Distinct clusters within a layer may be connected indirectly through devices in one or more other layers. For example, in some cases the first layer does not provide direct coupling between qubit devices of different clusters, and a given qubit device in a first cluster in a first layer can be coupled to a qubit device in a second cluster in the first layer by coupling to one or more qubit devices in a second, higher layer, which can mediate the interaction between clusters. In some implementations, there may be any integer number of clusters on the first layer or subsequent layers of the quantum processor employing such a tree-like multilayer configuration of devices.
George does not explicitly disclose:
- expresses a Pauli string from the plurality of Pauli strings through a series of qubit connection selections,
However, Cao discloses:
- expresses a Pauli string from the plurality of Pauli strings through a series of qubit connection selections
[0056]:
Each of the component matrices A.sub.1 . . . A.sub.k in the linear combination is expressible as a tensor product of Pauli matrices:
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where each single-qubit operator σ.sup.(x) is either a Pauli matrix acting on one qubit in the direction d (i.e., the x, y, or z direction) or the identity matrix acting only on the one qubit (i.e., the two-dimensional subspace spanned by the one qubit).
[0056]:
Each term of the summand in Eqn. 3 may be referred to herein as a “Pauli string”, i.e., a tensor-product of n single-qubit Pauli operators corresponding to the n qubits on which the corresponding component matrix A.sub.i operates.
In regard to claim 20: (Original)
George discloses:
- synthesizing the quantum circuit and executing the altering the position of the logical qubit are performed in conjunction with each other.
[Col 7, lines 11-17]:
In some implementations, the control system 110 includes a classical computing system that executes software to compile instructions for the quantum processor 102. For example, the control system 110 may decompose a quantum logic circuit or quantum computing program into discrete control operations or sets of control operations that can be executed by the hardware in the quantum computing system 100.
[Col 5, lines 17-24]:
Control signals can manipulate the quantum states of individual qubits and the joint states of multiple qubits. In some instances, conditional quantum logic can be performed in a manner that allows large-scale entanglement within the quantum processor 102. In some instances, information can be read out from the composite quantum system by measuring the quantum states of the individual qubits.
[Col 2, lines 41-43]:
multiple child qubit devices corresponding to leaves in the tree structure can operate
collectively as a logical qubit.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over
Alexander Papageorge et.al. (hereinafter George) US 10540604 B1,
in view of Yudong Cao et.al. (hereinafter Cao) US 20200104740 A1,
in view of Firas Hamze et.al. (hereinafter Hamze) US 20150269124 A1.
further in view of Stefan Berchtold et.al. (hereinafter Berch) The X-tree: An Index Structure for High-Dimensional Data, Proceeding of the Twenty-second International Conference on Very Large Data-Bases, Morgan Kaufmann, 1996, S.28-39.
In regard to claim 15 : (Previously Presented)
George, Cao and Hamze do not explicitly disclose:
- the multilevel hierarchical tree architecture includes a root node connected to a leaf node across different levels, wherein the root node is connected to multiple leaf nodes.
However, Berch discloses:
- the multilevel hierarchical tree architecture includes a root node connected to a leaf node across different levels, wherein the root node is connected to multiple leaf nodes.
[3, Page 31]:
The X-tree The X-tree (eXtended node tree) is a new index structure supporting efficient query processing of high-dimensional data. The goal is to support not only point data but also extended spatial data and therefore, the X-tree uses the concept of overlapping regions. From the insight obtained in the previous section, it is clear that we have to avoid overlap in the directory in order to improve the indexing of high-dimensional data
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[BRI: the root node at level 1 and leaf nodes are level 4 in a X-tree with 4 levels in Fig 5]
In regard to claim 16: (Previously Presented)
George, Cao and Hamze do not explicitly disclose:
- wherein the multilevel hierarchical tree is an X-tree architecture.
However, Berch discloses:
- the multilevel hierarchical tree architecture includes a root node connected to a leaf node across different levels, wherein the root node is connected to multiple leaf nodes.
[3, Page 31]:
The X-tree The X-tree (eXtended node tree) is a new index structure supporting efficient query processing of high-dimensional data. The goal is to support not only point data but also extended spatial data and therefore, the X-tree uses the concept of overlapping regions. From the insight obtained in the previous section, it is clear that we have to avoid overlap in the directory in order to improve the indexing of high-dimensional data
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[BRI: the X-tree of Fig 5 is a multi-hierarchical tree]
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over
Alexander Papageorge et.al. (hereinafter George) US 10540604 B1,
in view of Alexander Cowtan et.al. (hereinafter Cowtan) US 2021/0319159 A1,
in view of Jianxin Chen et.al. (hereinafter Chen) US 11049038 B2.
In regard to claim 5: (Currently Amended)
George discloses:
- to a superconducting quantum processor that includes qubit connectivity characterized by a multilevel hierarchical tree architecture, wherein the superconducting quantum processor comprises one or more quantum hardware devices that facilitate computational processing;
[Col 7, lines 11-18]:
In some implementations, the control system 110 includes a classical computing system that executes software to compile instructions for the quantum processor 102. For example, the control system 110 may decompose a quantum logic circuit or quantum computing program into discrete control operations or sets of control operations that can be executed by the hardware in the quantum computing system 100.
[Col 5, lines 1-4]:
FIG. 1 is a schematic diagram of an example quantum computing system 100. The example quantum computing system 100 shown in FIG. 1 includes a control system 110, a signal delivery system 106, and a quantum processor 102,
[Col 5, lines 62-64]:
In some implementations, the quantum processor 102 includes devices in multiple physical layers, and connections between the devices that define a tree structure topology,
[Col 6, lines 1-5]:
the quantum processor 102 includes a superconducting circuit, and the qubit devices are implemented as circuit devices that include Josephson junctions, for example, in superconducting quantum interference device (SQUID) loops or other arrangements
In [Col 2, lines 6-15]:
In some cases, design and fabrication complexity for three-dimensional integration can be reduced by using an architecture that utilizes qubits and clusters of qubits in individual layers to indirectly couple with other qubits and clusters of qubits within the same individual layer. In some aspects, such an indirect coupling can be realized by coupling the qubits through intermediary connections (e.g., between resonators and ancilla qubits) in one or more other layers (e.g., utilizing the third dimension of the quantum processor).
[Col 2, lines 21-28]:
a tree structure topology may permit a scalable way for two-dimensional arrays of qubit devices in an individual physical layer to be fully coupled to one another (e.g., using ancilla qubit devices in other physical layers). In some cases, the number of ancilla qubit devices in each layer of the tree structure topology is a logarithmic function of the number of qubit devices in the first layer of the tree structure topology (e.g., the number of leafs in the tree structure).
- a layout component that generates an initial hierarchical layout that maps physical qubits of the superconducting quantum processor with logical qubits
[Col 5, lines 35-37]:
In some implementations, the quantum processor 102 can operate using gate-based models for quantum computing. For example, the qubits can be initialized in an initial state, and a quantum logic circuit comprised of a series of quantum logic gates can be applied to transform the qubits and extract measurements representing the output of the quantum computation
[Col 6, lines 1-5]:
the quantum processor 102 includes a superconducting circuit, and the qubit devices are implemented as circuit devices that include Josephson junctions, for example, in superconducting quantum interference device (SQUID) loops or other arrangements
[Col 2, lines 6-15]:
In some cases, design and fabrication complexity for three-dimensional integration can be reduced by using an architecture that utilizes qubits and clusters of qubits in individual layers to indirectly couple with other qubits and clusters of qubits within the same individual layer. In some aspects, such an indirect coupling can be realized by coupling the qubits through intermediary connections (e.g., between resonators and ancilla qubits) in one or more other layers (e.g., utilizing the third dimension of the quantum processor).
in [Col 2, line 32-54]:
In some implementations, a tree representing the topological connections of the qubit devices can include clusters of child qubit devices connected to parent qubit devices, where each child qubit device in a cluster is connected to a common parent qubit device. The child qubit devices may be in the same physical layer of the quantum processor, or they may be distributed across multiple physical layers. The tree structure can include leaves representing quantum devices that are not parent qubit devices (and therefore do not have child qubit devices). In some implementations, each child qubit device representing a leaf in the tree structure can operate as an individual (e.g., single) qubit. Alternatively or additionally, multiple child qubit devices corresponding to leaves in the tree structure can operate collectively as a logical qubit. The operational qubits of a layer (e.g., the first layer) in a tree structure topology can be partially or fully coupled to one another through the mediation of ancilla qubit devices that can be in additional (e.g., second or higher) layers of the tree structure topology. In some cases, one or more child qubit devices can operate collectively with one or more ancilla qubit devices (which are above the child qubit devices in the tree structure topology) as a logical qubit. In some implementations, the three-dimensional topology can be described by a graph having the unit structure shown and described in connection with FIG. 2,
[Col 5, lines 62-67]:
In some implementations, the quantum processor 102 includes devices in multiple physical layers, and connections between the devices that define a tree structure topology. For instance, the quantum processor 102 may be implemented and operated as shown and described with respect to FIGS. 2, 3 and 4, or otherwise.
[Col 2, lines 15-18]:
In some implementations, distinct clusters of qubits in an individual layer can be topologically connected in a tree structure topology irrespective of the physical placement of the qubit devices across and within the layer.
- and a routing component that alters a position of a logical qubit of the logical qubits on a multilevel hierarchical tree architecture based on a qubit connection,
[Col 1, lines 59-67, Col 2 lines 1-4]:
In some implementations, a three-dimensional integration can enable more efficient interconnect routing to large arrays of qubits, e.g., in a given layer of a quantum processor. This can allow for denser qubit-qubit coupling geometries and increased connectivity between qubits, including increased connectivity beyond nearest-neighbor interactions,
[Col 2, lines 35-47]:
The tree structure can include leaves representing quantum devices that are not parent qubit devices (and therefore do not have child qubit devices). In some implementations, each child qubit device representing a leaf in the tree structure can operate as an individual (e.g., single) qubit. Alternatively or additionally, multiple child qubit devices corresponding to leaves in the tree structure can operate collectively as a logical qubit. The operational qubits of a layer (e.g., the first layer) in a tree structure topology can be partially or fully coupled to one another through the mediation of ancilla qubit devices that can be in additional (e.g., second or higher) layers of the tree structure topology,
- wherein the routing component executes one or more routing operations that define a relocation of one or more logical qubits from one node of the multilevel hierarchical tree architecture to another node, thereby moving the one or more logical qubits to one or more nodes and thereby physical qubit assignments capable of establishing the selected qubit connection based on the qubit connection selections
[Col 5, lines 40-53]:
quantum error correcting schemes can be deployed to achieve fault-tolerant quantum computation, or other computational regimes may be used. Pairs of qubits can be addressed, for example, with two-qubit logic operations that are capable of generating entanglement, independent of other pairs of qubits. In some implementations, more than two qubits can be addressed, for example, with multi-qubit quantum logic operations capable of generating multi-qubit entanglement. In some implementations, the quantum processor 102 is constructed and operated according to a scalable quantum computing architecture. For example, in some cases, the architecture can be scaled to a large number of qubits to achieve large-scale general purpose coherent quantum computing
[Col 8, lines 16-24]:
The example three-dimensional device topology shown in FIG. 2 includes devices that can be deployed in multiple physical layers of a quantum processor (e.g., qubit devices, readout devices, etc.). The example three-dimensional device topology shown in FIG. 2 includes connections that interconnect the devices in a tree structure topology, which includes child devices (in a first layer 202 of the tree structure topology) and parent devices (e.g., in a second layer 203 of the tree structure topology).
[Col 3, lines 47-62]:
In some implementations, a tree structure device topology, which can include qubit devices in multiple layers and connections between the qubit devices in the different layers, can provide connectivity between all pairs of qubit devices, and the path length between pairs of qubit devices can scale with the logarithm of the number of qubits in the quantum processor. Moreover, a tree structure device topology may provide a scalable solution to increasing the connectivity between qubit devices in a single layer. For example, a branching factor of two successive layers associated with the tree structure of the qubits can determine the degree of logarithmic scaling in connecting any arbitrary pair of qubits. In some aspects, the branching factor (which characterizes the number of children for each parent) between adjacent layers can be selected to minimize communication bottlenecks
[Col 10, lines 15-17]:
In some aspects of operation, qubit states defined in distinct clusters in the first layer 202 can be coupled by using hardware provided in the second layer 203.
[Col 10, lines 43-47]:
The operations may be performed in another manner, for example, in parallel, in another order, or in conjunction with other operations. Similar processes can be followed between any pair of individual qubit devices in distinct clusters.
(BRI: coherent quantum computing provides a way to relocate physical qubits by moving their quantum states without physically moving the qubits themselves allowing for better qubit connectivity, and increased scalability in large-scale quantum processors).
George does not explicitly disclose:
- A system, comprising: a memory that stores computer executable components; and a processor, operably coupled to the memory, and that executes the computer executable components stored in the memory, wherein the computer executable components comprise:
- a compiler component that maps a variational quantum eigensolver algorithm
However, Cowtan discloses:
- A system, comprising: a memory that stores computer executable components; and a processor, operably coupled to the memory, and that executes the computer executable components stored in the memory, wherein the computer executable components comprise:
[0010]:
Also described is a system and a method for generating a quantum circuit, in which a computer-implemented method comprises generating a quantum circuit
[0110]:
The computing system includes a quantum computer 250 and a classical (non-quantum computer) 210. Note that for clarity, the standard internal hardware and software components of classical computer 210, such as a processor, memory, storage, input/output, communications, operating system and so on that are not directly relevant to an understanding of the approach described herein are omitted from FIG. 11.
[0113 ]:
system and method are disclosed for providing a quantum circuit. The method is typically implemented by running compiler 220, whereby the compiler is a computer program comprising program instructions that when executed on a computing device causes the computing device to perform such a method. The compiler may be provided on a suitable storage medium such as described below for loading into the memory for execution by a processor.
- a compiler component that maps a variational quantum eigensolver algorithm
[0019]:
In accordance with a still further aspect of the concepts, systems and techniques described herein, a method for running a Variational Quantum Eigensolver (VQE) as a hybrid quantum-classical algorithm to approximate the ground state of some Hamiltonian includes using a subroutine performed on a quantum computer insider a larger optimization routine performed on a classical computer,
[0112]:
The VQE performs an iterative optimisation in which certain functionality within the iterative procedure is off-loaded from the classical computer 220 onto the quantum
- logical qubits included in a plurality of Pauli strings employed by the variational quantum eigensolver algorithm
[0097]:
recent work has explored the possibility of resynthesising a circuit in a topologically aware manner for limited gate sets [23, 33, 39]. This constrained synthesis has been found to typically produce lower ΛX counts than SWAP networks, and phase polynomials are a viable class of circuit for constrained synthesis
[0097]:
If topologically constrained phase polynomials can be composed with Clifford regions in a manner that respects architecture, this would appear to be a promising strategy for those devices with limited connectivity.
[0016]:
In embodiments, the diagonalisation may be performed by finding the Pauli string with the lowest weight; conjugating the corresponding Pauli gadget with a single-qubit Clifford gate and entangling gates; and commuting the Clifford gates through the rest of the Pauli gadgets until all the Clifford gates are outside the adjacent Pauli gadgets
[0016 ]:
the method may further comprise performing Clifford peephole optimisation by finding patterns of two-qubit Clifford circuits and replacing them with equivalent circuits with lower counts of entangling gates.
(BRI: It is known in the art that entangling gates type of quantum logic gate that manipulates qubits to create entanglement, a key resource in quantum computing)
[0019] :
In accordance with a still further aspect of the concepts, systems and techniques described herein, a method for running a Variational Quantum Eigensolver (VQE) as a hybrid quantum-classical algorithm to approximate the ground state of some Hamiltonian includes using a subroutine performed on a quantum computer insider a larger optimization routine performed on a classical computer, wherein the subroutine utilises a quantum circuit formed by diagonalising sets of Pauli gadgets to convert the Pauli gadgets into phase gadgets and transforming the phase gadgets into one- and two-qubit gates.
[0016]:
The present invention includes a method for extracting knowledge from information, comprising: transforming the information into one or more homoiconic, reflective, directed acyclic graphs, wherein the information comprises data and executable instructions
[0010]:
The instant disclosure provides a method and system for a homoiconic, and reflective, framework in the form of an executable graph (sometimes referred to as an “xGraph”). The present invention can be used as a foundation for a variety of applications. The concept of homoiconicity refers to the property that a program structure is similar to its data structure and is comprised of executable program code and data that co-exist. The invention includes a homoiconic structure wherein the data and executable aspects co-exist in a single framework. In this model, the data is the program and the program is the data. This allows the code to be accessed and transformed as data, using the same representation as the underlying data.
[0044] :
Such a system is termed “homoiconic” because the framework is both the process as well as the semantic content embodied in a single framework.
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine George, and Cowtan.
George teaches superconducting quantum processor as multi-level tree architecture.
Cowtan teaches compiler component.
One of ordinary skill would have motivation to combine George, and Cowtan to optimize for convergence towards ground state using hybrid quantum-classical algorithms (Cowtan [0019])
George and Cowtan do not explicitly disclose:
- wherein the system employs high-level domain knowledge and program semantics
- physical qubit assignments capable of establishing the selected qubit connection based on the qubit connection selections;
- and a synthesis component that adaptively synthesizes each quantum circuit according to an evolving logical-to-physical qubit mapping, wherein the synthesizing the quantum circuit and altering the position of the logical qubit are performed in conjunction with each other.
However, Chen discloses:
- wherein the system employs high-level domain knowledge and program semantics
[Col 4, lines 48-57]:
Once a computer is physically implemented, it is essentially idle until it is given something to “calculate.” In other words, a computer does nothing until instructed otherwise. Thus, to have a computer solve a task, the computer must be then provided with a set of instructions to follow which, when followed, accomplish the desired task. This set of instructions is called a program, which, collectively constitute software. In turn, the ability to create a program to solve a task is largely constrained by two domains: mathematical algorithms and the knowledge of how a given task is solved.
[Col 5, lines 2-3]:
Without this knowledge, the program solving a given task cannot be created. [ BRI:the set of instructions solving a task is constrained by both mathematical algorithms and task-specific knowledge. When a system uses high-level domain knowledge and program semantics, it ensures that the algorithmic structure is both formally sound and meaningfully applicable to the problem domain
- and a synthesis component that adaptively synthesizes each quantum circuit according to an evolving logical-to-physical qubit mapping, wherein the synthesizing the quantum circuit
[Col 7, lines 17-20]:
Operations are performed on qubits using quantum logic gates, which take one or more qubits as input and gives one or more qubits as output.
[Col 27, lines 45-48]:
Some embodiments may modulate their optimizations for increased efficiency (e.g., reducing the initial quantum circuit's T-count) with limitations imposed by the target quantum hardware the quantum circuit may be implemented on.
[BRI: taking one or more qubits as input and producing one or more qubits as output does represent the synthesis of a quantum circuit according to an evolving logical-to-physical qubit mapping, provided the synthesis process explicitly adapts the mapping during execution to match the physical hardware’s constraints and capabilities and the constraints for the target hardware is provided]
[Col 7, lines 64-65]:
while powerful, maintaining the qubits in a necessary state (e.g., entangled with other qubits)
[Col 8, lines 7-13]:
To help combat the fragility of the necessary quantum states, many quantum computer systems implement a form of fault tolerance. The primary form of fault tolerance used is to create a “logical qubit,” which is made up of several redundant physical qubits and, as a consequence, is more robust.
- and altering the position of the logical qubit are performed in conjunction with each other.
[Col 25, lines 27-40]:
Additionally, some embodiments may optimize a quantum circuit in place, whereas other embodiments may use auxiliary quantum circuits as part of the optimization process. For example, in some embodiments, transforming an initial quantum circuit into an intermediate quantum circuit may involve altering the initial quantum circuit into the intermediate quantum circuit (e.g., overwriting the representation of the initial quantum circuit into the intermediate quantum circuit). In contrast, in some embodiments, transforming an initial quantum circuit into an intermediate quantum circuit may involve generating a new quantum circuit which is then transformed into the intermediate quantum circuit (e.g., by using the initial quantum circuit as a template).
[Col 27, lines 45-48]:
Some embodiments may modulate their optimizations for increased efficiency (e.g., reducing the initial quantum circuit's T-count) with limitations imposed by the target quantum hardware the quantum circuit may be implemented on. [BRI: in many quantum circuit optimization pipelines, the intermediate transformation step can involve logical qubit position altering if it changes the mapping between logical qubits and physical qubits. This is a deliberate part of compilation to improve hardware compatibility and performance, and it is well-supported by modern quantum compiler and ML-based optimization techniques]
Does Operations are performed on qubits using quantum logic gates, which take one or more qubits as input and gives one or more qubits as output and taking into account specific hardware constraints of targeted hardware when optimizing and altering the initial quantum circuit into the intermediate quantum circuit represents evolving logical-to-physical qubit mapping, wherein the synthesizing the quantum circuit and altering the position of the logical qubit are performed in conjunction with each other]
It would have obvious to one of ordinary skill in the art before the effective filing date of
the present application to combine George, Cowtan and Chen.
George teaches multi-level hierarchical tree architecture,
Cowtan teaches quantum compilers.
Chen teaches synthesis that adapts to logical to physical qubit mapping.
One of ordinary skill would have motivation to combine George, Cowtan and Chen that can use reduced qubits to reduce cost and further improve performance on the hardware (Chen [Col 27, lines 54-55]).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over
Alexander Papageorge et.al. (hereinafter George) US 10540604 B1,
in view of Alexander Cowtan et.al. (hereinafter Cowtan) US 2021/0319159 A1,
in view of Jianxin Chen et.al. (hereinafter Chen) US 11049038 B2.
further in view of Stefan Berchtold et.al. (hereinafter Berch) The X-tree: An Index Structure for High-Dimensional Data, Proceeding of the Twenty-second International Conference on Very Large Data-Bases, Morgan Kaufmann, 1996, S.28-39.
In regard to claim 7 : (Previously Presented)
George, Cowtan and Chen do not explicitly disclose:
- the multilevel hierarchical tree architecture includes a root node connected to a leaf node across different levels, wherein the root node is connected to multiple leaf nodes.
However, Berch discloses:
- the multilevel hierarchical tree architecture includes a root node connected to a leaf node across different levels, wherein the root node is connected to multiple leaf nodes.
[3, Page 31]:
The X-tree The X-tree (eXtended node tree) is a new index structure supporting efficient query processing of high-dimensional data. The goal is to support not only point data but also extended spatial data and therefore, the X-tree uses the concept of overlapping regions. From the insight obtained in the previous section, it is clear that we have to avoid overlap in the directory in order to improve the indexing of high-dimensional data
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[BRI: the root node at level 1 and leaf nodes are level 4 in a X-tree with 4 levels in Fig 5]
It would have obvious to one of ordinary skill in the art before the effective filing date of
the present application to combine George, Cowtan, Chen and Berch.
George teaches multi-level hierarchical tree architecture,
Cowtan teaches quantum compilers.
Chen teaches synthesis that adapts to logical to physical qubit mapping.
Berch teaches x-tree.
One of ordinary skill would have motivation to combine George, Cowtan, Chen and Berch that can use reduced qubits to reduce cost and further improve performance on the hardware (Chen [Col 27, lines 54-55]).
In regard to claim 8: (Previously Presented)
George, Cowtan and Chen do not explicitly disclose:
- wherein the multilevel hierarchical tree is an X-tree architecture.
However, Berch discloses:
- wherein the multilevel hierarchical tree is an X-tree architecture.
[3, Page 31]:
The X-tree The X-tree (eXtended node tree) is a new index structure supporting efficient query processing of high-dimensional data. The goal is to support not only point data but also extended spatial data and therefore, the X-tree uses the concept of overlapping regions. From the insight obtained in the previous section, it is clear that we have to avoid overlap in the directory in order to improve the indexing of high-dimensional data
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243
398
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[BRI: the X-tree of Fig 5 is a multi-hierarchical tree]
It would have obvious to one of ordinary skill in the art before the effective filing date of
the present application to combine George, Cowtan, Chen and Berch.
George teaches multi-level hierarchical tree architecture,
Cowtan teaches quantum compilers.
Chen teaches synthesis that adapts to logical to physical qubit mapping.
Berch teaches x-tree.
One of ordinary skill would have motivation to combine George, Cowtan, Chen and Berch that can use reduced qubits to reduce cost and further improve performance on the hardware (Chen [Col 27, lines 54-55]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over
Alexander Papageorge et.al. (hereinafter George) US 10540604 B1,
in view of Alexander Cowtan et.al. (hereinafter Cowtan) US 2021/0319159 A1,
in view of Jianxin Chen et.al. (hereinafter Chen) US 11049038 B2.
further in view of Yudong Cao et.al. (hereinafter Cao) US 20200104740 A1,
In regard to claim 9: (Previously Presented)
George discloses:
- a mapping component that determines how many of the quantum computations
employ a first logical qubit from the logical qubits, and how many of the quantum computations employ a second logical qubit from the logical qubits.
[Col 2, lines 41-43]:
multiple child qubit devices corresponding to leaves in the tree structure can operate
collectively as a logical qubit.
[Col 6, lines 34-45]:
The control signals can be configured to encode information in the qubit devices, to process the information by performing logical gates or other types of operations, or to extract information from the qubit devices. In some examples, the operations can be expressed as single-qubit gates, two-qubit gates, or other types of logical gates that operate on one or more qubits. A sequence of operations can be applied to the qubits to perform a quantum algorithm. The quantum algorithm may correspond to a computational task, a quantum error correction procedure, a quantum state distillation procedure, or a combination of these and other types of operations.
George does not explicitly disclose:
- wherein the variational quantum eigensolver algorithm defines quantum computations executable by the superconducting quantum processor, and wherein the system further comprising:
- wherein the execution of the variational eigensolver algorithm performs a chemistry simulation.
However, Cao discloses:
- wherein the variational quantum eigensolver algorithm defines quantum computations executable by the superconducting quantum processor, and wherein the system further comprising:
[0111]:
in embodiments in which some or all of the qubits 104 are implemented as superconducting circuits
[0047]:
One well-known technique within the field of quantum computing is the variational quantum eigensolver (VQE), which requires only shallow quantum circuits to prepare an ansatz state
[0101]:
Quantum annealing starts with the classical computer 254 generating an initial Hamiltonian 260 and a final Hamiltonian 262 based on a computational problem 258 to be solved, and providing the initial Hamiltonian 260, the final Hamiltonian 262 and an annealing schedule 270 as input to the quantum computer 252
- wherein the execution of the variational eigensolver algorithm performs a chemistry simulation.
[0090]:
Embodiments herein may be applied to problems in quantum chemistry, such as inverse iteration to approximate the ground state
|
g
of a quantum system of interest.
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine George, Cowtan, Chen and Cao.
George teaches multi-level hierarchical tree architecture,
Cowtan teaches quantum compilers.
Chen teaches synthesis that adapts to logical to physical qubit mapping.
Cao teaches VQE and sparse connections of qubits.
One of ordinary skill would have motivation to combine George, Cowtan, Chen and Cao optimize the estimation of an objective function within context of a hybrid quantum-classical system using a convergence criterion (Cao [0089]).
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over
Alexander Papageorge et.al. (hereinafter George) US 10540604 B1,
in view of Alexander Cowtan et.al. (hereinafter Cowtan) US 2021/0319159 A1.
in view of Jianxin Chen et.al. (hereinafter Chen) US 11049038 B2.
further in view of Yudong Cao et.al. (hereinafter Cao) US 20200104740 A1,
further in view of in view of Firas Hamze et.al. (hereinafter Hamze) US 20150269124 A1.
In regard to claim 10: (Original)
George discloses:
- wherein the first logical qubit is mapped to a more central level of the multilevel hierarchical tree architecture than the second logical qubit in the initial hierarchical layout based on the first logical qubit being employed in more of the quantum computations than the second logical qubit.
[Col 2, lines 35-46]:
the tree structure can include leaves representing quantum devices that are not parent qubit devices (and therefore do not have child qubit devices). In some implementations, each child qubit device representing a leaf in the tree structure can operate as an individual (e.g., single) qubit. Alternatively or additionally, multiple child qubit devices corresponding to leaves in the tree structure can operate collectively as a logical qubit,
[Col 4, lines 4-7]:
In some implementations, the base layer (the first or lowest layer) of the tree structure topology can include computational qubits, while the higher layers (second layer and greater) of the tree structure can include ancilla qubits.
In regard to claim 11: (Currently Amended)
George discloses:
- wherein [[a]] synthesis component that synthesizes a quantum circuit
[Col 7, line 11-17]:
In some implementations, the control system 110 includes a classical computing system that executes software to compile instructions for the quantum processor 102. For example, the control system 110 may decompose a quantum logic circuit or quantum computing program into discrete control operations or sets of control operations that can be executed by the hardware in the quantum computing system 100.
- wherein the synthesis component selects a qubit connection between the logical qubits based on an effect of a previously selected qubit connection on a mapping of the physical qubits with the logical qubits;
[Col 13, lines 61-67, Col 14, lines 1-3]:
A quantum control sequence is applied to at least one of the plurality of devices to transform the computational state in the quantum processor. Applying the quantum control sequence includes using one or more parent qubit devices in a second layer of the tree structure topology to mediate between child qubit devices (e.g., between pairs of qubit devices or between larger clusters of qubit devices) in the first layer of the tree structure topology. A readout of the transformed computational state is performed.
[Col 14, lines 8-11]:
At least one of the logical qubits may be defined by multiple child qubit devices. At least one of the logical qubits may be defined by at least one child qubit device and at least one parent qubit device”,
[Col 14, lines 29-31]:
Applying the quantum control sequence may include transferring one or more qubit states between devices in different layers of the tree structure topology,
[Col 2, lines 29-35]:
In some implementations, a tree representing the topological connections of the qubit devices can include clusters of child qubit devices connected to parent qubit devices, where each child qubit device in a cluster is connected to a common parent qubit device. The child qubit devices may be in the same physical layer of the quantum processor, or they may be distributed across multiple physical layers.
George does not explicitly disclose:
- expresses a Pauli string from the plurality of Pauli strings through a series of qubit connection selections,
However, Cowtan discloses:
- expresses a Pauli string from the plurality of Pauli strings through a series of qubit connection selections
[0114]:
perform macroscopic term sequencing for the circuit using Pauli strings.
[0009]:
systems and methods are described for generating a quantum circuit. In one particular embodiment, systems and methods are described for generating a quantum circuit from a Unitary Coupled Cluster (UCC) ansatz. In embodiments the UCC ansatz represents the excitation of a reference state by a parameterised operator including excitation operators. The UCC ansatz includes multi-qubit Pauli operators, referred to as Pauli strings, determined from each excitation operator. In embodiments, a method for generating a quantum circuit includes partitioning the Pauli strings into mutually commuting sets and sequencing the Pauli strings by set.
[0009]:
In embodiments, each set of Pauli gadgets is diagonalised to convert the Pauli gadgets into phase gadgets which are then transformed into one- and two-qubit native gates to generate the quantum circuit.
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine George, and Cowtan.
George teaches superconducting quantum processor topology as a X-tree architecture.
Cowtan teaches compiler support.
One of ordinary skill would have motivation to combine George, and Cowtan to optimize for convergence towards ground state using hybrid quantum-classical algorithms (Cowtan [0019])
In regard to claim 12: (Original)
George discloses:
- synthesizing the quantum circuit and altering the position of the logical qubit are performed in conjunction with each other.
[Col 7, lines 11-17]:
In some implementations, the control system 110 includes a classical computing system that executes software to compile instructions for the quantum processor 102. For example, the control system 110 may decompose a quantum logic circuit or quantum computing program into discrete control operations or sets of control operations that can be executed by the hardware in the quantum computing system 100.
[Col 5, lines 17-24]:
Control signals can manipulate the quantum states of individual qubits and the joint states of multiple qubits. In some instances, conditional quantum logic can be performed in a manner that allows large-scale entanglement within the quantum processor 102. In some instances, information can be read out from the composite quantum system by measuring the quantum states of the individual qubits.
[Col 2, lines 41-43]:
multiple child qubit devices corresponding to leaves in the tree structure can operate
collectively as a logical qubit.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over
Alexander Papageorge et.al. (hereinafter George) US 10540604 B1,
in view of Yudong Cao et.al. (hereinafter Cao) US 20200104740 A1,
in view of Firas Hamze et.al. (hereinafter Hamze) US 20150269124 A1.
further in view of Stefan Berchtold et.al. (hereinafter Berch) The X-tree: An Index Structure for High-Dimensional Data, Proceeding of the Twenty-second International Conference on Very Large Data-Bases, Morgan Kaufmann, 1996, S.28-39.
In regard to claim 3: (Original)
George, Cao and Hamze do not explicitly disclose:
- segmented into a plurality of levels, and wherein a connection between the root node and the leaf node crosses between two levels from the plurality of levels.
However, Berch discloses:
- segmented into a plurality of levels, and wherein a connection between the root node and the leaf node crosses between two levels from the plurality of levels.
[3, Page 31]:
The X-tree The X-tree (eXtended node tree) is a new index structure supporting efficient query processing of high-dimensional data. The goal is to support not only point data but also extended spatial data and therefore, the X-tree uses the concept of overlapping regions. From the insight obtained in the previous section, it is clear that we have to avoid overlap in the directory in order to improve the indexing of high-dimensional data
PNG
media_image4.png
243
398
media_image4.png
Greyscale
[BRI: the X-tree of Fig 5 shows 4 levels where the root nodes and leaf nodes (data nodes) crosses two levels]
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine George, Cao, Hamze and Berch.
George teaches superconducting quantum processor topology.
Cao teaches VQE and sparse connections of qubits.
Hamze teaches X-tree representation in which each node is a qubit and each edge is connection between the related qubits.
Berch teaches x-tree.
One of ordinary skill would have motivation to combine George, Cao, Hamze and Berch that improves the performance in indexing high dimensional data using X-tree (Berch [1, Page 28]).
In regard to claim 4: (Original)
George discloses:
- the superconducting quantum processor topology comprises five superconducting qubits, wherein a first superconducting qubit from the five superconducting qubits
[Col 4, lines 1-3]:
In some cases, the quantum processor 102 includes a superconducting circuit, and the qubit devices are implemented as circuit devices.
[Col 13, lines 54-63]:
In a first example, a computational state is encoded in a quantum processor. The quantum processor includes a plurality of devices residing in a plurality of physical layers. The quantum processor includes connections that interconnect the plurality of devices in a tree structure topology. The computational state is encoded in child qubit devices in a first layer of the tree structure topology. A quantum control sequence is applied to at least one of the plurality of devices to transform the computational state in the quantum processor.
George, Cao and Hamze do not explicitly disclose:
- represented as the root node in a first level of the X-tree architecture, and wherein four other superconducting qubits from the five superconducting qubits are represented as leaf nodes in a second level of the X-tree architecture.
However, Berch discloses:
- represented as the root node in a first level of the X-tree architecture, and wherein four other superconducting qubits from the five superconducting qubits are represented as leaf nodes in a second level of the X-tree architecture.
[3, Page 31]:
The X-tree The X-tree (eXtended node tree) is a new index structure supporting efficient query processing of high-dimensional data. The goal is to support not only point data but also extended spatial data and therefore, the X-tree uses the concept of overlapping regions. From the insight obtained in the previous section, it is clear that we have to avoid overlap in the directory in order to improve the indexing of high-dimensional data
PNG
media_image4.png
243
398
media_image4.png
Greyscale
[BRI: the X-tree of Fig 5 shows the first node at the root and its child is a supernode at the second level showing the supernode with 4 nodes which is further connected to the next level]
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine George, Cao, Hamze and Berch.
George teaches superconducting quantum processor topology.
Cao teaches VQE and sparse connections of qubits.
Hamze teaches X-tree representation in which each node is a qubit and each edge is connection between the related qubits.
Berch teaches x-tree.
One of ordinary skill would have motivation to combine George, Cao, Hamze and Berch that improves the performance in indexing high dimensional data using X-tree (Berch [1, Page 28]).
Conclusion
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/TIRUMALE K RAMESH/Examiner, Art Unit 2121
/Li B. Zhen/Supervisory Patent Examiner, Art Unit 2121
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