DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. Claims 1, 4-11, 13-18 and 21-25 are currently presented for Examination.
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
3. The amendment filed on 11/05/2025 has been entered and considered by the examiner. By the
amendment, claims 1, 11, 18 and 24-25 are amended. In view of amendments made, examiner withdrawn the 101 rejections. Regarding the 101 rejections, the claim requires generating new test patterns, modifying circuit structure and testing fabricated hardware. Claim recites “wherein executing the test comprises: generating input conditions according to the test pattern; applying the input conditions to electrical input pins of the fabricated physical integrated circuit formed from the modified circuit model, via an automated test system comprising signal generation hardware and measurement instrumentation; receiving measured output electrical signals from the fabricated physical integrated circuit; and determining whether the fabricated physical integrated circuit is operating as designed based on the measured output electrical signals.” The amended claims clearly integrate any judicial exception into a practical application by requiring concrete physical operations on fabricated integrated circuits through automated test systems, in a manner that effects an actual technological improvement to IC defect detection coverage and test development efficiency. The claims ties into a technical process for improving IC testing, which improves detection of unmodeled defects in integrated circuits. See as filed specification [0020-0021]
The 103 rejection of the claims is modified and an explanation is provided below. See office below.
Applicant 103 arguments
The Combination of Wen and Pichamuthu Fails to Teach the Amended Claims Assigning "virtual defects" that are "arbitrarily assigned identifiers uniquely associated with one set of input conditions and assigned independent of, and without reference to, any modeled fault effect or any known or assumed physical characteristic, limitation, or defect of an integrated circuit physically formed according to the circuit model." Determining, based on simulation results, that a logic behavioral model is "untested" because a simulated instance produced no fault relative to its expected output" In response to that determination, modifying the circuit model "by adding one or more logic components at input ports of the circuit model to adaptively configure input conditions" correlated to the untested model. " Generating a new test pattern for the modified circuit model "different from the plurality of existing test patterns and enabling detection of unmodeled defects.". Executing the new test pattern on a fabricated physical IC via an automated test system having signal generation hardware and measurement instrumentation and using the measured electrical signals to determine whether the IC is operating as designed. Neither Wen nor Pichamuthu, separately or in combination, discloses or suggests these limitations.
Examiner response
In view of Applicant amendment and arguments, Examiner withdraw the Pichamuthu references and added the new reference Rajski and Sokar. Now the claims are rejected under Wen et al. (US 20060107157 A1) in view of Rajski et al. (US20060053357A1) and further in view of Sokar et al. (PAT NO: US11182525B1). See office action for detail.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
7. Claims 1, 4-11, 13-18 and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Wen et al. (US 20060107157 A1) in view of Rajski et al. (US20060053357A1) and further in view of Sokar et al. (PAT NO: US11182525B1)
Regarding claim 1
Wen teaches assigning, to each of a plurality of sets of input conditions of a circuit model, a corresponding virtual defect, (see para 69-73-At step 602, X-injection is carried out to assign different X symbols for showing uncertain faulty values in the calculation of simulated output responses to the fanout branches of the gate Xi. For example, as illustrated in FIG. 7, if the gate G1 is a failing candidate gate having fanout branches b1, b2 and b3, X1(b1), X2 (b2) and X3(b3) are injected into the fanout branches b1, b2 and b3. See para 60-64- In FIG. 4A, which illustrates an example of an integrated logic circuit unit 1, this integrated logic circuit unit 1 is formed by gates G1, G2, G3 and G4, five input signal lines I1, I2, . . . , I5 and three output signal-lines O1, O2 and O3. In this case, if the integrated logic circuit unit 1 is normally operated under the condition that an input vector VEC is applied to the input signal lines I1, I2, . . . , I5, an expected output response EXO is obtained at the output signal lines O1, O2 and O3)
generating a table of the circuit model, the table including a plurality of logic behavioral models of the circuit model, each of the plurality of logic behavioral models including a corresponding set of the plurality of sets of input conditions, a corresponding output result, and the corresponding virtual defect; (see [005]- a dynamic defect changes its behavior for different input vectors because the strength of a signal can vary for different input conditions. Finally, a circuit may contain a single defect or multiple defects. see para 18-24- A fanout-free gate has one X-fault, corresponding to any physical defect or defects in the gate or on its output. The X-fault model handles the unknown faulty behavior of a complex defect such as a Byzantine defect with different X symbols. The X-fault model allows a fault to have different faulty behaviors under different input vectors, making it suitable for the per-test fault diagnosis scheme in handling dynamic defects. see para 57-60 and fig 4A-4B- In FIG. 3, which illustrates an example of the X-fault model, in accordance with the present invention, X1 and X2 denote two arbitrary faulty logic values. Therefore, the fanout X-fault model can closely represent such complex defects as Byzantine defects. In FIG. 4A, which illustrates an example of an integrated logic circuit unit 1, this integrated logic circuit unit 1 is formed by gates G1, G2, G3 and G4, five input signal lines I1, I2, . . . , I5 and three output signal-lines O1, O2 and O3. In this case, if the integrated logic circuit unit 1 is normally operated under the condition that an input vector VEC is applied to the input signal lines I1, I2, . . . , I5, an expected output response EXO is obtained at the output signal lines O1, O2 and O3. An example of the relationship between the input vector VEC and the expected output response EXO is illustrated in FIG. 4B. Note that, in FIG. 4A, an input vector VECi=(0, 1, 1, 0, 1) is applied as the input vector VEC to the input signal lines I1, I2, . . . , I5, and its resulting expected output response EXO=(1, 0, 1) is obtained. see para 95- Steps 1104 to 1110 perform a matching operation between the above-mentioned simulated output response SHO (Pk) and the observed output response OBO to obtain fault diagnosis values p(FVEC, Gi). In this case, since the fault diagnosis values p(FVEC, Gi) are calculated in consideration of an error rate and a fault level, each of the fault diagnosis values p(FVEC, Gi) varies from 0 to 1. Note that the fault diagnosis values (matching values) of the prior art per-test fault diagnosis method were 1 (coincidence) or 0 (incoincidence). see fig 14 fault diagnosis table and para 130- That is, all essential faults are extracted and excluded from the fault diagnosis table to change it to a target diagnosis table. Note that one essential fault is defined by a fault such that an entry in the fault diagnosis table is the only non-zero entry in the corresponding row (failing input vector) and the corresponding column (faulty gate). The essential faults are indispensable in the multiplet. If there is no essential fault, the target diagnosis table is the same as the original diagnosis table.)
Examiner note: See table 4B. Wen describes the "X-fault" acting as a proxy for defects (including complex/Byzantine defects).
executing, according to the table, a fault detection simulation by simulating a plurality of instances of the circuit model according to the table comprising logic gates, wherein simulating the plurality of instances of the circuit model comprises applying a plurality of existing test patterns, each associated with the corresponding virtual defect, to the circuit model to simulate behavior of the logic gates, (see para 002- The present invention relates to a method and apparatus for carrying out fault diagnosis for integrated logic circuits (or “circuits” hereafter), to achieve high diagnostic resolution even in the presence of complex, dynamic, and/or multiple defects, all inevitable in deep-submicron circuits. See para 18-24-The X-fault model allows a fault to have different faulty behaviors under different input vectors, making it suitable for the per-test fault diagnosis scheme in handling dynamic defects. see para 57-60 and fig 4A-4B- In the above-mentioned prior art per-test fault diagnosis method, however, as explained above, the accuracy is low for a circuit with complex defects, since a misdiagnosis may occur for a Byzantine defect such as a resistive short or open which shows a plurality of logical behaviors as illustrated in FIGS. 1 and 2. In FIG. 3, which illustrates an example of the X-fault model, in accordance with the present invention, X1 and X2 denote two arbitrary faulty logic values. Therefore, the fanout X-fault model can closely represent such complex defects as Byzantine defects. In FIG. 4A, which illustrates an example of an integrated logic circuit unit 1, this integrated logic circuit unit 1 is formed by gates G1, G2, G3 and G4, five input signal lines I1, I2, . . . , I5 and three output signal-lines O1, O2 and O3. In this case, if the integrated logic circuit unit 1 is normally operated under the condition that an input vector VEC is applied to the input signal lines I1, I2, . . . , I5, an expected output response EXO is obtained at the output signal lines O1, O2 and O3. An example of the relationship between the input vector VEC and the expected output response EXO is illustrated in FIG. 4B. Note that, in FIG. 4A, an input vector VECi=(0, 1, 1, 0, 1) is applied as the input vector VEC to the input signal lines I1, I2, . . . , I5, and its resulting expected output response EXO=(1, 0, 1) is obtained. See also fig 14.)
Examiner note: Examiner consider the input vector as a test pattern which is a set of specific inputs provided to a system to verify its behavior and functionality.
generating a plurality of simulation outputs in response to applying the plurality of existing test patterns; (See para 60 and fig 4A-4B-In FIG. 4A, which illustrates an example of an integrated logic circuit unit 1, this integrated logic circuit unit 1 is formed by gates G1, G2, G3 and G4, five input signal lines I1, I2, . . . , I5 and three output signal-lines O1, O2 and O3. In this case, if the integrated logic circuit unit 1 is normally operated under the condition that an input vector VEC is applied to the input signal lines I1, I2, . . . , I5, an expected output response EXO is obtained at the output signal lines O1, O2 and O3. An example of the relationship between the input vector VEC and the expected output response EXO is illustrated in FIG. 4B. Note that, in FIG. 4A, an input vector VECi=(0, 1, 1, 0, 1) is applied as the input vector VEC to the input signal lines I1, I2, . . . , I5, and its resulting expected output response EXO=(1, 0, 1) is obtained. See also para 83- Thus, one or more simulated output responses are obtained for each combination of one input vector and one faulty gate, which would relax a matching condition which will be explained later.))
comparing each of the plurality of simulation outputs to a vector from the plurality of logic behavioral models in the table; detecting, in response to a match between at least one simulation output and the vector, at least one instance of the plurality of instances that is absent of the fault; (See para 26-30-All previous per-test fault diagnosis methods use a strict matching criterion, in which a fault simulation result for a fault in a circuit model is compared with the corresponding observed response of the real circuit at all primary outputs under a failing vector. This often results in a mismatch, which leads to lower diagnostic resolution. In the present invention three factors, i.e. the matching information, the number of matched errors, and the depth of a fault, are all used in per-test fault diagnosis. A diagnosis value is calculated for each fault based on the three factors. Generally, the diagnosis value for a fault under a failing input vector is zero if the fault-simulation result and its corresponding circuit response does not match for the fault and the failing input vector. See fig 11 and see para 90-92- First, at step 1101, a difference vector DEP is calculated by an exclusive OR operation between the bits of an observed output response OBO at the output signal lines O.sub.1, O.sub.2 and O.sub.3 of the integrated logic circuit unit 1 and the corresponding bits of its expected output response EXO. Next, at step 1102, it is determined whether |DEF| is 0. As a result, when |DEF| is 0, this means that the observed output response OBO coincides with the expected-output response EPO, i.e., no fault is generated)
Examiner note: According to the instant specification [0037]one or more behavioral models with sets of input conditions unable to detect any fault as an untested behavioral model. Step 1102 determines no fault for one or more behavioral models (VEC) with sets of input conditions when the |DEF| is 0. Comparisons happening under an input condition reflects instances.
Wen does not teach wherein each virtual defect is an arbitrarily assigned identifier uniquely associated with one such set of input conditions and is assigned independent of, and without reference to, any modeled fault effect or any known or assumed physical characteristic, limitation, or defect of an integrated circuit physically formed according to the circuit model; determining, in response to executing the detection, that at least one of the plurality of logic behavioral models is untested based on the detected at least one instance of the plurality of instances corresponding to the at least one of the plurality of logic behavioral models absent of the fault;in response to determining that the at least one of the plurality of logic behavioral models is untested, modifying the circuit model by adding one or more logic components at input ports of the circuit model to adaptively configure input conditions, according to input conditions unable to detect fault associated with the at least one of the plurality of logic behavioral models that is untested; generating, according to the modification, a modified circuit model for physical implementation of the integrated circuit; generating a test pattern for the modified circuit model, based at least in part on the table of the circuit model associated with the at least one of the plurality of logic behavioral models that is untested, wherein the test pattern is different from the plurality of existing test patterns and enables detection of unmodeled defects; and executing, using the test pattern, a test on the integrated circuit formed based on the modified circuit model having the one or more added logic components, wherein executing the test comprises: generating input conditions according to the test pattern; applying the input conditions to electrical input pins of the fabricated physical integrated circuit formed from the modified circuit model, via an automated test system comprising signal generation hardware and measurement instrumentation; receiving measured output electrical signals from the fabricated physical integrated circuit; and determining whether the fabricated physical integrated circuit is operating as designed based on the measured output electrical signals.
In the related field of invention, Rajski teaches wherein each virtual defect is an arbitrarily assigned identifier uniquely associated with one such set of input conditions (see para 130-131-An extracted defect can be defined by the data describing the actual defect, like location and physical properties. Additional data can be associated with each defect. For example, in one exemplary implementation, the defects in the list (9) have one, some, or all of the following additional properties: 1. A unique identifier. See para 256- Therefore, according to one embodiment, the size of the fault dictionary can be reduced by assigning one unique ID for each unique observation point combination. See also para 188)
determining, in response to executing the detection, that at least one of the plurality of logic behavioral models is untested based on the detected at least one instance of the plurality of instances corresponding to the at least one of the plurality of logic behavioral models absent of the fault; (see para 0008- In some embodiments of the disclosed method, the existence of at least one potential defect not found in the generated dictionary can also be diagnosed (for example, using incremental diagnosis or incremental simulation). see para 154-155- In general, however, the test-result analysis is performed to determine from the test result data (20) and the dictionary (16) which classes of defects have failed, and if possible, which individual defects. FIG. 31 is a block diagram showing an exemplary manner in which the processing (21) can be performed. Process (21.1) is performed to try to identify the defect, respectively the class or subclass of the defect, which can best explain the failing behavior of the integrated circuit. FIG. 39 also shows a comparison of the two associated step functions indicating the number of expected and observed defects, respectively, for each subclass of defect. See para 164- Generate additional test patterns to cover defects that may not have been covered before. See para 208- In case the ATPG (13.3.1.2) determines faults to be untestable, it can update the fault list (A) and the dictionary (B), using an updating procedure (13.3.1.5). Otherwise, the ATPG (13.3.1.2) can make the generated test-pattern candidate available for defect simulation (13.3.1.3))
in response to determining that the at least one of the plurality of logic behavioral models is untested, (see para 0008 and See para 164- Generate additional test patterns to cover defects that may not have been covered before) modifying the circuit model by adding one or more logic components at input ports of the circuit model to adaptively configure input conditions, according to input conditions unable to detect fault associated with the at least one of the plurality of logic behavioral models that is untested; (see para 14-In some embodiments, probabilities that one or more of the potential defects actually caused the integrated circuit failures are determined from diagnostic results produced using the fault dictionary. These probabilities are then reported. One or more of the following acts can be performed based at least in part on the reported probabilities: (a) adjusting one or more design manufacturing rules; (b) adjusting one or more defect extraction rules; or (c) providing recommended modifications of one or more features in the integrated circuit. see para 99-101- A netlist description (for example, netlist (4713)) of a design can be modified to enable design-for-test procedures like test pattern generation, simulation, and fault simulation to support defect-based testing by adding or deleting gates, or by adding or deleting signal lines, or both. This analysis investigates if some of the DFM rules (1) from which the defect-extraction rules (3) were derived should be modified. This information can be used to improve the DFM rules, and thus the yield, for the current integrated circuit (e.g. by means of a redesign or a mask modification (27)). In addition, the improved DFM rules can lead to higher initial yield of the next design, which is based on the now-improved DFM rules. See para 255- For illustrative purposes, this discussion makes reference to FIG. 46, which shows an exemplary fanout-free region embedded in a circuit. The exemplary region comprises one NAND gate and one OR gate. Signal s is termed the “stem” of this fanout-free region, and signal lines a, b, c, and d are internal signals. For illustrative purposes only, assume that only combinational test pattern sets are used to test this circuit.)
generating, according to the modification, a modified circuit model for physical implementation of an integrated circuit; (see para 14-In some embodiments, probabilities that one or more of the potential defects actually caused the integrated circuit failures are determined from diagnostic results produced using the fault dictionary. These probabilities are then reported. One or more of the following acts can be performed based at least in part on the reported probabilities: (a) adjusting one or more design manufacturing rules; (b) adjusting one or more defect extraction rules; or (c) providing recommended modifications of one or more features in the integrated circuit. In some embodiments, the fault dictionary is a compressed fault dictionary using one or more bit masks to associate one or more failing test responses to respective potential defects. See para 101- This analysis investigates if some of the DFM rules (1) from which the defect-extraction rules (3) were derived should be modified. This information can be used to improve the DFM rules, and thus the yield, for the current integrated circuit (e.g. by means of a redesign or a mask modification (27)).)
generating a test pattern for the modified circuit model, based at least in part on the table of the circuit model associated with the at least one of the plurality of logic behavioral models that is untested, wherein the test pattern is different from the plurality of existing test patterns and enables detection of unmodeled defects; (see para 0008- In some embodiments of the disclosed method, the existence of at least one potential defect not found in the generated dictionary can also be diagnosed (for example, using incremental diagnosis or incremental simulation). and see para 14-In some embodiments, probabilities that one or more of the potential defects actually caused the integrated circuit failures are determined from diagnostic results produced using the fault dictionary. These probabilities are then reported. One or more of the following acts can be performed based at least in part on the reported probabilities: (a) adjusting one or more design manufacturing rules; (b) adjusting one or more defect extraction rules; or (c) providing recommended modifications of one or more features in the integrated circuit. See para 76- fault simulation/test pattern generating component (4712) (such as an automatic test pattern generation (ATPG) tool) can receive the extracted defects and operate to create one or more test patterns targeting the extracted defects. To generate the test patterns, the test pattern generating component (4712) can use a different representation of the integrated circuit, such as a netlist (4713). see para 99-101- A netlist description (for example, netlist (4713)) of a design can be modified to enable design-for-test procedures like test pattern generation, simulation, and fault simulation to support defect-based testing by adding or deleting gates, or by adding or deleting signal lines, or both. This analysis investigates if some of the DFM rules (1) from which the defect-extraction rules (3) were derived should be modified. This information can be used to improve the DFM rules, and thus the yield, for the current integrated circuit (e.g. by means of a redesign or a mask modification (27)). In addition, the improved DFM rules can lead to higher initial yield of the next design, which is based on the now-improved DFM rules. See para 164- Generate additional test patterns to cover defects that may not have been covered before. See para 152- The fault dictionary can comprise, for example, a table organized into rows, with each row containing data for a test pattern.)
and executing, using the test pattern, a test on the integrated circuit formed based on the modified circuit model having the one or more added logic components. (see para 153-It is assumed for purposes of this discussion that devices realizing the integrated circuit (5) have been tested using the test pattern set (17) as illustrated in Section III of FIG. 1. See para 0077 and fig 47--The integrated circuit design is manufactured (4705) and tested (4714) (for example, using a tester or ATE). During testing (4714), fail information for one or more integrated circuits can be recorded. The testing can be performed, for example, using the generated test patterns targeting the extracted defects.)
wherein executing the test comprises: generating input conditions according to the test pattern; applying the input conditions to electrical input pins of the fabricated physical integrated circuit formed from the modified circuit model, via an automated test system comprising signal generation hardware and measurement instrumentation; receiving measured output electrical signals from the fabricated physical integrated circuit; and determining whether the fabricated physical integrated circuit is operating as designed based on the measured output electrical signals. (see para 0012- A set of test patterns is produced by: (a) selecting from previously generated test patterns one or more test patterns that detect at least some of the identified potential defects; (b) generating one or more test patterns that explicitly target at least some of the identified potential defects; or both (a) and (b). Test-result data can be received that comprises failing test responses obtained during testing of the integrated circuits using at least a portion of the test patterns in the set of test patterns. The at least one fault dictionary can be applied to the test-result data in order to diagnose potential defects associated with one or more of the failing test responses. see para 153-It is assumed for purposes of this discussion that devices realizing the integrated circuit (5) have been tested using the test pattern set (17) as illustrated in Section III of FIG. 1. Test result data (20) can be available either in real time (while production testing is still in progress) or from a database storing earlier test results. Section IV of FIG. 1 involves the processing and analysis of test-result data (21). A more detailed description of the analysis is provided in a separate section below. In general, however, the test-result analysis is performed to determine from the test result data (20) and the dictionary (16) which classes of defects have failed, and if possible, which individual defects See para 0077 and fig 47--The integrated circuit design is manufactured (4705) and tested (4714) (for example, using a tester or ATE). During testing (4714), fail information for one or more integrated circuits can be recorded. The testing can be performed, for example, using the generated test patterns targeting the extracted defects.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date
of the claimed invention to modify the method for diagnosing faults in an integrated logic circuit as disclosed by Wen to include wherein each virtual defect is an arbitrarily assigned identifier uniquely associated with one such set of input conditions; determining, in response to executing the detection, that at least one of the plurality of logic behavioral models is untested based on the detected at least one instance of the plurality of instances corresponding to the at least one of the plurality of logic behavioral models absent of the fault; in response to determining that the at least one of the plurality of logic behavioral models is untested, modifying the circuit model by adding one or more logic components at input ports of the circuit model to adaptively configure input conditions, according to input conditions unable to detect fault associated with the at least one of the plurality of logic behavioral models that is untested; generating, according to the modification, a modified circuit model for physical implementation of the integrated circuit; generating a test pattern for the modified circuit model, based at least in part on the table of the circuit model associated with the at least one of the plurality of logic behavioral models that is untested, wherein the test pattern is different from the plurality of existing test patterns and enables detection of unmodeled defects; and executing, using the test pattern, a test on the integrated circuit formed based on the modified circuit model having the one or more added logic components, wherein executing the test comprises: generating input conditions according to the test pattern; applying the input conditions to electrical input pins of the fabricated physical integrated circuit formed from the modified circuit model, via an automated test system comprising signal generation hardware and measurement instrumentation; receiving measured output electrical signals from the fabricated physical integrated circuit; and determining whether the fabricated physical integrated circuit is operating as designed based on the measured output electrical signals as taught by Rajski in the system of Wen in order to reduce the number of defective chips being produced, foundries (integrated circuit manufacturers) often provide a number of recommended design rules that designers can use to help improve the yield of their particular design. Such rules are generally referred to herein as Design for Manufacturability (DFM) rules and can pertain to a wide variety of parameters related to integrated circuit design. (see para 0004, Rajski)
The combination of Wen and Rajski does not teach each virtual defect is assigned independent of, and without reference to, any modeled fault effect or any known or assumed physical characteristic, limitation, or defect of an integrated circuit physically formed according to the circuit model.
In the related field of invention, Sokar teaches each virtual defect is assigned independent of, and without reference to, any modeled fault effect or any known or assumed physical characteristic, limitation, or defect of an integrated circuit physically formed according to the circuit model. (see col 2 line 15-28- In one embodiment of the disclosure, a fault aware analog model (FAAM) system is disclosed. The FAAM system comprises a FAAM builder module comprising a model construction module configured to receive a reference dataset associated with a circuit block. In some embodiments, the reference dataset comprises a set of data values that defines input to output relationship of the circuit block for both in spec and out of spec operation of the circuit block, wherein the reference data set is derived based on data associated with a ground truth representation of the circuit block. The model construction module is further configured to generate a FAAM comprising a behavioral model of the circuit block, based on the reference dataset. In some embodiments, the FAAM is configured to approximate the input to output relationship of the circuit block that is defined by the set of data values in the reference dataset. See col 8 line 55-58- Simple Random Sampling (SRS) or Latin-Hypercube-Sampling (LHS), to form the set of input values to be utilized within the reference dataset. See col 6 line 29-31- In one embodiment, a method to develop a FAAM based on extending nominal models with out-of-spec behavior using the reference data set is disclosed. See col 11 line 33-40- Generally, the parametric model is not constructed based on physical assumptions and laws, but is rather fitted/trained based on the generated reference dataset, so that it represents the reference dataset as well as possible. Specifically, the plurality of model parameters is modified/trained based on the reference dataset, in order for the parametric model to approximate the input-output relationship defined by the reference dataset. See fig 3A (lookup table))
Examiner note: “Fault inputs” to the model where the faults originate exterior to the model itself, i.e. from the source blocks. These are the inputs which are irrespective of physical defects of the circuit model.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date
of the claimed invention to modify the method for diagnosing faults in an integrated logic circuit as disclosed by Wen to include each virtual defect is assigned independent of, and without reference to, any modeled fault effect or any known or assumed physical characteristic, limitation, or defect of an integrated circuit physically formed according to the circuit model as taught by Sokar in the system of Wen and Rajski in order develop data driven behavioral models that are fault-aware. Another motivation is to find defects such as hard defects (open and short circuits) and/or soft/parametric defects (change in a process parameter of a circuit element), that are present in the circuit due to unintended production errors or post-manufacturing mishandling. Thus, it provides the probabilities that the Integrated Circuit (IC) does or does not contain a fault, given that the test program has pass. (see col 1 line 5-25, Sokar)
Regarding claim 11
Wen teaches a device comprising: one or more processors; and a non-transitory computer readable medium storing instruction when executed by the one or more processors cause the one or more processors to: (see para 151 and claim 26-Note that the above-mentioned flowcharts of FIGS. 5, 6 and 11 can be stored in an ROM or another nonvolatile memory or in a random access memory or another volatile memory)
generate a table of a circuit model, the table including a plurality of logic behavioral models of the circuit model, each of the plurality of logic behavioral models including a corresponding set of input conditions, a corresponding output result, and a corresponding virtual defect,( see [005]- a dynamic defect changes its behavior for different input vectors because the strength of a signal can vary for different input conditions. Finally, a circuit may contain a single defect or multiple defects. see para 18-24- A fanout-free gate has one X-fault, corresponding to any physical defect or defects in the gate or on its output. The X-fault model handles the unknown faulty behavior of a complex defect such as a Byzantine defect with different X symbols. The X-fault model allows a fault to have different faulty behaviors under different input vectors, making it suitable for the per-test fault diagnosis scheme in handling dynamic defects. see para 57-60 and fig 4A-4B- In FIG. 3, which illustrates an example of the X-fault model, in accordance with the present invention, X1 and X2 denote two arbitrary faulty logic values. Therefore, the fanout X-fault model can closely represent such complex defects as Byzantine defects. In FIG. 4A, which illustrates an example of an integrated logic circuit unit 1, this integrated logic circuit unit 1 is formed by gates G1, G2, G3 and G4, five input signal lines I1, I2, . . . , I5 and three output signal-lines O1, O2 and O3. In this case, if the integrated logic circuit unit 1 is normally operated under the condition that an input vector VEC is applied to the input signal lines I1, I2, . . . , I5, an expected output response EXO is obtained at the output signal lines O1, O2 and O3. An example of the relationship between the input vector VEC and the expected output response EXO is illustrated in FIG. 4B. Note that, in FIG. 4A, an input vector VECi=(0, 1, 1, 0, 1) is applied as the input vector VEC to the input signal lines I1, I2, . . . , I5, and its resulting expected output response EXO=(1, 0, 1) is obtained. see para 95- Steps 1104 to 1110 perform a matching operation between the above-mentioned simulated output response SHO (Pk) and the observed output response OBO to obtain fault diagnosis values p(FVEC, Gi). In this case, since the fault diagnosis values p(FVEC, Gi) are calculated in consideration of an error rate and a fault level, each of the fault diagnosis values p(FVEC, Gi) varies from 0 to 1. Note that the fault diagnosis values (matching values) of the prior art per-test fault diagnosis method were 1 (coincidence) or 0 (incoincidence). see fig 14 fault diagnosis table and para 130- That is, all essential faults are extracted and excluded from the fault diagnosis table to change it to a target diagnosis table. Note that one essential fault is defined by a fault such that an entry in the fault diagnosis table is the only non-zero entry in the corresponding row (failing input vector) and the corresponding column (faulty gate). The essential faults are indispensable in the multiplet. If there is no essential fault, the target diagnosis table is the same as the original diagnosis table.)
Examiner note: In digital circuit testing, input conditions with faulty gates correspond to "virtual defects" through fault modeling. Faulty gate corresponds to a virtual defect. A stuck-at fault assumes that a signal line in a circuit is permanently fixed at a logical '0' or a logical '1', regardless of the inputs to the circuit. This is a behavioral, or logical, description of a defect and largely irrespective of the physical characteristics of a specific integrated circuit (IC). This logical modeling approach is a fundamental principle of digital circuit testing.
perform, according to one or more test patterns associated with a circuit model, fault detection simulation by simulating a plurality of instances of the circuit model according to the table comprising logic gates, wherein simulating the plurality of instances of the circuit model comprises applying a plurality of existing test patterns, each associated with the corresponding virtual defect, to the circuit model to simulate behavior of the logic gates, (see para 002- The present invention relates to a method and apparatus for carrying out fault diagnosis for integrated logic circuits (or “circuits” hereafter), to achieve high diagnostic resolution even in the presence of complex, dynamic, and/or multiple defects, all inevitable in deep-submicron circuits. see para 57-60 and fig 4A-4B- In the above-mentioned prior art per-test fault diagnosis method, however, as explained above, the accuracy is low for a circuit with complex defects, since a misdiagnosis may occur for a Byzantine defect such as a resistive short or open which shows a plurality of logical behaviors as illustrated in FIGS. 1 and 2. In FIG. 3, which illustrates an example of the X-fault model, in accordance with the present invention, X1 and X2 denote two arbitrary faulty logic values. Therefore, the fanout X-fault model can closely represent such complex defects as Byzantine defects. In FIG. 4A, which illustrates an example of an integrated logic circuit unit 1, this integrated logic circuit unit 1 is formed by gates G1, G2, G3 and G4, five input signal lines I1, I2, . . . , I5 and three output signal-lines O1, O2 and O3. In this case, if the integrated logic circuit unit 1 is normally operated under the condition that an input vector VEC is applied to the input signal lines I1, I2, . . . , I5, an expected output response EXO is obtained at the output signal lines O1, O2 and O3. An example of the relationship between the input vector VEC and the expected output response EXO is illustrated in FIG. 4B. Note that, in FIG. 4A, an input vector VECi=(0, 1, 1, 0, 1) is applied as the input vector VEC to the input signal lines I1, I2, . . . , I5, and its resulting expected output response EXO=(1, 0, 1) is obtained. See also fig 14)
Examiner note: Examiner consider the input vector as a test pattern which is a set of specific inputs provided to a system to verify its behavior and functionality.
generating a plurality of simulation outputs in response to applying the plurality of existing test patterns; (See para 60 and fig 4A-4B-In FIG. 4A, which illustrates an example of an integrated logic circuit unit 1, this integrated logic circuit unit 1 is formed by gates G1, G2, G3 and G4, five input signal lines I1, I2, . . . , I5 and three output signal-lines O1, O2 and O3. In this case, if the integrated logic circuit unit 1 is normally operated under the condition that an input vector VEC is applied to the input signal lines I1, I2, . . . , I5, an expected output response EXO is obtained at the output signal lines O1, O2 and O3. An example of the relationship between the input vector VEC and the expected output response EXO is illustrated in FIG. 4B. Note that, in FIG. 4A, an input vector VECi=(0, 1, 1, 0, 1) is applied as the input vector VEC to the input signal lines I1, I2, . . . , I5, and its resulting expected output response EXO=(1, 0, 1) is obtained. See also para 83)
compare each of the plurality of simulation outputs to a vector from the plurality of logic behavioral models in the table; detect, in response to a match between at least one simulation output and the vector, at least one instance of the plurality of instances that is absent of the fault; (See para 26-30-All previous per-test fault diagnosis methods use a strict matching criterion, in which a fault simulation result for a fault in a circuit model is compared with the corresponding observed response of the real circuit at all primary outputs under a failing vector. This often results in a mismatch, which leads to lower diagnostic resolution. In the present invention three factors, i.e. the matching information, the number of matched errors, and the depth of a fault, are all used in per-test fault diagnosis. A diagnosis value is calculated for each fault based on the three factors. Generally, the diagnosis value for a fault under a failing input vector is zero if the fault-simulation result and its corresponding circuit response does not match for the fault and the failing input vector. See fig 11 and see para 90-92- First, at step 1101, a difference vector DEP is calculated by an exclusive OR operation between the bits of an observed output response OBO at the output signal lines O.sub.1, O.sub.2 and O.sub.3 of the integrated logic circuit unit 1 and the corresponding bits of its expected output response EXO. Next, at step 1102, it is determined whether |DEF| is 0. As a result, when |DEF| is 0, this means that the observed output response OBO coincides with the expected-output response EPO, i.e., no fault is generated)
Examiner note: According to the instant specification [0037]one or more behavioral models with sets of input conditions unable to detect any fault as an untested behavioral model. Step 1102 determines no fault for one or more behavioral models (VEC) with sets of input conditions when the |DEF| is 0.
generate a reduced table of the circuit model according to the detection including the at least one of the plurality of logic behavioral models that is untested based on the at least one instance of the plurality of instances absent of the fault; (see para 005- Fault diagnosis is the process of identifying suspicious areas in a failing circuit by making use of logical faults assumed in a circuit model. A logical fault has two attributes: location and logical behavior. In a gate-level circuit model, the location attribute is one or more nets or pins, and the logical behavior attribute is one or more logic values. Fault modeling defines these attributes in a general manner. The process of identifying faults, with likely link to physical defects, is known as fault diagnosis. See para 30- If the fault-simulation result and its corresponding circuit response match, the diagnosis value for the fault under the failing input vector is a value greater than zero, and the value is calculated based on the number of matched errors and the depth of a fault. see para 130-131- That is, all essential faults are extracted and excluded from the fault diagnosis table to change it to a target diagnosis table. Note that one essential fault is defined by a fault such that an entry in the fault diagnosis table is the only non-zero entry in the corresponding row (failing input vector) and the corresponding column (faulty gate). The essential faults are indispensable in the multiplet. If there is no essential fault, the target diagnosis table is the same as the original diagnosis table. In FIG. 14, the faulty gate G5 is an essential fault. Therefore, the faulty gate G5 is excluded from the original fault diagnosis table.)
Examiner note: By removing essential faults (faults uniquely detected by a specific input vector/gate combo), the remaining "target diagnosis table" represents a reduced model that excludes those specific faults. Therefore, the new target table models a state that is absent of those faults, and because those essential faults are no longer part of the diagnosis set, they are effectively untested in the context of the new, reduced diagnosis table.
Wen does not teach wherein each virtual defect is an arbitrarily assigned identifier uniquely associated with one such set of input conditions and is assigned independent of, and without reference to, any modeled fault effect or any known or assumed physical characteristic, limitation, or defect of an integrated circuit physically formed according to the circuit model; determine, in response to performing the detection, that at least one of the plurality of logic behavioral models is untested based on the detected at least one instance of the plurality of instances corresponding to the at least one of the plurality of logic behavioral models absent of the fault; modify, according to the reduced table, the circuit model by adding one or more logic components at input ports of the circuit model to adaptively configure input conditions, according to input conditions unable to detect fault associated with the at least one of the plurality of logic behavioral models that is untested; generate, according to the modification, a modified circuit model for physical implementation of the integrated circuit; generate an additional test pattern for the modified circuit model, wherein the additional test pattern is different from the plurality of existing test patterns and enables detection of unmodeled defects; and execute, using the test pattern, a test on the integrated circuit formed based on the modified circuit model having the one or more added logic components, wherein execute the test comprises: generate input conditions according to the test pattern; apply the input conditions to electrical input pins of the fabricated physical integrated circuit formed from the modified circuit model, via an automated test system comprising signal generation hardware and measurement instrumentation; receive measured output electrical signals from the fabricated physical integrated circuit; and determine whether the fabricated physical integrated circuit is operating as designed based on the measured output electrical signals.
In the related field of invention, Rajski teaches wherein each virtual defect is an arbitrarily assigned identifier uniquely associated with one such set of input conditions (see para 130-131-An extracted defect can be defined by the data describing the actual defect, like location and physical properties. Additional data can be associated with each defect. For example, in one exemplary implementation, the defects in the list (9) have one, some, or all of the following additional properties: 1. A unique identifier. See para 256- Therefore, according to one embodiment, the size of the fault dictionary can be reduced by assigning one unique ID for each unique observation point combination. See also para 188)
determine, in response to performing the detection, that at least one of the plurality of logic behavioral models is untested based on the detected at least one instance of the plurality of instances corresponding to the at least one of the plurality of logic behavioral models absent of the fault; (see para 0008- In some embodiments of the disclosed method, the existence of at least one potential defect not found in the generated dictionary can also be diagnosed (for example, using incremental diagnosis or incremental simulation). see para 154-155- In general, however, the test-result analysis is performed to determine from the test result data (20) and the dictionary (16) which classes of defects have failed, and if possible, which individual defects. FIG. 31 is a block diagram showing an exemplary manner in which the processing (21) can be performed. Process (21.1) is performed to try to identify the defect, respectively the class or subclass of the defect, which can best explain the failing behavior of the integrated circuit. FIG. 39 also shows a comparison of the two associated step functions indicating the number of expected and observed defects, respectively, for each subclass of defect. See para 164- Generate additional test patterns to cover defects that may not have been covered before. See para 208- In case the ATPG (13.3.1.2) determines faults to be untestable, it can update the fault list (A) and the dictionary (B), using an updating procedure (13.3.1.5). Otherwise, the ATPG (13.3.1.2) can make the generated test-pattern candidate available for defect simulation (13.3.1.3))
modify, according to the reduced table, the circuit model, by adding one or more logic components at input ports of the circuit model to adaptively configure input conditions, according to input conditions unable to detect fault associated with the at least one of the plurality of logic behavioral models that is untested; (see para 14-In some embodiments, probabilities that one or more of the potential defects actually caused the integrated circuit failures are determined from diagnostic results produced using the fault dictionary. These probabilities are then reported. One or more of the following acts can be performed based at least in part on the reported probabilities: (a) adjusting one or more design manufacturing rules; (b) adjusting one or more defect extraction rules; or (c) providing recommended modifications of one or more features in the integrated circuit. see para 99-101- A netlist description (for example, netlist (4713)) of a design can be modified to enable design-for-test procedures like test pattern generation, simulation, and fault simulation to support defect-based testing by adding or deleting gates, or by adding or deleting signal lines, or both. This analysis investigates if some of the DFM rules (1) from which the defect-extraction rules (3) were derived should be modified. This information can be used to improve the DFM rules, and thus the yield, for the current integrated circuit (e.g. by means of a redesign or a mask modification (27)). In addition, the improved DFM rules can lead to higher initial yield of the next design, which is based on the now-improved DFM rules. See para 255- For illustrative purposes, this discussion makes reference to FIG. 46, which shows an exemplary fanout-free region embedded in a circuit. The exemplary region comprises one NAND gate and one OR gate. Signal s is termed the “stem” of this fanout-free region, and signal lines a, b, c, and d are internal signals. For illustrative purposes only, assume that only combinational test pattern sets are used to test this circuit.)
generate, according to the modification, a modified circuit model for physical implementation of an integrated circuit; (see para 14-In some embodiments, probabilities that one or more of the potential defects actually caused the integrated circuit failures are determined from diagnostic results produced using the fault dictionary. These probabilities are then reported. One or more of the following acts can be performed based at least in part on the reported probabilities: (a) adjusting one or more design manufacturing rules; (b) adjusting one or more defect extraction rules; or (c) providing recommended modifications of one or more features in the integrated circuit. In some embodiments, the fault dictionary is a compressed fault dictionary using one or more bit masks to associate one or more failing test responses to respective potential defects. See para 101- This analysis investigates if some of the DFM rules (1) from which the defect-extraction rules (3) were derived should be modified. This information can be used to improve the DFM rules, and thus the yield, for the current integrated circuit (e.g. by means of a redesign or a mask modification (27)).)
generate an additional test pattern for the modified circuit model, wherein the additional test pattern is different from the plurality of existing test patterns and enables detection of unmodeled defects; (see para 0008- In some embodiments of the disclosed method, the existence of at least one potential defect not found in the generated dictionary can also be diagnosed (for example, using incremental diagnosis or incremental simulation). and see para 14-In some embodiments, probabilities that one or more of the potential defects actually caused the integrated circuit failures are determined from diagnostic results produced using the fault dictionary. These probabilities are then reported. One or more of the following acts can be performed based at least in part on the reported probabilities: (a) adjusting one or more design manufacturing rules; (b) adjusting one or more defect extraction rules; or (c) providing recommended modifications of one or more features in the integrated circuit. See para 76- fault simulation/test pattern generating component (4712) (such as an automatic test pattern generation (ATPG) tool) can receive the extracted defects and operate to create one or more test patterns targeting the extracted defects. To generate the test patterns, the test pattern generating component (4712) can use a different representation of the integrated circuit, such as a netlist (4713). see para 99-101- A netlist description (for example, netlist (4713)) of a design can be modified to enable design-for-test procedures like test pattern generation, simulation, and fault simulation to support defect-based testing by adding or deleting gates, or by adding or deleting signal lines, or both. This analysis investigates if some of the DFM rules (1) from which the defect-extraction rules (3) were derived should be modified. This information can be used to improve the DFM rules, and thus the yield, for the current integrated circuit (e.g. by means of a redesign or a mask modification (27)). In addition, the improved DFM rules can lead to higher initial yield of the next design, which is based on the now-improved DFM rules. See para 164- Generate additional test patterns to cover defects that may not have been covered before. See para 152- The fault dictionary can comprise, for example, a table organized into rows, with each row containing data for a test pattern.)
and execute, using the additional test pattern, a test on the integrated circuit formed based on the modified circuit model having the one or more added logic components. (see para 153-It is assumed for purposes of this discussion that devices realizing the integrated circuit (5) have been tested using the test pattern set (17) as illustrated in Section III of FIG. 1. See para 0077 and fig 47--The integrated circuit design is manufactured (4705) and tested (4714) (for example, using a tester or ATE). During testing (4714), fail information for one or more integrated circuits can be recorded. The testing can be performed, for example, using the generated test patterns targeting the extracted defects.)
wherein execute the test comprises: generate input conditions according to the test pattern; apply the input conditions to electrical input pins of the fabricated physical integrated circuit formed from the modified circuit model, via an automated test system comprising signal generation hardware and measurement instrumentation; receive measured output electrical signals from the fabricated physical integrated circuit; and determine whether the fabricated physical integrated circuit is operating as designed based on the measured output electrical signals. (see para 0012- A set of test patterns is produced by: (a) selecting from previously generated test patterns one or more test patterns that detect at least some of the identified potential defects; (b) generating one or more test patterns that explicitly target at least some of the identified potential defects; or both (a) and (b). Test-result data can be received that comprises failing test responses obtained during testing of the integrated circuits using at least a portion of the test patterns in the set of test patterns. The at least one fault dictionary can be applied to the test-result data in order to diagnose potential defects associated with one or more of the failing test responses. see para 153-It is assumed for purposes of this discussion that devices realizing the integrated circuit (5) have been tested using the test pattern set (17) as illustrated in Section III of FIG. 1. Test result data (20) can be available either in real time (while production testing is still in progress) or from a database storing earlier test results. Section IV of FIG. 1 involves the processing and analysis of test-result data (21). A more detailed description of the analysis is provided in a separate section below. In general, however, the test-result analysis is performed to determine from the test result data (20) and the dictionary (16) which classes of defects have failed, and if possible, which individual defects See para 0077 and fig 47--The integrated circuit design is manufactured (4705) and tested (4714) (for example, using a tester or ATE). During testing (4714), fail information for one or more integrated circuits can be recorded. The testing can be performed, for example, using the generated test patterns targeting the extracted defects.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date
of the claimed invention to modify the method for diagnosing faults in an integrated logic circuit as disclosed by Wen to include wherein each virtual defect is an arbitrarily assigned identifier uniquely associated with one such set of input conditions; determine, in response to performing the detection, that at least one of the plurality of logic behavioral models is untested based on the detected at least one instance of the plurality of instances corresponding to the at least one of the plurality of logic behavioral models absent of the fault; modify, according to the reduced table, the circuit model by adding one or more logic components at input ports of the circuit model to adaptively configure input conditions, according to input conditions unable to detect fault associated with the at least one of the plurality of logic behavioral models that is untested; generate, according to the modification, a modified circuit model for physical implementation of the integrated circuit; generating an additional test pattern for the modified circuit model, wherein the additional test pattern is different from the plurality of existing test patterns and enables detection of unmodeled defects; and execute, using the test pattern, a test on the integrated circuit formed based on the modified circuit model having the one or more added logic components, wherein execute the test comprises: generating input conditions according to the test pattern; apply the input conditions to electrical input pins of the fabricated physical integrated circuit formed from the modified circuit model, via an automated test system comprising signal generation hardware and measurement instrumentation; receive measured output electrical signals from the fabricated physical integrated circuit; and determine whether the fabricated physical integrated circuit is operating as designed based on the measured output electrical signals as taught by Rajski in the system of Wen in order to reduce the number of defective chips being produced, foundries (integrated circuit manufacturers) often provide a number of recommended design rules that designers can use to help improve the yield of their particular design. Such rules are generally referred to herein as Design for Manufacturability (DFM) rules and can pertain to a wide variety of parameters related to integrated circuit design. (see para 0004, Rajski)
The combination of Wen and Rajski does not teach each virtual defect is assigned independent of, and without reference to, any modeled fault effect or any known or assumed physical characteristic, limitation, or defect of an integrated circuit physically formed according to the circuit model.
In the related field of invention, Sokar teaches each virtual defect is assigned independent of, and without reference to, any modeled fault effect or any known or assumed physical characteristic, limitation, or defect of an integrated circuit physically formed according to the circuit model. (see col 2 line 15-28- In one embodiment of the disclosure, a fault aware analog model (FAAM) system is disclosed. The FAAM system comprises a FAAM builder module comprising a model construction module configured to receive a reference dataset associated with a circuit block. In some embodiments, the reference dataset comprises a set of data values that defines input to output relationship of the circuit block for both in spec and out of spec operation of the circuit block, wherein the reference data set is derived based on data associated with a ground truth representation of the circuit block. The model construction module is further configured to generate a FAAM comprising a behavioral model of the circuit block, based on the reference dataset. In some embodiments, the FAAM is configured to approximate the input to output relationship of the circuit block that is defined by the set of data values in the reference dataset. See col 8 line 55-58- Simple Random Sampling (SRS) or Latin-Hypercube-Sampling (LHS), to form the set of input values to be utilized within the reference dataset. See col 6 line 29-31- In one embodiment, a method to develop a FAAM based on extending nominal models with out-of-spec behavior using the reference data set is disclosed. See col 11 line 33-40- Generally, the parametric model is not constructed based on physical assumptions and laws, but is rather fitted/trained based on the generated reference dataset, so that it represents the reference dataset as well as possible. Specifically, the plurality of model parameters is modified/trained based on the reference dataset, in order for the parametric model to approximate the input-output relationship defined by the reference dataset. See fig 3A (lookup table))
Examiner note: “Fault inputs” to the model where the faults originate exterior to the model itself, i.e. from the source blocks. These are the inputs which are irrespective of physical defects of the circuit model.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date
of the claimed invention to modify the method for diagnosing faults in an integrated logic circuit as disclosed by Wen to include each virtual defect is assigned independent of, and without reference to, any modeled fault effect or any known or assumed physical characteristic, limitation, or defect of an integrated circuit physically formed according to the circuit model as taught by Sokar in the system of Wen and Rajski in order develop data driven behavioral models that are fault-aware. Another motivation is to find defects such as hard defects (open and short circuits) and/or soft/parametric defects (change in a process parameter of a circuit element), that are present in the circuit due to unintended production errors or post-manufacturing mishandling. Thus, it provides the probabilities that the Integrated Circuit (IC) does or does not contain a fault, given that the test program has pass. (see col 1 line 5-25, Sokar)
Regarding claim 18
Wen teaches a non-transitory computer readable medium storing instruction when executed by one or more processors cause the one or more processors to: (see para 151 and claim 26-Note that the above-mentioned flowcharts of FIGS. 5, 6 and 11 can be stored in an ROM or another nonvolatile memory or in a random access memory or another volatile memory.)
generate a table of a circuit model, the table including a plurality of logic behavioral models of the circuit model, each of the plurality of logic behavioral models including a corresponding set of input conditions, a corresponding output result, and a corresponding virtual defect, ( see [005]- a dynamic defect changes its behavior for different input vectors because the strength of a signal can vary for different input conditions. Finally, a circuit may contain a single defect or multiple defects. see para 18-24- A fanout-free gate has one X-fault, corresponding to any physical defect or defects in the gate or on its output. The X-fault model handles the unknown faulty behavior of a complex defect such as a Byzantine defect with different X symbols. The X-fault model allows a fault to have different faulty behaviors under different input vectors, making it suitable for the per-test fault diagnosis scheme in handling dynamic defects. see para 57-60 and fig 4A-4B- In FIG. 3, which illustrates an example of the X-fault model, in accordance with the present invention, X1 and X2 denote two arbitrary faulty logic values. Therefore, the fanout X-fault model can closely represent such complex defects as Byzantine defects. In FIG. 4A, which illustrates an example of an integrated logic circuit unit 1, this integrated logic circuit unit 1 is formed by gates G1, G2, G3 and G4, five input signal lines I1, I2, . . . , I5 and three output signal-lines O1, O2 and O3. In this case, if the integrated logic circuit unit 1 is normally operated under the condition that an input vector VEC is applied to the input signal lines I1, I2, . . . , I5, an expected output response EXO is obtained at the output signal lines O1, O2 and O3. An example of the relationship between the input vector VEC and the expected output response EXO is illustrated in FIG. 4B. Note that, in FIG. 4A, an input vector VECi=(0, 1, 1, 0, 1) is applied as the input vector VEC to the input signal lines I1, I2, . . . , I5, and its resulting expected output response EXO=(1, 0, 1) is obtained. see para 95- Steps 1104 to 1110 perform a matching operation between the above-mentioned simulated output response SHO (Pk) and the observed output response OBO to obtain fault diagnosis values p(FVEC, Gi). In this case, since the fault diagnosis values p(FVEC, Gi) are calculated in consideration of an error rate and a fault level, each of the fault diagnosis values p(FVEC, Gi) varies from 0 to 1. Note that the fault diagnosis values (matching values) of the prior art per-test fault diagnosis method were 1 (coincidence) or 0 (incoincidence). see fig 14 fault diagnosis table and para 130- That is, all essential faults are extracted and excluded from the fault diagnosis table to change it to a target diagnosis table. Note that one essential fault is defined by a fault such that an entry in the fault diagnosis table is the only non-zero entry in the corresponding row (failing input vector) and the corresponding column (faulty gate). The essential faults are indispensable in the multiplet. If there is no essential fault, the target diagnosis table is the same as the original diagnosis table.)
Examiner note: In digital circuit testing, input conditions with faulty gates correspond to "virtual defects" through fault modeling. Faulty gate corresponds to a virtual defect. A stuck-at fault assumes that a signal line in a circuit is permanently fixed at a logical '0' or a logical '1', regardless of the inputs to the circuit. This is a behavioral, or logical, description of a defect and largely irrespective of the physical characteristics of a specific integrated circuit (IC). This logical modeling approach is a fundamental principle of digital circuit testing.
simulate, according to one or more test patterns associated with a circuit model, a plurality of instances of the circuit model according to the table comprising logic gates, wherein simulating the plurality of instances of the circuit model comprises applying a plurality of existing test patterns, each associated with the corresponding virtual defect, to the circuit model to simulate behavior of the logic gates, (see para 002- The present invention relates to a method and apparatus for carrying out fault diagnosis for integrated logic circuits (or “circuits” hereafter), to achieve high diagnostic resolution even in the presence of complex, dynamic, and/or multiple defects, all inevitable in deep-submicron circuits. see para 57-60 and fig 4A-4B- In the above-mentioned prior art per-test fault diagnosis method, however, as explained above, the accuracy is low for a circuit with complex defects, since a misdiagnosis may occur for a Byzantine defect such as a resistive short or open which shows a plurality of logical behaviors as illustrated in FIGS. 1 and 2. In FIG. 3, which illustrates an example of the X-fault model, in accordance with the present invention, X1 and X2 denote two arbitrary faulty logic values. Therefore, the fanout X-fault model can closely represent such complex defects as Byzantine defects. In FIG. 4A, which illustrates an example of an integrated logic circuit unit 1, this integrated logic circuit unit 1 is formed by gates G1, G2, G3 and G4, five input signal lines I1, I2, . . . , I5 and three output signal-lines O1, O2 and O3. In this case, if the integrated logic circuit unit 1 is normally operated under the condition that an input vector VEC is applied to the input signal lines I1, I2, . . . , I5, an expected output response EXO is obtained at the output signal lines O1, O2 and O3. An example of the relationship between the input vector VEC and the expected output response EXO is illustrated in FIG. 4B. Note that, in FIG. 4A, an input vector VECi=(0, 1, 1, 0, 1) is applied as the input vector VEC to the input signal lines I1, I2, . . . , I5, and its resulting expected output response EXO=(1, 0, 1) is obtained.)
Examiner note: Examiner consider the input vector as a test pattern which is a set of specific inputs provided to a system to verify its behavior and functionality.
generating a plurality of simulation outputs in response to applying the plurality of existing test patterns; (See para 60 and fig 4A-4B-In FIG. 4A, which illustrates an example of an integrated logic circuit unit 1, this integrated logic circuit unit 1 is formed by gates G1, G2, G3 and G4, five input signal lines I1, I2, . . . , I5 and three output signal-lines O1, O2 and O3. In this case, if the integrated logic circuit unit 1 is normally operated under the condition that an input vector VEC is applied to the input signal lines I1, I2, . . . , I5, an expected output response EXO is obtained at the output signal lines O1, O2 and O3. An example of the relationship between the input vector VEC and the expected output response EXO is illustrated in FIG. 4B. Note that, in FIG. 4A, an input vector VECi=(0, 1, 1, 0, 1) is applied as the input vector VEC to the input signal lines I1, I2, . . . , I5, and its resulting expected output response EXO=(1, 0, 1) is obtained. See also para 83)
compare each of the plurality of simulation outputs to a vector from the plurality of logic behavioral models in the table; (See para 26-30-All previous per-test fault diagnosis methods use a strict matching criterion, in which a fault simulation result for a fault in a circuit model is compared with the corresponding observed response of the real circuit at all primary outputs under a failing vector. This often results in a mismatch, which leads to lower diagnostic resolution. In the present invention three factors, i.e. the matching information, the number of matched errors, and the depth of a fault, are all used in per-test fault diagnosis. A diagnosis value is calculated for each fault based on the three factors. Generally, the diagnosis value for a fault under a failing input vector is zero if the fault-simulation result and its corresponding circuit response does not match for the fault and the failing input vector. See fig 11 and see para 90-92- First, at step 1101, a difference vector DEP is calculated by an exclusive OR operation between the bits of an observed output response OBO at the output signal lines O.sub.1, O.sub.2 and O.sub.3 of the integrated logic circuit unit 1 and the corresponding bits of its expected output response EXO. Next, at step 1102, it is determined whether |DEF| is 0. As a result, when |DEF| is 0, this means that the observed output response OBO coincides with the expected-output response EPO, i.e., no fault is generated)
detect one instance of the plurality of instances of the circuit model, the one instance simulated with a set of input conditions of a logic behavioral model from the table and rendered a fault result different from its corresponding output result; (See para 26-30-All previous per-test fault diagnosis methods use a strict matching criterion, in which a fault simulation result for a fault in a circuit model is compared with the corresponding observed response of the real circuit at all primary outputs under a failing vector. This often results in a mismatch, which leads to lower diagnostic resolution. In the present invention three factors, i.e. the matching information, the number of matched errors, and the depth of a fault, are all used in per-test fault diagnosis. A diagnosis value is calculated for each fault based on the three factors. Generally, the diagnosis value for a fault under a failing input vector is zero if the fault-simulation result and its corresponding circuit response does not match for the fault and the failing input vector.)
Examiner note: According to the instant specification [0037]one or more behavioral models with sets of input conditions unable to detect any fault as an untested behavioral model. Step 1102 determines no fault for one or more behavioral models (VEC) with sets of input conditions when the |DEF| is 0.
detect, in response to a match between at least one simulation output and the vector, at least one instance of one other instance of the plurality of plurality of instances of the circuit model is untested based on the at least one other instance of the plurality of instances corresponding to another logic behavioral model absent of the fault; (See para 26-30-All previous per-test fault diagnosis methods use a strict matching criterion, in which a fault simulation result for a fault in a circuit model is compared with the corresponding observed response of the real circuit at all primary outputs under a failing vector. This often results in a mismatch, which leads to lower diagnostic resolution. In the present invention three factors, i.e. the matching information, the number of matched errors, and the depth of a fault, are all used in per-test fault diagnosis. A diagnosis value is calculated for each fault based on the three factors. Generally, the diagnosis value for a fault under a failing input vector is zero if the fault-simulation result and its corresponding circuit response does not match for the fault and the failing input vector. If the fault-simulation result and its corresponding circuit response match, the diagnosis value for the fault under the failing input vector is a value greater than zero, and the value is calculated based on the number of matched errors and the depth of a fault. See fig 11 and see para 90-92- First, at step 1101, a difference vector DEP is calculated by an exclusive OR operation between the bits of an observed output response OBO at the output signal lines O.sub.1, O.sub.2 and O.sub.3 of the integrated logic circuit unit 1 and the corresponding bits of its expected output response EXO. Next, at step 1102, it is determined whether |DEF| is 0. As a result, when |DEF| is 0, this means that the observed output response OBO coincides with the expected-output response EPO, i.e., no fault is generated. see para 130-131- That is, all essential faults are extracted and excluded from the fault diagnosis table to change it to a target diagnosis table. Note that one essential fault is defined by a fault such that an entry in the fault diagnosis table is the only non-zero entry in the corresponding row (failing input vector) and the corresponding column (faulty gate). The essential faults are indispensable in the multiplet. If there is no essential fault, the target diagnosis table is the same as the original diagnosis table. In FIG. 14, the faulty gate G5 is an essential fault. Therefore, the faulty gate G5 is excluded from the original fault diagnosis table.)
Examiner note: According to the instant specification [0037]one or more behavioral models with sets of input conditions unable to detect any fault as an untested behavioral model. Step 1102 determines no fault for one or more behavioral models (VEC) with sets of input conditions when the |DEF| is 0. By removing essential faults (faults uniquely detected by a specific input vector/gate combo), the remaining "target diagnosis table" represents a reduced model that excludes those specific faults. Therefore, the new target table models a state that is absent of those faults, and because those essential faults are no longer part of the diagnosis set, they are effectively untested in the context of the new, reduced diagnosis table.
exclude the logic behavioral model from the table of the circuit model according to the detected one instance. (See para 005- Fault diagnosis is the process of identifying suspicious areas in a failing circuit by making use of logical faults assumed in a circuit model. A logical fault has two attributes: location and logical behavior. In a gate-level circuit model, the location attribute is one or more nets or pins, and the logical behavior attribute is one or more logic values. Fault modeling defines these attributes in a general manner. The process of identifying faults, with likely link to physical defects, is known as fault diagnosis.
Wen does not teach wherein each virtual defect is an arbitrarily assigned identifier uniquely associated with one such set of input conditions and is assigned independent of, and without reference to, any modeled fault effect or any known or assumed physical characteristic, limitation, or defect of an integrated circuit physically formed according to the circuit model; determine, in response to performing the detection, that at least one of the plurality of logic behavioral models is untested based on the detected at least one instance of the plurality of instances corresponding to the at least one of the plurality of logic behavioral models absent of the fault; modify, according to the reduced table, the circuit model by adding one or more logic components at input ports of the circuit model to adaptively configure input conditions, according to input conditions unable to detect fault associated with the at least one of the plurality of logic behavioral models that is untested; generate, according to the modification, a modified circuit model for physical implementation of the integrated circuit; generate an additional test pattern for the modified circuit model, wherein the additional test pattern is different from the plurality of existing test patterns and enables detection of unmodeled defects; and execute, using the test pattern, a test on the integrated circuit formed based on the modified circuit model having the one or more added logic components, wherein execute the test comprises: generate input conditions according to the test pattern; apply the input conditions to electrical input pins of the fabricated physical integrated circuit formed from the modified circuit model, via an automated test system comprising signal generation hardware and measurement instrumentation; receive measured output electrical signals from the fabricated physical integrated circuit; and determine whether the fabricated physical integrated circuit is operating as designed based on the measured output electrical signals.
In the related field of invention, Rajski teaches wherein each virtual defect is an arbitrarily assigned identifier uniquely associated with one such set of input conditions (see para 130-131-An extracted defect can be defined by the data describing the actual defect, like location and physical properties. Additional data can be associated with each defect. For example, in one exemplary implementation, the defects in the list (9) have one, some, or all of the following additional properties: 1. A unique identifier. See para 256- Therefore, according to one embodiment, the size of the fault dictionary can be reduced by assigning one unique ID for each unique observation point combination. See also para 188)
determine, in response to performing the detection, that at least one of the plurality of logic behavioral models is untested based on the detected at least one instance of the plurality of instances corresponding to the at least one of the plurality of logic behavioral models absent of the fault; (see para 0008- In some embodiments of the disclosed method, the existence of at least one potential defect not found in the generated dictionary can also be diagnosed (for example, using incremental diagnosis or incremental simulation). see para 154-155- In general, however, the test-result analysis is performed to determine from the test result data (20) and the dictionary (16) which classes of defects have failed, and if possible, which individual defects. FIG. 31 is a block diagram showing an exemplary manner in which the processing (21) can be performed. Process (21.1) is performed to try to identify the defect, respectively the class or subclass of the defect, which can best explain the failing behavior of the integrated circuit. FIG. 39 also shows a comparison of the two associated step functions indicating the number of expected and observed defects, respectively, for each subclass of defect. See para 164- Generate additional test patterns to cover defects that may not have been covered before. See para 208- In case the ATPG (13.3.1.2) determines faults to be untestable, it can update the fault list (A) and the dictionary (B), using an updating procedure (13.3.1.5). Otherwise, the ATPG (13.3.1.2) can make the generated test-pattern candidate available for defect simulation (13.3.1.3))
modify, according to the reduced table, the circuit model, by adding one or more logic components at input ports of the circuit model to adaptively configure input conditions, according to input conditions unable to detect fault associated with the at least one of the plurality of logic behavioral models that is untested; (see para 14-In some embodiments, probabilities that one or more of the potential defects actually caused the integrated circuit failures are determined from diagnostic results produced using the fault dictionary. These probabilities are then reported. One or more of the following acts can be performed based at least in part on the reported probabilities: (a) adjusting one or more design manufacturing rules; (b) adjusting one or more defect extraction rules; or (c) providing recommended modifications of one or more features in the integrated circuit. see para 99-101- A netlist description (for example, netlist (4713)) of a design can be modified to enable design-for-test procedures like test pattern generation, simulation, and fault simulation to support defect-based testing by adding or deleting gates, or by adding or deleting signal lines, or both. This analysis investigates if some of the DFM rules (1) from which the defect-extraction rules (3) were derived should be modified. This information can be used to improve the DFM rules, and thus the yield, for the current integrated circuit (e.g. by means of a redesign or a mask modification (27)). In addition, the improved DFM rules can lead to higher initial yield of the next design, which is based on the now-improved DFM rules. See para 255- For illustrative purposes, this discussion makes reference to FIG. 46, which shows an exemplary fanout-free region embedded in a circuit. The exemplary region comprises one NAND gate and one OR gate. Signal s is termed the “stem” of this fanout-free region, and signal lines a, b, c, and d are internal signals. For illustrative purposes only, assume that only combinational test pattern sets are used to test this circuit.)
generate, according to the modification, a modified circuit model for physical implementation of an integrated circuit; (see para 14-In some embodiments, probabilities that one or more of the potential defects actually caused the integrated circuit failures are determined from diagnostic results produced using the fault dictionary. These probabilities are then reported. One or more of the following acts can be performed based at least in part on the reported probabilities: (a) adjusting one or more design manufacturing rules; (b) adjusting one or more defect extraction rules; or (c) providing recommended modifications of one or more features in the integrated circuit. In some embodiments, the fault dictionary is a compressed fault dictionary using one or more bit masks to associate one or more failing test responses to respective potential defects. See para 101- This analysis investigates if some of the DFM rules (1) from which the defect-extraction rules (3) were derived should be modified. This information can be used to improve the DFM rules, and thus the yield, for the current integrated circuit (e.g. by means of a redesign or a mask modification (27)).)
generate an additional test pattern for the modified circuit model, wherein the additional test pattern is different from the plurality of existing test patterns and enables detection of unmodeled defects; (see para 0008- In some embodiments of the disclosed method, the existence of at least one potential defect not found in the generated dictionary can also be diagnosed (for example, using incremental diagnosis or incremental simulation). and see para 14-In some embodiments, probabilities that one or more of the potential defects actually caused the integrated circuit failures are determined from diagnostic results produced using the fault dictionary. These probabilities are then reported. One or more of the following acts can be performed based at least in part on the reported probabilities: (a) adjusting one or more design manufacturing rules; (b) adjusting one or more defect extraction rules; or (c) providing recommended modifications of one or more features in the integrated circuit. See para 76- fault simulation/test pattern generating component (4712) (such as an automatic test pattern generation (ATPG) tool) can receive the extracted defects and operate to create one or more test patterns targeting the extracted defects. To generate the test patterns, the test pattern generating component (4712) can use a different representation of the integrated circuit, such as a netlist (4713). see para 99-101- A netlist description (for example, netlist (4713)) of a design can be modified to enable design-for-test procedures like test pattern generation, simulation, and fault simulation to support defect-based testing by adding or deleting gates, or by adding or deleting signal lines, or both. This analysis investigates if some of the DFM rules (1) from which the defect-extraction rules (3) were derived should be modified. This information can be used to improve the DFM rules, and thus the yield, for the current integrated circuit (e.g. by means of a redesign or a mask modification (27)). In addition, the improved DFM rules can lead to higher initial yield of the next design, which is based on the now-improved DFM rules. See para 164- Generate additional test patterns to cover defects that may not have been covered before. See para 152- The fault dictionary can comprise, for example, a table organized into rows, with each row containing data for a test pattern.)
and execute, using the additional test pattern, a test on the integrated circuit formed based on the modified circuit model having the one or more added logic components. (see para 153-It is assumed for purposes of this discussion that devices realizing the integrated circuit (5) have been tested using the test pattern set (17) as illustrated in Section III of FIG. 1. See para 0077 and fig 47--The integrated circuit design is manufactured (4705) and tested (4714) (for example, using a tester or ATE). During testing (4714), fail information for one or more integrated circuits can be recorded. The testing can be performed, for example, using the generated test patterns targeting the extracted defects.)
wherein execute the test comprises: generate input conditions according to the test pattern; apply the input conditions to electrical input pins of the fabricated physical integrated circuit formed from the modified circuit model, via an automated test system comprising signal generation hardware and measurement instrumentation; receive measured output electrical signals from the fabricated physical integrated circuit; and determine whether the fabricated physical integrated circuit is operating as designed based on the measured output electrical signals. (see para 0012- A set of test patterns is produced by: (a) selecting from previously generated test patterns one or more test patterns that detect at least some of the identified potential defects; (b) generating one or more test patterns that explicitly target at least some of the identified potential defects; or both (a) and (b). Test-result data can be received that comprises failing test responses obtained during testing of the integrated circuits using at least a portion of the test patterns in the set of test patterns. The at least one fault dictionary can be applied to the test-result data in order to diagnose potential defects associated with one or more of the failing test responses. see para 153-It is assumed for purposes of this discussion that devices realizing the integrated circuit (5) have been tested using the test pattern set (17) as illustrated in Section III of FIG. 1. Test result data (20) can be available either in real time (while production testing is still in progress) or from a database storing earlier test results. Section IV of FIG. 1 involves the processing and analysis of test-result data (21). A more detailed description of the analysis is provided in a separate section below. In general, however, the test-result analysis is performed to determine from the test result data (20) and the dictionary (16) which classes of defects have failed, and if possible, which individual defects See para 0077 and fig 47--The integrated circuit design is manufactured (4705) and tested (4714) (for example, using a tester or ATE). During testing (4714), fail information for one or more integrated circuits can be recorded. The testing can be performed, for example, using the generated test patterns targeting the extracted defects.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date
of the claimed invention to modify the method for diagnosing faults in an integrated logic circuit as disclosed by Wen to include wherein each virtual defect is an arbitrarily assigned identifier uniquely associated with one such set of input conditions; determine, in response to performing the detection, that at least one of the plurality of logic behavioral models is untested based on the detected at least one instance of the plurality of instances corresponding to the at least one of the plurality of logic behavioral models absent of the fault; modify, according to the reduced table, the circuit model by adding one or more logic components at input ports of the circuit model to adaptively configure input conditions, according to input conditions unable to detect fault associated with the at least one of the plurality of logic behavioral models that is untested; generate, according to the modification, a modified circuit model for physical implementation of the integrated circuit; generating an additional test pattern for the modified circuit model, wherein the additional test pattern is different from the plurality of existing test patterns and enables detection of unmodeled defects; and execute, using the test pattern, a test on the integrated circuit formed based on the modified circuit model having the one or more added logic components, wherein execute the test comprises: generating input conditions according to the test pattern; apply the input conditions to electrical input pins of the fabricated physical integrated circuit formed from the modified circuit model, via an automated test system comprising signal generation hardware and measurement instrumentation; receive measured output electrical signals from the fabricated physical integrated circuit; and determine whether the fabricated physical integrated circuit is operating as designed based on the measured output electrical signals as taught by Rajski in the system of Wen in order to reduce the number of defective chips being produced, foundries (integrated circuit manufacturers) often provide a number of recommended design rules that designers can use to help improve the yield of their particular design. Such rules are generally referred to herein as Design for Manufacturability (DFM) rules and can pertain to a wide variety of parameters related to integrated circuit design. (see para 0004, Rajski)
The combination of Wen and Rajski does not teach each virtual defect is assigned independent of, and without reference to, any modeled fault effect or any known or assumed physical characteristic, limitation, or defect of an integrated circuit physically formed according to the circuit model.
In the related field of invention, Sokar teaches each virtual defect is assigned independent of, and without reference to, any modeled fault effect or any known or assumed physical characteristic, limitation, or defect of an integrated circuit physically formed according to the circuit model. (see col 2 line 15-28- In one embodiment of the disclosure, a fault aware analog model (FAAM) system is disclosed. The FAAM system comprises a FAAM builder module comprising a model construction module configured to receive a reference dataset associated with a circuit block. In some embodiments, the reference dataset comprises a set of data values that defines input to output relationship of the circuit block for both in spec and out of spec operation of the circuit block, wherein the reference data set is derived based on data associated with a ground truth representation of the circuit block. The model construction module is further configured to generate a FAAM comprising a behavioral model of the circuit block, based on the reference dataset. In some embodiments, the FAAM is configured to approximate the input to output relationship of the circuit block that is defined by the set of data values in the reference dataset. See col 8 line 55-58- Simple Random Sampling (SRS) or Latin-Hypercube-Sampling (LHS), to form the set of input values to be utilized within the reference dataset. See col 6 line 29-31- In one embodiment, a method to develop a FAAM based on extending nominal models with out-of-spec behavior using the reference data set is disclosed. See col 11 line 33-40- Generally, the parametric model is not constructed based on physical assumptions and laws, but is rather fitted/trained based on the generated reference dataset, so that it represents the reference dataset as well as possible. Specifically, the plurality of model parameters is modified/trained based on the reference dataset, in order for the parametric model to approximate the input-output relationship defined by the reference dataset. See fig 3A (lookup table))
Examiner note: “Fault inputs” to the model where the faults originate exterior to the model itself, i.e. from the source blocks. These are the inputs which are irrespective of physical defects of the circuit model.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date
of the claimed invention to modify the method for diagnosing faults in an integrated logic circuit as disclosed by Wen to include each virtual defect is assigned independent of, and without reference to, any modeled fault effect or any known or assumed physical characteristic, limitation, or defect of an integrated circuit physically formed according to the circuit model as taught by Sokar in the system of Wen and Rajski in order develop data driven behavioral models that are fault-aware. Another motivation is to find defects such as hard defects (open and short circuits) and/or soft/parametric defects (change in a process parameter of a circuit element), that are present in the circuit due to unintended production errors or post-manufacturing mishandling. Thus, it provides the probabilities that the Integrated Circuit (IC) does or does not contain a fault, given that the test program has pass. (see col 1 line 5-25, Sokar)
Regarding claim 4, 13 and 21
Wen further teaches wherein the test pattern or the additional test pattern includes a vector of two or more different sets of the plurality of sets of input conditions. (see para 60- In FIG. 4A, which illustrates an example of an integrated logic circuit unit 1, this integrated logic circuit unit 1 is formed by gates G1, G2, G3 and G4, five input signal lines I1, I2, . . . , I5 and three output signal-lines O1, O2 and O3. In this case, if the integrated logic circuit unit 1 is normally operated under the condition that an input vector VEC is applied to the input signal lines I1, I2, . . . , I5, an expected output response EXO is obtained at the output signal lines O1, O2 and O3. An example of the relationship between the input vector VEC and the expected output response EXO is illustrated in FIG. 4B. Note that, in FIG. 4A, an input vector VECi=(0, 1, 1, 0, 1) is applied as the input vector VEC to the input signal lines I1, I2, . . . , I5, and its resulting expected output response EXO=(1, 0, 1) is obtained.)
Regarding claim 5
Wen further teaches generating a reduced table of the circuit model according to the fault detection simulation (see para 005- Fault diagnosis is the process of identifying suspicious areas in a failing circuit by making use of logical faults assumed in a circuit model. A logical fault has two attributes: location and logical behavior. In a gate-level circuit model, the location attribute is one or more nets or pins, and the logical behavior attribute is one or more logic values. Fault modeling defines these attributes in a general manner. The process of identifying faults, with likely link to physical defects, is known as fault diagnosis. see para 130-131- That is, all essential faults are extracted and excluded from the fault diagnosis table to change it to a target diagnosis table. Note that one essential fault is defined by a fault such that an entry in the fault diagnosis table is the only non-zero entry in the corresponding row (failing input vector) and the corresponding column (faulty gate). The essential faults are indispensable in the multiplet. If there is no essential fault, the target diagnosis table is the same as the original diagnosis table. In FIG. 14, the faulty gate G5 is an essential fault. Therefore, the faulty gate G5 is excluded from the original fault diagnosis table.)
Wen does not teach executing the fault detection simulation of the circuit model according to one or more different test patterns associated with the circuit model; wherein the test pattern is generated based on the reduced table of the circuit model.
However, Rajski further teaches executing the fault detection simulation of the circuit model according to one or more different test patterns associated with the circuit model; wherein the test pattern is generated based on the reduced table of the circuit model. (See para 152- For purposes of this discussion, it is assumed that a fault dictionary (16) is generated together with the pattern set. The fault dictionary can comprise, for example, a table organized into rows, with each row containing data for a test pattern. See para 164-165- 4. Generate additional test patterns to better cover the identified problem with higher resolution 5. Generate additional test patterns to cover defects that may not have been covered before)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date
of the claimed invention to modify the method for diagnosing faults in an integrated logic circuit as disclosed by Wen to include executing the fault detection simulation of the circuit model according to one or more different test patterns associated with the circuit model; wherein the test pattern is generated based on the reduced table of the circuit model as taught by Rajski in the system of Wen and Sokar in order to reduce the number of defective chips being produced, foundries (integrated circuit manufacturers) often provide a number of recommended design rules that designers can use to help improve the yield of their particular design. Such rules are generally referred to herein as Design for Manufacturability (DFM) rules and can pertain to a wide variety of parameters related to integrated circuit design. (see para 0004, Rajski)
Regarding claim 6 and 14
Wen further teaches detecting one instance of the plurality of instances of the circuit model, the one instance simulated with a set of input conditions of a logic behavioral model from the table and rendered a fault result different from the corresponding output result. (See para 26-30-All previous per-test fault diagnosis methods use a strict matching criterion, in which a fault simulation result for a fault in a circuit model is compared with the corresponding observed response of the real circuit at all primary outputs under a failing vector. This often results in a mismatch, which leads to lower diagnostic resolution. In the present invention three factors, i.e. the matching information, the number of matched errors, and the depth of a fault, are all used in per-test fault diagnosis. A diagnosis value is calculated for each fault based on the three factors. Generally, the diagnosis value for a fault under a failing input vector is zero if the fault-simulation result and its corresponding circuit response does not match for the fault and the failing input vector.)
However, Wen does not teach wherein executing the fault detection simulation of the circuit model includes: simulating the plurality of instances of the circuit model according to the one or more different test patterns associated with the circuit model.
However, Rajski further teaches wherein executing the fault detection simulation of the circuit model includes: simulating the plurality of instances of the circuit model according to the one or more different test patterns associated with the circuit model. (see para 185 -For example, the original test pattern set (11) can be simulated in order to determine an initial classification of the defects. See para 208-212- In case the ATPG (13.3.1.2) determines faults to be untestable, it can update the fault list (A) and the dictionary (B), using an updating procedure (13.3.1.5). Otherwise, the ATPG (13.3.1.2) can make the generated test-pattern candidate available for defect simulation (13.3.1.3). For the selected set of target faults, the ATPG (13.3.1.2.2) tries to satisfy the task defined in target defect set and ATPG task (13.3.1.1.4). In case the task requires distinguishing between two or more defects, the ATPG has several options. For example, it can block the fault effect propagation for some of them, allowing only the others to be detected, or it can propagate the fault effect to different observation points. If successful, the ATPG procedure (13.3.1.2.2) computes a test pattern candidate (13.3.1.2.3), which, as shown in FIG. 23, can be defect simulated (13.3.1.3). Note that this simulation is different from regular fault simulation, since the fault simulator does not need to update the fault list (A) because it does not know yet if the pattern candidate (13.3.1.2.3) will be accepted for addition into the test-pattern set. Therefore, in one implementation, the defect simulation procedure (13.3.1.3) stores the simulated responses (13.3.1.3.1) of the candidate test pattern for later evaluation. This evaluation can be performed, for example, by the response analysis procedure (13.3.1.4) shown in FIG. 24. At this point, it is already known that the pattern generation was at least in part a success.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date
of the claimed invention to modify the method for diagnosing faults in an integrated logic circuit as disclosed by Wen to include wherein executing the fault detection simulation of the circuit model includes: simulating the plurality of instances of the circuit model according to the one or more different test patterns associated with the circuit model as taught by Rajski in the system of Wen and Sokar in order to reduce the number of defective chips being produced, foundries (integrated circuit manufacturers) often provide a number of recommended design rules that designers can use to help improve the yield of their particular design. Such rules are generally referred to herein as Design for Manufacturability (DFM) rules and can pertain to a wide variety of parameters related to integrated circuit design. (see para 0004, Rajski)
Regarding claim 7 and 15
Wen further teaches wherein generating the reduced table of the circuit model according to the fault detection simulation includes: excluding, from the plurality of logic behavioral models in the table, the logic behavioral model applied to the one instance and rendered the fault result. (see para 005- Fault diagnosis is the process of identifying suspicious areas in a failing circuit by making use of logical faults assumed in a circuit model. A logical fault has two attributes: location and logical behavior. In a gate-level circuit model, the location attribute is one or more nets or pins, and the logical behavior attribute is one or more logic values. Fault modeling defines these attributes in a general manner. The process of identifying faults, with likely link to physical defects, is known as fault diagnosis. see para 130-131- That is, all essential faults are extracted and excluded from the fault diagnosis table to change it to a target diagnosis table. Note that one essential fault is defined by a fault such that an entry in the fault diagnosis table is the only non-zero entry in the corresponding row (failing input vector) and the corresponding column (faulty gate). The essential faults are indispensable in the multiplet. If there is no essential fault, the target diagnosis table is the same as the original diagnosis table. In FIG. 14, the faulty gate G5 is an essential fault. Therefore, the faulty gate G5 is excluded from the original fault diagnosis table.)
Regarding claim 8 and 16
Wen further teaches detecting one instance of the plurality of instances of the circuit model, the one instance simulated with a set of input conditions of a logic behavioral model from the table and rendered a fault result different from the corresponding output result, wherein the logic behavioral model is determined to be one of one or more of the plurality of logic behavioral models. (See para 26-30-All previous per-test fault diagnosis methods use a strict matching criterion, in which a fault simulation result for a fault in a circuit model is compared with the corresponding observed response of the real circuit at all primary outputs under a failing vector. This often results in a mismatch, which leads to lower diagnostic resolution. In the present invention three factors, i.e. the matching information, the number of matched errors, and the depth of a fault, are all used in per-test fault diagnosis. A diagnosis value is calculated for each fault based on the three factors. Generally, the diagnosis value for a fault under a failing input vector is zero if the fault-simulation result and its corresponding circuit response does not match for the fault and the failing input vector.)
However, Wen does not teach wherein executing the fault detection simulation of the circuit model includes: simulating the plurality of instances of the circuit model according to the one or more different test patterns associated with the circuit model.
However, Rajski further teaches wherein executing the fault detection simulation of the circuit model includes: simulating the plurality of instances of the circuit model according to the one or more different test patterns associated with the circuit model. (see para 185 -For example, the original test pattern set (11) can be simulated in order to determine an initial classification of the defects. See para 208-212- In case the ATPG (13.3.1.2) determines faults to be untestable, it can update the fault list (A) and the dictionary (B), using an updating procedure (13.3.1.5). Otherwise, the ATPG (13.3.1.2) can make the generated test-pattern candidate available for defect simulation (13.3.1.3). For the selected set of target faults, the ATPG (13.3.1.2.2) tries to satisfy the task defined in target defect set and ATPG task (13.3.1.1.4). In case the task requires distinguishing between two or more defects, the ATPG has several options. For example, it can block the fault effect propagation for some of them, allowing only the others to be detected, or it can propagate the fault effect to different observation points. If successful, the ATPG procedure (13.3.1.2.2) computes a test pattern candidate (13.3.1.2.3), which, as shown in FIG. 23, can be defect simulated (13.3.1.3). Note that this simulation is different from regular fault simulation, since the fault simulator does not need to update the fault list (A) because it does not know yet if the pattern candidate (13.3.1.2.3) will be accepted for addition into the test-pattern set. Therefore, in one implementation, the defect simulation procedure (13.3.1.3) stores the simulated responses (13.3.1.3.1) of the candidate test pattern for later evaluation. This evaluation can be performed, for example, by the response analysis procedure (13.3.1.4) shown in FIG. 24. At this point, it is already known that the pattern generation was at least in part a success.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date
of the claimed invention to modify the method for diagnosing faults in an integrated logic circuit as disclosed by Wen to include wherein executing the fault detection simulation of the circuit model includes: simulating the plurality of instances of the circuit model according to the one or more different test patterns associated with the circuit model as taught by Rajski in the system of Wen and Sokar in order to reduce the number of defective chips being produced, foundries (integrated circuit manufacturers) often provide a number of recommended design rules that designers can use to help improve the yield of their particular design. Such rules are generally referred to herein as Design for Manufacturability (DFM) rules and can pertain to a wide variety of parameters related to integrated circuit design. (see para 0004, Rajski)
Regarding claim 9 and 17
Wen further teaches wherein generating the reduced table of the circuit model according to the fault detection simulation includes: excluding, from the plurality of logic behavioral models in the table, the logic behavioral model applied to the plurality of instances of the circuit model and rendered the fault result. (See para 005- Fault diagnosis is the process of identifying suspicious areas in a failing circuit by making use of logical faults assumed in a circuit model. A logical fault has two attributes: location and logical behavior. In a gate-level circuit model, the location attribute is one or more nets or pins, and the logical behavior attribute is one or more logic values. Fault modeling defines these attributes in a general manner. The process of identifying faults, with likely link to physical defects, is known as fault diagnosis. see para 130-131- That is, all essential faults are extracted and excluded from the fault diagnosis table to change it to a target diagnosis table. Note that one essential fault is defined by a fault such that an entry in the fault diagnosis table is the only non-zero entry in the corresponding row (failing input vector) and the corresponding column (faulty gate). The essential faults are indispensable in the multiplet. If there is no essential fault, the target diagnosis table is the same as the original diagnosis table. In FIG. 14, the faulty gate G5 is an essential fault. Therefore, the faulty gate G5 is excluded from the original fault diagnosis table.)
Regarding claim 10
Wen further teaches simulating the plurality of instances of the circuit model according to the test pattern; (see para 002- The present invention relates to a method and apparatus for carrying out fault diagnosis for integrated logic circuits (or “circuits” hereafter), to achieve high diagnostic resolution even in the presence of complex, dynamic, and/or multiple defects, all inevitable in deep-submicron circuits. see para 57-60 and fig 4A-4B- In the above-mentioned prior art per-test fault diagnosis method, however, as explained above, the accuracy is low for a circuit with complex defects, since a misdiagnosis may occur for a Byzantine defect such as a resistive short or open which shows a plurality of logical behaviors as illustrated in FIGS. 1 and 2. In FIG. 3, which illustrates an example of the X-fault model, in accordance with the present invention, X1 and X2 denote two arbitrary faulty logic values. Therefore, the fanout X-fault model can closely represent such complex defects as Byzantine defects. In FIG. 4A, which illustrates an example of an integrated logic circuit unit 1, this integrated logic circuit unit 1 is formed by gates G1, G2, G3 and G4, five input signal lines I1, I2, . . . , I5 and three output signal-lines O1, O2 and O3. In this case, if the integrated logic circuit unit 1 is normally operated under the condition that an input vector VEC is applied to the input signal lines I1, I2, . . . , I5, an expected output response EXO is obtained at the output signal lines O1, O2 and O3. An example of the relationship between the input vector VEC and the expected output response EXO is illustrated in FIG. 4B. Note that, in FIG. 4A, an input vector VECi=(0, 1, 1, 0, 1) is applied as the input vector VEC to the input signal lines I1, I2, . . . , I5, and its resulting expected output response EXO=(1, 0, 1) is obtained.)
Examiner note: Examiner consider the input vector as a test pattern which is a set of specific inputs provided to a system to verify its behavior and functionality.
detecting one instance of the plurality of instances of the circuit model, the one instance simulated with a set of input conditions of a logic behavioral model in the reduced table and rendered a result matching the corresponding output result; (See para 26-30-All previous per-test fault diagnosis methods use a strict matching criterion, in which a fault simulation result for a fault in a circuit model is compared with the corresponding observed response of the real circuit at all primary outputs under a failing vector. This often results in a mismatch, which leads to lower diagnostic resolution. In the present invention three factors, i.e. the matching information, the number of matched errors, and the depth of a fault, are all used in per-test fault diagnosis. A diagnosis value is calculated for each fault based on the three factors. Generally, the diagnosis value for a fault under a failing input vector is zero if the fault-simulation result and its corresponding circuit response does not match for the fault and the failing input vector. If the fault-simulation result and its corresponding circuit response match, the diagnosis value for the fault under the failing input vector is a value greater than zero, and the value is calculated based on the number of matched errors and the depth of a fault. See also para 83)
Wen does not teach adding a test logic to each of the plurality of instances.
However, Rajski further teaches adding a test logic to each of the plurality of instances. ((see para 14-In some embodiments, probabilities that one or more of the potential defects actually caused the integrated circuit failures are determined from diagnostic results produced using the fault dictionary. These probabilities are then reported. One or more of the following acts can be performed based at least in part on the reported probabilities: (a) adjusting one or more design manufacturing rules; (b) adjusting one or more defect extraction rules; or (c) providing recommended modifications of one or more features in the integrated circuit. see para 99-101- A netlist description (for example, netlist (4713)) of a design can be modified to enable design-for-test procedures like test pattern generation, simulation, and fault simulation to support defect-based testing by adding or deleting gates, or by adding or deleting signal lines, or both. This analysis investigates if some of the DFM rules (1) from which the defect-extraction rules (3) were derived should be modified. This information can be used to improve the DFM rules, and thus the yield, for the current integrated circuit (e.g. by means of a redesign or a mask modification (27)). In addition, the improved DFM rules can lead to higher initial yield of the next design, which is based on the now-improved DFM rules. See para 255- For illustrative purposes, this discussion makes reference to FIG. 46, which shows an exemplary fanout-free region embedded in a circuit. The exemplary region comprises one NAND gate and one OR gate. Signal s is termed the “stem” of this fanout-free region, and signal lines a, b, c, and d are internal signals. For illustrative purposes only, assume that only combinational test pattern sets are used to test this circuit.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date
of the claimed invention to modify the method for diagnosing faults in an integrated logic circuit as disclosed by Wen to include adding a test logic to each of the plurality of instances as taught by Rajski in the system of Wen and Sokar in order to reduce the number of defective chips being produced, foundries (integrated circuit manufacturers) often provide a number of recommended design rules that designers can use to help improve the yield of their particular design. Such rules are generally referred to herein as Design for Manufacturability (DFM) rules and can pertain to a wide variety of parameters related to integrated circuit design. (see para 0004, Rajski)
Regarding claim 22
Wen further teaches generating a reduced table of the circuit model according to the simulation of the plurality of instances, (see para 005- Fault diagnosis is the process of identifying suspicious areas in a failing circuit by making use of logical faults assumed in a circuit model. A logical fault has two attributes: location and logical behavior. In a gate-level circuit model, the location attribute is one or more nets or pins, and the logical behavior attribute is one or more logic values. Fault modeling defines these attributes in a general manner. The process of identifying faults, with likely link to physical defects, is known as fault diagnosis. see para 130-131- That is, all essential faults are extracted and excluded from the fault diagnosis table to change it to a target diagnosis table. Note that one essential fault is defined by a fault such that an entry in the fault diagnosis table is the only non-zero entry in the corresponding row (failing input vector) and the corresponding column (faulty gate). The essential faults are indispensable in the multiplet. If there is no essential fault, the target diagnosis table is the same as the original diagnosis table. In FIG. 14, the faulty gate G5 is an essential fault. Therefore, the faulty gate G5 is excluded from the original fault diagnosis table.)
Wen does not teach wherein the additional test pattern is generated based on the reduced table of the circuit model.
However, Rajski further teaches wherein the additional test pattern is generated based on the reduced table of the circuit model. (See para 152- For purposes of this discussion, it is assumed that a fault dictionary (16) is generated together with the pattern set. The fault dictionary can comprise, for example, a table organized into rows, with each row containing data for a test pattern. See para 164-165- 4. Generate additional test patterns to better cover the identified problem with higher resolution 5. Generate additional test patterns to cover defects that may not have been covered before)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date
of the claimed invention to modify the method for diagnosing faults in an integrated logic circuit as disclosed by Wen to include wherein the additional test pattern is generated based on the reduced table of the circuit model as taught by Rajski in the system of Wen and Sokar in order to reduce the number of defective chips being produced, foundries (integrated circuit manufacturers) often provide a number of recommended design rules that designers can use to help improve the yield of their particular design. Such rules are generally referred to herein as Design for Manufacturability (DFM) rules and can pertain to a wide variety of parameters related to integrated circuit design. (see para 0004, Rajski)
Regarding claim 23
Wen further teaches exclude, the plurality of logic behavioral models in the table, the logic behavioral model applied to the plurality of instances of the circuit model and rendered the fault result. (see para 005- Fault diagnosis is the process of identifying suspicious areas in a failing circuit by making use of logical faults assumed in a circuit model. A logical fault has two attributes: location and logical behavior. In a gate-level circuit model, the location attribute is one or more nets or pins, and the logical behavior attribute is one or more logic values. Fault modeling defines these attributes in a general manner. The process of identifying faults, with likely link to physical defects, is known as fault diagnosis. see para 130-131- That is, all essential faults are extracted and excluded from the fault diagnosis table to change it to a target diagnosis table. Note that one essential fault is defined by a fault such that an entry in the fault diagnosis table is the only non-zero entry in the corresponding row (failing input vector) and the corresponding column (faulty gate). The essential faults are indispensable in the multiplet. If there is no essential fault, the target diagnosis table is the same as the original diagnosis table. In FIG. 14, the faulty gate G5 is an essential fault. Therefore, the faulty gate G5 is excluded from the original fault diagnosis table.)
Regarding claim 24 and 25
Wen does not teach the fabricated physical integrated circuit comprises the physical characteristics that the virtual defects are generated irrespective of.
However, Sokar further teaches the fabricated physical integrated circuit comprises the physical characteristics that the virtual defects are generated irrespective of. (see col 2 line 15-28- In one embodiment of the disclosure, a fault aware analog model (FAAM) system is disclosed. The FAAM system comprises a FAAM builder module comprising a model construction module configured to receive a reference dataset associated with a circuit block. In some embodiments, the reference dataset comprises a set of data values that defines input to output relationship of the circuit block for both in spec and out of spec operation of the circuit block, wherein the reference data set is derived based on data associated with a ground truth representation of the circuit block. The model construction module is further configured to generate a FAAM comprising a behavioral model of the circuit block, based on the reference dataset. In some embodiments, the FAAM is configured to approximate the input to output relationship of the circuit block that is defined by the set of data values in the reference dataset. See col 4 line 3-12- In order to calculate the test coverage metrics of the test program for the circuit (e.g., an analog circuit), analog defect simulation (ADS) of the circuit, referred to herein as a test circuit or a module under test, is performed. To perform ADS on the test circuit, potential defects are extracted from the test circuit according to the IEEE definitions. See col 8 line 55-58- Simple Random Sampling (SRS) or Latin-Hypercube-Sampling (LHS), to form the set of input values to be utilized within the reference dataset. See col 6 line 29-31- In one embodiment, a method to develop a FAAM based on extending nominal models with out-of-spec behavior using the reference data set is disclosed. See col 11 line 33-40- Generally, the parametric model is not constructed based on physical assumptions and laws, but is rather fitted/trained based on the generated reference dataset, so that it represents the reference dataset as well as possible. Specifically, the plurality of model parameters is modified/trained based on the reference dataset, in order for the parametric model to approximate the input-output relationship defined by the reference dataset. See fig 3A (lookup table))
Examiner note: “Fault inputs” to the model where the faults originate exterior to the model itself, i.e. from the source blocks. These are the inputs which are irrespective of physical defects of the circuit model.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date
of the claimed invention to modify the method for diagnosing faults in an integrated logic circuit as disclosed by Wen to include the fabricated physical integrated circuit comprises the physical characteristics that the virtual defects are generated irrespective of as taught by Sokar in the system of Wen and Rajski in order develop data driven behavioral models that are fault-aware. Another motivation is to find defects such as hard defects (open and short circuits) and/or soft/parametric defects (change in a process parameter of a circuit element), that are present in the circuit due to unintended production errors or post-manufacturing mishandling. Thus, it provides the probabilities that the Integrated Circuit (IC) does or does not contain a fault, given that the test program has pass. (see col 1 line 5-25, Sokar)
Conclusion
8. Claims 1, 4-11, 13-18 and 21-25 is/are rejected.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lin, et al. US 20070288822 A1
Discussing a system for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects.
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PURSOTTAM GIRI whose telephone number is (469)295-9101. The examiner can normally be reached 7:30-5:30 PM, Monday to Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ryan Pitaro can be reached on 5712724071. The fax phone number for the organization where this application or proceeding is assigned is 571-272-4071.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PURSOTTAM GIRI/Examiner, Art Unit 2188
/RENEE D CHAVEZ/Supervisory Patent Examiner, Art Unit 2186