DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on Mar. 23th 2026 has been entered.
Response to Amendment
The amendment filed on Mar. 13th 2026 has been entered. Claims 1-3, 5, 7, 13, 15, 18-20, 32-33, 36-37 and 44-54 remain pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 15, 18-20 and 44-45 are rejected under 35 U.S.C. 103 as being unpatentable over Oda et al. (US 20100328894) in view of Badihi et al. (US 20180306990), Li et al. (US 6540525) and Hong et al. (US 20100134126).
Regarding claim 15, Oda teaches an electronic package (optical interconnection device; Abstract), comprising:
a package substrate (fig. 4, electric wiring board 10; para. 0061) with a first side (top side) and a second side (bottom side) opposite the first side;
a first set of photonic engine modules (optical modules 12 above 10; para. 0061) coupled to the first side of the package substrate (top side of 10);
a second set of photonic engine modules (12 below 10) coupled to the second side of the package substrate (bottom side of 10), wherein the first and second sets of photonic engine modules (12) are communicatively coupled to the package substrate (LSI 11 and the optical modules 12 are electrically connected to the electric wiring board 10); and
a single heat sink (fig. 10, heatsink 3; para. 0006) which spans multiple photonic engine modules (optical interface module 2; para. 0006, similar to 12 above 10 in fig. 4) of the first set of photonic engine modules (fig. 4, 12 above 10).
Oda fails to explicitly teach a switch die coupled to the first side of the package substrate.
However, Badihi teaches a switch die (Badihi: fig. 3, switching Integrated Circuit (IC) 44; para. 0048) coupled to the first side of the package substrate (Badihi: top side of substrate 76, 44 electrically connect between substrate 80 and substrate 76; para. 0080, similar to 10 of Oda).
Badihi and Oda are considered to be analogous to the claimed invention because they are in the same field of electronic package devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add switch die as taught by Badihi into Oda.
Doing so would realize a switch die, which is essential for connect the network and computer. In addition, the network switches provide improved techniques for transmitting communication signals at high data rates over long transmission ranges between network entities with minimal degrading in the quality of transmission (e.g., signal integrity), thereby reducing the number of HOPs required (Badihi: para. 0027).
Oda in view of Badihi fails to explicitly teach a system board;
a socket, wherein the socket has a rectangular shape, a top edge of the rectangular shape of the socket is attached to, and extends along, the second side of the first package substrate, an opposing bottom edge of the socket is attached to, and extends along, the system board, and the socket has a standoff height that is greater than a thickness of the photonic engine modules of the second set of photonic engine modules; and
electrical routing paths that extent through the socket to provide an electrical connection between the system board and the die.
However, Li teaches a system board (Li: fig. 7, system board 22; col. 4, lin. 54);
a socket (Li: pads 14, pins 18 and sockets 20; col. 4, lin. 55), wherein the socket (Li: top end 14) is attached to the second side (bottom side) of the package substrate (Li: electrical circuit members 122; col. 11, lin. 38-39, similar to 10 of Oda), an opposing end of the socket (Li: bottom end 14) is attached to the system board (Li: 22), the socket (Li: 14, 18, 20) has a standoff height (Li: height of 18 in 20) that is greater than a thickness of the photonic engine modules (Li: semiconductor elements 16 below 122; col. 11, lin. 37, similar to 12 of Oda ) of the second set of photonic engine modules (Li: 16 below 122); and
electrical routing paths (Li: 14 may provide Signal, power connections, from bottom to top; col. 6, lin. 54-55) through the socket (Li: 14, 18, 20) to provide an electrical connection (Li: 14 may provide Signal, power connections; col. 6, lin. 54-55) between the system board (Li: 22) and the die (Li: electrical circuit members 134; col. 11, lin. 38-39, similar to 44 of Badihi).
Li, Badihi and Oda are considered to be analogous to the claimed invention because they are in the same field of electronic package devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add detail of a socket to system board as taught by Li into Oda in view of Badihi.
Doing so would realize a socket connection to assure effective repair, upgrade, and/or replacement of various components (Li: col. 2, lin. 28-29).
In addition, Oda in view of Badihi and Li fails to explicitly teach the socket has a rectangular shape, a top edge of the socket is attached to, and extends along, the second side of the first package substrate, an opposing bottom edge of the socket is attached to, and extends along, the system board.
However, Hong teaches the socket (Hong: fig. 34, pogo pin block 70; para. 0090, similar to 20 of Li) has a rectangular shape (Hong: 70 has a rectangular shape), a top edge of the rectangular shape of the socket (Hong: top edge of 70) is attached to (Hong: through hole space transformer 60; para. 0090), and extends along (Hong: parallel along), the bottom side of the first package substrate (Hong: bottom side of contact substrate 51; para. 0090, similar to 122 of Li), an opposing bottom edge of the socket (Hong: bottom edge of 70) is attached to, and extends along (Hong: attached and parallel along), a top side of the system board (Hong: top side of printed circuit board (PCB) 80, similar to 22 of Li).
Hong, Li, Badihi and Oda are considered to be analogous to the claimed invention because they are in the same field of electronic package devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the socket with a rectangular shape and contacts shape as taught by Hong.
Doing so would realize a contact structure which is capable of simplifying its manufacturing processes, thereby improving its yield (Hong: para. 0007).
Regarding claim 18, Oda in view of Badihi, Li and Hong further teaches the switch die (Badihi: fig. 3, 44) is coupled directly to the package substrate by an interconnect (Badihi: IC 44 is mounted on package substrate 80 and electrically connect between substrate 80 and substrate 76; para. 0079-0080).
Regarding claim 19, Oda in view of Badihi, Li and Hong further teaches the switch die (Badihi: fig. 3, 44) is on a second package substrate (Oda: fig. 4, LSI 11; para. 0061, similar to 80 of Badihi), and the second package substrate (Oda: 11) is coupled to the first side of the package substrate (Oda: top side of 10) by an interconnect (Oda: LSI 11 are electrically connected to the electric wiring board 10 and have optical interconnection of input and output signals; para. 0061, 0083).
Regarding claim 20, Oda in view of Badihi, Li and Hong teaches the electronic package of claim 15, further comprising:
a second socket (Oda: fig. 4, socket between 11 and 10; para. 0072) coupled to the first side of the package substrate (Oda: top side of 10), wherein the second socket (Oda: socket between 11 and 10) is directly below the switch die (Badihi: fig. 3, 44, which is directly on 11 of Oda).
Regarding claim 44, Oda in view of Badihi, Li and Hong teaches the electronic package of claim 15, wherein the second set of photonic engine modules (Li: fig. 7, 16 below 122) are arranged symmetrically around the socket (Li: 14, 18, 20).
Regarding claim 45, Oda in view of Badihi, Li and Hong teaches the electronic package of claim 15, wherein the socket (Li: fig. 7, 14, 18, 20) is a sole socket (Li: 14, 18, 20 together is the only socket) around which the second set of photonic engine modules (Li: 16 below 122) are laterally arranged.
Claim 37 is rejected under 35 U.S.C. 103 as being unpatentable over Oda in view of Badihi, Li and Hong as applied to claim 15 above, and further in view of Lee et al. (US 20140048924).
Regarding claim 37, Oda Badihi, Li and Hong further teaches the electronic package of claim 15, wherein respective photonic engine modules of the first and second sets of photonic engine modules (Oda: fig. 4, 12) each comprise:
a respective socket (Oda: 12 are electrically connected to 10 by a socket; para. 0061) by which the respective photonic engine module (Oda: 12) is attached to the package substrate (Oda: 4); and
in a stacked configuration (Oda: stack of 12 and liquid cooling pipe 14; para. 0062), a photonic engine (Oda: 12) and a generic heat sink (Oda: 14).
Oda in view of Badihi, Li and Hong fails to explicitly teach a thermal interface material (TIM), and an integrated heat spreader (IHS), wherein the IHS is thermally coupled to the photonic engine by the TIM.
However, Lee teaches a thermal interface material (TIM) (Lee: fig. 2, TIM 141; para. 0003), and an integrated heat spreader (IHS) (Lee: IHS 150; para. 0003), wherein the IHS (Lee: 150) is thermally coupled to the photonic engine (Lee: integrated circuit die 140; para. 0003, similar to 12 of Oda) by the TIM (Lee: 141).
Lee, Hong, Li, Badihi and Oda are considered to be analogous to the claimed invention because they are in the same field of electronic package devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add TIM, IHS as taught by Lee.
Doing so would realize a heat dissipation device to increase the thermal transfer efficiency (Lee: para. 0003).
Allowable Subject Matter
Claims 1-3,5,7,13,32-33,36 and 46-54 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 would be allowable for disclosing “a daughter board disposed above the at least one socket and spaced apart from the top of the at least one socket by a gap;
a land grid array (LGA) connector disposed above the daughter board;
a first plurality of contacts which extend upward from the top of the mother board, through the at least one socket, to the gap;
a second plurality of contacts which extend downward from the plurality of LGA pads, through the LGA connector, to the gap, wherein bottom portions of the second plurality of contacts mate with top portions of the first plurality of contacts;
photonic engine modules attached to the top and bottom sides of the first package substrate; wherein the photonic engine modules are communicatively coupled to the die package through the first package substrate”.
Luebs et al. (US 6477058) teaches a daughter board (fig. 3, 14) disposed above the at least one socket (52) and spaced apart from the top of the at least one socket (top of 52) by a gap (gap between 14 and 52); a land grid array (LGA) connector (50) disposed above the daughter board (14); a first plurality of contacts (contacts in 52) which extend upward from the top of the mother board (top of 16), through the at least one socket (52), to the gap (gap between 14 and 52). However, Luebs fails to teach a second plurality of contacts which extend downward from the plurality of LGA pads, through the LGA connector, to the gap, wherein bottom portions of the second plurality of contacts mate with top portions of the first plurality of contacts; photonic engine modules attached to the top and bottom sides of the first package substrate; wherein the photonic engine modules are communicatively coupled to the die package through the first package substrate.
Claims 2-3,5,7,13,32-33,36 and 46-54 would be also allowable because they are dependent on claim 1.
Response to Arguments
Applicant's arguments filed Mar. 13th 2026 have been fully considered but they are not persuasive.
With respect to pages 11-12 of applicant’s response of claim 15 is rejected under 35 U.S.C.103.
Applicant submits "Oda in view of Badihi, Li and Hong, fail to disclose or suggest the claimed features".
The examiner respectfully disagrees.
As shown in fig. 10 of Oda, Oda teaches a single heat sink 3 which spans multiple photonic engine modules (2, similar to 12 above 10 in fig. 4) of the first set of photonic engine modules (12 above 10 in fig. 4) to improve a cooling capability. As result, given a broadest reasonable interpretation, Oda in view of Badihi, Li and Hong teaches all limitations of claims 15. Details of rejections are discussed above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818
Prosecution Insights