DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Applicant
This Office Action is in response to Applicant’s reply filed on 21 January 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4, 6-8 and 20-24 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1 and 21 recites “wherein the bit line discharge portion extending from the bit line vertically has a same width as the bit line vertically in a same direction over the body substrate.” Applicant’s originally filed specification does not disclose the bit line discharge portion having a same width as the bit line vertically in a same direction over the body substrate. Applicant’s specification, for example in Fig. 1, appears to show the bit line discharge portion BLE having a same width as the bit line BL in a direction (D2) parallel to an upper surface of the substrate BS, not vertically in the direction D1, which is vertically from the substate BS. For compact prosecution, to be consistent with Applicant’s specification, it will be interpreted as “wherein the bit line discharge portion extending from the bit line vertically has a same width as the bit line in a direction parallel to an upper surface of the substrate.”
Claims 2-4, 6-8, 20 and 22-24, which depend either directly or indirectly from independent claims 1 and 21, do not remedy the issues of claims 1 and 21 and therefore are also rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-8 and 20-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (U.S. Pub. 2021/0183862) in view of Yu (U.S. Pub. 2009/0020808) in view of Kim et al. (U.S. Pub. 2019/0221557).
Claims 1-4, 6 and 20: Son et al., in Fig. 2 and in paragraphs 35-43, discloses a semiconductor device, comprising:
a body substrate (SUB);
a memory cell array (SCA) including a plurality of memory cells (DS and SP) that are vertically stacked over the body substrate (SUB), and a bit line (BL) sharing the memory cells (DS and SP), the bit line (BL) extended vertically over the body substrate (SUB);
a bit line discharge portion (PER) coupled between the body substrate (SUB) and a bottom portion of the bit line (BL), wherein the bit line discharge portion (PER) extending vertically in a same direction (vertical direction) as the bit line (BL) over the body substrate (SUB);
wherein each of the memory cells (DS and SP) includes:
a capacitor (DS) laterally spaced apart from the bit line (BL);
an active layer (SP) laterally oriented between the bit line (BL) and the capacitor (DS); and
a word line (WL) positioned on any one of an upper surface and a lower surface of the active layer (SP), and laterally extending in a direction intersecting the active layer (SP),
wherein the bit line discharge portion (PER) is electrically coupled to the bottom portion of the bit line (BL) and is physically coupled to the body substrate (SUB) and the bottom portion of the bit line (BL),
wherein the bit line discharge portion (PER) is positioned between the bit line (BL) and the body substrate (SUB).
Son et al. appears not to explicitly disclose wherein the bit line discharge portion extending from the bit line vertically has a same width as the bit line in a direction parallel to an upper surface of the substrate, and the bit line discharge portion comprises at least one material different from a material included in the bit line;
wherein the bit line discharge portion is electrically and phsically coupled to the body substrate and the bottom portion of the bit line;
wherein the bit line discharge portion includes a conductive material or a semiconductor material; and
wherein the bit line discharge portion directly contacts the body substrate.
Yu, however, in Fig. 1H and in paragraphs 115, 116 and 118, discloses the bit line discharge portion (450) extending from the bit line (460 and 470) vertically has a same width (width b) as the bit line (460 and 470) in a direction parallel to an upper surface of the substrate (100), and the bit line discharge portion (450) comprises at least one material (silicon) different from a material (metal) included in the bit line (460 and 470);
wherein the bit line discharge portion (450) is electrically and phsically coupled to the body substrate (100) and the bottom portion (bottom portion of 460 and 470) of the bit line (460 and 470);
wherein the bit line discharge portion (450) includes a conductive material or a semiconductor material; and
wherein the bit line discharge portion (450) directly contacts the body substrate (100) in order to reduce contact resistance between the bit line and underlying circuits.
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It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Son et al. with the disclosure of Yu to have made the bit line discharge portion extending from the bit line vertically has a same width as the bit line in a direction parallel to an upper surface of the substrate, and the bit line discharge portion comprises at least one material different from a material included in the bit line;
wherein the bit line discharge portion is electrically and phsically coupled to the body substrate and the bottom portion of the bit line;
wherein the bit line discharge portion includes a conductive material or a semiconductor material; and
wherein the bit line discharge portion directly contacts the body substrate in order to reduce contact resistance between the bit line and underlying circuits (paragraph 116 of Yu).
Son et al. also appears not to explicitly disclose a multi-level metal line coupled to an upper portion of the bit line, and
at least one control circuit which is positioned at a higher level than the memory cell array and controls the memory cell array,
wherein the multi-level metal line is disposed in a peripheral circuit portion, the peripheral circuit portion positioned at a higher level than the memory cell array.
Kim et al., however, in Figs. 17, 19 and 24 and in paragraphs 167, 171, 175 and 189, discloses a multi-level metal line (2792, 1792 and 1780) coupled to an upper portion of the bit line (98), and
at least one control circuit (2000) which is positioned at a higher level than the memory cell array (100) and controls the memory cell array (100),
wherein the multi-level metal line (2792, 1792 and 1780) is disposed in a peripheral circuit portion (2000), the peripheral circuit portion (2000) positioned at a higher level than the memory cell array (100) in order to have very low voltage CMOS devices separated from low voltage and high voltage CMOS devices.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Son et al. with the disclosure of Kim et al. to have made a multi-level metal line coupled to an upper portion of the bit line, and
at least one control circuit which is positioned at a higher level than the memory cell array and controls the memory cell array,
wherein the multi-level metal line is disposed in a peripheral circuit portion, the peripheral circuit portion positioned at a higher level than the memory cell array in order to have very low voltage CMOS devices separated from low voltage and high voltage CMOS devices (paragraph 189 of Kim et al.).
Claim 7: Son et al. in view of Yu in view of Kim et al. discloses the semiconductor device of claim 1, and since Son et al., in paragraph 33, discloses the memory cell consists of a transistor MCT and a capacitor, Son et al. would disclose wherein the memory cell array is a portion of a Dynamic Random Access Memory (DRAM) cell array.
Claim 8: Son et al. in view of Yu in view of Kim et al. discloses the semiconductor device of claim 1, and Son et al., in paragraph 37, wherein the active layer (SP) includes monocrystalline silicon, polysilicon, amorphous silicon, silicon germanium, indium gallium zinc oxide (IGZO), MoS2 or WS2.
Claims 21 and 22: Son et al. discloses a semiconductor device, in Fig. 2 and in paragraphs 35-43, comprising:
a body substrate (SUB);
a memory cell array (SCA) including a plurality of memory cells (DS and SP) are vertically stacked over the body substrate (SUB) and a bit line (BL) sharing the memory cells (DS and SP), the bit line (BL) extended vertically over the body substrate (SUB); and
a bit line discharge portion (PER) coupled between the body substrate (SUB) and a bottom portion of the bit line (BL), wherein the bit line discharge portion (PER) extending vertically in a same direction (vertical direction) as the bit line (BL) over the body substrate (SUB),
wherein the bit line discharge portion (PER) is electrically coupled to the bottom portion of the bit line (BL) and is physically coupled to the body substrate (SUB) and the bottom portion of the bit line (BL), and
wherein the bit line discharge portion (PER) and the bit line (BL) are different from each other.
Son et al. appears not to explicitly disclose wherein the bit line discharge portion extending from the bit line vertically has a same width as the bit line in a direction parallel to an upper surface of the substrate, and the bit line discharge portion comprises at least one material different from a material included in the bit line, and
wherein the bit line discharge portion is electrically and physically coupled to the body substrate and the bottom portion of the bit line.
Yu, however, in Fig. 1H and in paragraphs 116 and 118, discloses wherein the bit line discharge portion (450) extending from the bit line (460 and 470) vertically has a same width (width b) as the bit line (460 and 470) in a direction parallel to an upper surface of the substrate (100, and the bit line discharge portion (450) comprises at least one material (silicon) different from a material (metal) included in the bit line (460 and 470), and
wherein the bit line discharge portion (450) is electrically and physically coupled to the body substrate (100) and the bottom portion (bottom portion of 460 and 470) of the bit line (460 and 470) in order to reduce contact resistance between the bit line and underlying circuits.
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It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Son et al. with the disclosure of Yu to have made the bit line discharge portion extending from the bit line vertically has a same width as the bit line in a direction parallel to an upper surface of the substrate, and the bit line discharge portion comprises at least one material different from a material included in the bit line, and
wherein the bit line discharge portion is electrically and physically coupled to the body substrate and the bottom portion of the bit line in order to reduce contact resistance between the bit line and underlying circuits (paragraph 116 of Yu).
Son et al. appears not to explicitly disclose a multi-level metal line coupled to an upper portion of the bit line.
Kim et al., however, in Figs. 17, 19 and 24 and in paragraphs 167, 171, 175 and 189, discloses a multi-level metal line (2792, 1792 and 1780) coupled to an upper portion of the bit line (98).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Son et al. with the disclosure of Kim et al. to have made a multi-level metal line coupled to an upper portion of the bit line in order to have very low voltage CMOS devices separated from low voltage and high voltage CMOS devices (paragraph 189 of Kim et al.).
Claim 23: Son et al. in view of Yu in view of Kim et al. discloses the semiconductor device of claim 21, and Son et al., in Fig. 2 and in paragraphs 40, 41 and 43, further discloses wherein each of the memory cells (DS and SP) includes:
a capacitor (DS) laterally spaced apart from the bit line (BL);
an active layer (SP) laterally oriented between the bit line (BL) and the capacitor (DS); and
a word line (WL) positioned on any one of an upper surface and a lower surface of the active layer (SP), and laterally extending in a direction intersecting the active layer (SP).
Claim 24: Son et al. in view of Yu in view of Kim et al. discloses the semiconductor device of claim 23, and Son et al., in Fig. 7 and in paragraph 73, further discloses wherein the capacitor (DS) includes:
a cylindrical storage node (EL1);
a dielectric layer (DL) on the cylindrical storage node (EL1); and
a plate node (EL2) on the dielectric layer (DL).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-4, 6-8 and 20-24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/J.L/ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815