Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/8/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note 1: There are no changes from the rejections of the prior Office action. The citations relied upon, and the rationale applied to the rejections in the instant Office action are the same as before. The modification to the rejections are limited to matters of form, and additional remarks included to promote clarity of the record.
Rejection Note 2: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-6, 11-12, and 17-26 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20180294226 A1) in view of Liebman (US 20210118798 A1).
Fig. 7 is the M2 level, Figs. 1, 2A, and 2B are related to Fig. 7 (see [0048]). Figs. 1/2A/2B teach the perpendicular relation.
Regarding claim 1, Lee discloses a method comprising:
routing buried power rails (Fig. 7: PR71-74; these rails being buried in a dielectric, [0075]: “BEOL may include…adding a dielectric, planarizing, forming holes, adding metal layers, forming vias”) underneath (selecting positive Z direction as underneath) a memory instance (C71 is relied upon here to teach a generic standard cell);
identifying (these rails are deliberately designed to have specific dimensions, shapes, and relations to produce a desired electrical path; additional remarks regarding the deliberate design are further below. Therefore, the respective lengths of each power rail would necessarily have been known, i.e., identified during the method) first rails of the buried power rails (See annotated figure) disposed in a first layer (M2) and second rails of the buried power rails (See annotated figure) disposed perpendicular to the first rails (perpendicular in the X/Y plane) in a second layer (M1);
identifying (these rails are deliberately designed to have specific dimensions, shapes, and relations to produce a desired electrical path; additional remarks regarding the deliberate design are further below. Therefore, the respective lengths of each power rail would necessarily have been known, i.e., identified during the method) long rails of the first rails (See annotated figure) with a first length (as measured in the Y direction) and short rails of the first rails (See annotated figure) with a second length (as measured in the Y direction) that is less than the first length (“less than” is determined by the long rails extending completely over and beyond the second power rails in the Y direction, while first power rails are fully confined within the cell boundary); and
separately coupling the long rails and the short rails to the second rails with vias that extend between the first layer and the second layer (Fig. 1 shows vias coupling and extending between the first and second layers),
wherein at least one of the short rails is positioned to define a spatial gap (See annotated figure) located adjacent an edge of the memory instance (Cell Boundary, adjacent in the Y direction) and extending inward (extending inward in the Y direction) to provide a region (the region being the entire second layer) for addition of one or more additional second rails in the second layer (selecting PR73 and PR74 as the additional second rails in the second layer).
Lee discloses vias and the first and second layers (Fig. 1: vias, M1, M2) but fails to explicitly illustrate the via configuration for the selected embodiment (Fig. 7). Thus, Lee fails to expressly disclose “separately coupling the long rails and the short rails to the second rails with vias that extend between the first layer and the second layer”.
However, Lee teaches:
The first rails can be designed to perform the function of power rails ([0049]: “the power rail PR71 may include a pattern L71 of the M2 layer”).
All of the chosen first rails (of the selected Fig. 7 embodiment) overlap the second rails (in the Z direction). Thus, the first rails are spatially capable of coupling to the second rails (of the underlying M1 layer) in situations where a via is included.
The power rail arrangement may be varied as a design choice according to required circuitry configuration (Fig. 7: cells C71-C79 have varied M2 rail configurations; [0021]: “patterns of the M2 layer and the pattern of the M3 layer may be determined in a routing operation after the standard cells C11 and C12 are placed in a design process of the standard cells”).
Thus, separately coupling the long and short rails (of the first power rails in the M2 layer) to the second rails (of the overlapping M1 layer) with vias used in the same way as those disclosed in the Fig. 1 embodiment would have been obvious to one of ordinary skill in the art before the effective filing date because it is a design choice according to required circuitry configuration. Lee provides a teaching to motivate one to include the claimed via coupling configuration in that it would enable improved electrical operation ([0049]: “an IR drop may be mitigated”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date because it is a design choice encompassed by the prior art that would enable improved electrical operation. MPEP 2143 (I)(G). MPEP 2144 (I).
Illustrated below are marked and annotated figures of Figs. 1 and 7 of Lee.
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Lee fails to disclose the generic standard cell (Fig. 7: C71) is a memory instance. Thus, Lee fails to disclose “a memory instance”, as recited in the claim.
Liebman discloses a similar method where a standard cell is described as a memory instance ([0031]: “standard cells, such as inverter cells, NAND cells, NOR cells, and the like from a standard cell library”).
Modifying the generic standard cell of Lee to be a memory instance would arrive at the claimed method. Liebman teaches a design incentive for configuring a standard cell as a memory instance in that it would provide a cell according to required circuitry function ([0031]: “active devices, such as logic circuits, analog circuits, memory circuits…configured to perform one or more operations”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed memory instance because it a design incentive encompassed within the prior art, chosen according to required circuitry function. MPEP 2143 (I)(F).
Regarding claim 2, Lee in view of Liebman discloses the method of claim 1 (Lee: Fig. 7), wherein: a first set of the long rails (selecting one of the long rails as the first set) in the first layer is coupled to ground ([0023]: “VSS” being ground consistent with the disclosure as well as the ordinary and customary meaning of VSS; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration),
and a second set of the long rails (selecting another of the long rails as the second set) in the first layer is coupled to a first supply ([0023]: “VDD” being the first supply; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration).
Regarding claim 3, Lee in view of Liebman discloses the method of claim 2 (Lee: Fig. 7), wherein: a first set of the second rails (PR71) in the second layer is coupled to ground ([0023]: “VSS” being ground consistent with the disclosure as well as the ordinary and customary meaning of VSS; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration) by way of a via coupled to the first set of the long rails in the first layer (as reasoned in the claim 1 rejection the claimed via configuration is a design choice according to required circuitry configuration),
and a second set of the second rails (PR72) in the second layer is coupled to the first supply ([0023]: “VDD” being the first supply; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration) by way of another via coupled to the second set of the long rails in the first layer (as reasoned in the claim 1 rejection the claimed via configuration is a design choice according to required circuitry configuration).
Regarding claim 4, Lee in view of Liebman discloses the method of claim 1 (Lee: Fig. 7), wherein: a first set of the short rails (selecting one of the short rails as the first set) in the first layer is coupled to a second supply ([0023]: “VSS” being the second supply; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration),
and a second set of the short rails (selecting another of the short rails as the second set) in the first layer is coupled to a third supply ([0023]: “VDD” being the third supply; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration).
Regarding claim 5, Lee in view of Liebman discloses the method of claim 4 (Lee: Fig. 7), wherein: a third set of the second rails (PR71) in the second layer is coupled to the second supply ([0023]: “VSS” being ground consistent with the disclosure as well as the ordinary and customary meaning of VSS; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration) by way of a via coupled to the first set of the short rails in the first layer (as reasoned in the claim 1 rejection the claimed via configuration is a design choice according to required circuitry configuration),
and a fourth set of the second rails (PR72) in the second layer is coupled to the third supply ([0023]: “VDD” being the first supply; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration) by way of another via coupled to the second set of the short rails in the first layer (as reasoned in the claim 1 rejection the claimed via configuration is a design choice according to required circuitry configuration).
Regarding claim 6, Lee in view of Liebman discloses the method of claim 1 (Lee: Fig. 7), wherein: the first rails have a first width (as measured in the X direction), and the second rails have a second width (as measured in the X direction) that is greater than the first width (greater in the X direction because it extends beyond a full overlap).
Regarding claim 21, Lee in view of Liebman discloses the method of claim 1 (Lee: Fig. 7), wherein each of the short rails is coupled to a single one of the second rails (as reasoned in the claim 1 rejection, the claimed coupling configuration is a design choice according to required circuitry configuration).
Regarding claim 22, Lee in view of Liebman discloses the method of claim 1 (Lee: Fig. 7), wherein each of the short rails overlaps at least two of the second rails (overlaps PR71 and PR72 in at least the Z direction and directions angled between the Z and Y directions).
Regarding independent claim 11, Lee discloses a method comprising:
fabricating a memory instance (Fig. 7: C71 is relied upon here to teach a generic standard cell);
fabricating a power distribution network having buried power rails (PR71-74; these rails being buried in a dielectric, [0075]: “BEOL may include…adding a dielectric, planarizing, forming holes, adding metal layers, forming vias”) routed underneath (selecting positive Z direction as underneath) the memory instance; and
fabricating the buried power rails with first rails (See annotated figure) in a first layer (M2) and second rails (PR71 and PR72; corresponding to Fig. 1: PR11, PR12) that are arranged perpendicular to the first rails (perpendicular in the X/Y plane) in a second layer (M1), wherein:
the first rails include long rails (See annotated figure) with a first length (as measured in the Y direction) and short rails (see annotated figure) with a second length (as measured in the Y direction) that is less than the first length (“less than” is determined by the long rails extending completely over and beyond the second power rails in the Y direction, while first power rails are fully confined within the cell boundary), and
the long rails and the short rails are separately coupled to the second rails with vias that extend between the first layer and the second layer (Fig. 1 shows vias coupling and extending between the first and second layers),
wherein at least one of the short rails is positioned to define a spatial gap (Gap designated by dashed reference lines) that extends from an edge of the memory instance (Cell Boundary) toward an interior region of the memory instance (toward in the Y direction).
Lee discloses vias and the first and second layers (Fig. 1: vias, M1, M2) but fails to explicitly illustrate the via configuration for the selected embodiment (Fig. 7). Thus, Lee fails to disclose “the long rails and the short rails are separately coupled to the second rails with vias that extend between the first layer and the second layer”.
However, Lee teaches:
The first rails can be designed to perform the function of power rails ([0049]: “the power rail PR71 may include a pattern L71 of the M2 layer”).
All of the chosen first rails (of the selected Fig. 7 embodiment) overlap the second rails (in the Z direction). Thus, the first rails are spatially capable of coupling to the second rails (of the underlying M1 layer) in situations where a via is included.
The power rail arrangement may be varied as a design choice according to required circuitry configuration (Fig. 7: C71-C79 have varied M2 rail configurations; [0021]: “patterns of the M2 layer and the pattern of the M3 layer may be determined in a routing operation after the standard cells C11 and C12 are placed in a design process of the standard cells”).
Thus, separately coupling the long and short rails (of the first power rails in the M2 layer) to the second rails (of the overlapping M1 layer) with vias used in the same way as those disclosed in the Fig. 1 embodiment would have been obvious to one of ordinary skill in the art before the effective filing date because it is a design choice according to required circuitry configuration. Lee provides a teaching to motivate one to include the claimed coupling configuration in that it would enable improved electrical operation ([0049]: “an IR drop may be mitigated”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date because it is a design choice encompassed by the prior art that would enable improved electrical operation. MPEP 2143 (I)(G). MPEP 2144 (I).
Lee fails to disclose the generic standard cell (Fig. 7: C71) is a memory instance. Thus, Lee fails to disclose “fabricating a memory instance”, as recited in the claim.
Liebman discloses a similar fabricating method where a standard cell is described as a memory instance ([0031]: “standard cells, such as inverter cells, NAND cells, NOR cells, and the like from a standard cell library”).
Modifying the standard cell of Lee to be a memory instance would arrive at the claimed method. Liebman teaches a design incentive for configuring a standard cell as a memory instance in that it would provide a cell according to required circuitry function ([0031]: “active devices, such as logic circuits, analog circuits, memory circuits…configured to perform one or more operations”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed memory instance because it a design incentive encompassed within the prior art, chosen according to required circuitry function. MPEP 2143 (I)(F).
Regarding claim 12, Lee in view of Liebman discloses the method of claim 11 (Lee: Fig. 1), further comprising:
disposing the first rails in the first layer (the first rails are in M2);
and disposing the second rails perpendicular to the first rails in the second layer (the second rails are in M1 and perpendicular in the X/Y plane);
identifying the long rails of the first rails with the first length (as reasoned in the claim 11 rejection, these rails are deliberately formed to have specific dimensions, shapes, and relations to produce a desired electrical path. Therefore, the respective lengths of each power rail would necessarily have been known, i.e., identified during the method);
identifying the short rails of the first rails with the second length that is less than the first length (as reasoned in the claim 11 rejection, these rails are deliberately formed to have specific dimensions, shapes, and relations to produce a desired electrical path. Therefore, the respective lengths of each power rail would necessarily have been known, i.e., identified during the method);
and separately coupling the long rails and the short rails to the second rails with vias that extend between the first layer and the second layer (as reasoned in the claim 11 rejection, the claimed via configuration is a design choice according to required circuitry configuration).
Regarding claim 23, Lee in view of Liebman discloses the method of claim 11 (Lee: Fig. 7), wherein each of the short rails is coupled to a single one of the second rails (as reasoned in the claim 11 rejection, the claimed coupling configuration is a design choice according to required circuitry configuration).
Regarding claim 24, Lee in view of Liebman discloses the method of claim 11 (Lee: Fig. 7), wherein each of the short rails overlaps at least two of the second rails (overlaps PR71 and PR72 in at least the Z direction and directions angled between the Z and Y directions).
Regarding independent claim 17, Lee discloses a device comprising:
a memory instance (Fig. 7: C71 is relied upon here to teach a generic standard cell); and
a power distribution network having buried power rails (PR71-74; these rails being buried in a dielectric, [0075]: “BEOL may include…adding a dielectric, planarizing, forming holes, adding metal layers, forming vias”) routed underneath (selecting positive Z direction as underneath) the memory instance, wherein:
the buried power rails have first rails (See annotated figure) disposed in a first layer (M2) and second rails (PR71 and PR72; corresponding to Fig. 1: PR11, PR12) disposed perpendicular to the first rails (perpendicular in the X/Y plane) in a second layer (M1),
the first rails have long rails (See annotated figure) with a first length (as measured in the Y direction) and short rails (See annotated figure) with a second length (as measured in the Y direction) that is less than the first length (“less than” is determined by the long rails extending completely over and beyond the second power rails in the Y direction, while first power rails are fully confined within the cell boundary), and
the long rails and the short rails are separately coupled to the second rails with vias that extend between the first layer and the second layer (Fig. 1 shows vias coupling and extending between the first and second layers),
wherein at least one of the short rails is positioned to define a spatial gap (Gap designated by dashed reference lines) located adjacent an edge (Cell Boundary) of the memory instance and extending inward (inward in the Y direction) to provide a region (the region being the entire second layer) for addition of one or more additional second rails in the second layer (selecting PR73 and PR74 as the additional second rails in the second layer).
Lee discloses the vias and the first and second layers (Fig. 1: vias, M1, M2) but fails to explicitly illustrate the via configuration for the selected embodiment (Fig. 7). Thus, Lee fails to disclose “the long rails and the short rails are separately coupled to the second rails with vias that extend between the first layer and the second layer”.
However, Lee teaches:
The first rails can be designed to perform the function of power rails ([0049]: “the power rail PR71 may include a pattern L71 of the M2 layer”).
All of the chosen first rails (of the selected Fig. 7 embodiment) overlap the second rails (in the Z direction). Thus, Lee teaches the first rails are spatially capable of coupling to the second rails (of the underlying M1 layer) in situations where a via is included.
The power rail arrangement may be varied as a design choice according to required circuitry configuration (Fig. 7: C71-C79 have varied M2 rail configurations; [0021]: “patterns of the M2 layer and the pattern of the M3 layer may be determined in a routing operation after the standard cells C11 and C12 are placed in a design process of the standard cells”).
Thus, separately coupling the long and short rails (of the first power rails in the M2 layer) to the second rails (of the overlapping M1 layer) with vias used in the same way as those disclosed in the Fig. 1 embodiment would have been obvious to one of ordinary skill in the art before the effective filing date because it is a design choice according to required circuitry configuration. Lee provides a teaching to motivate one to include the claimed coupling configuration in that it would enable improved electrical operation ([0049]: “an IR drop may be mitigated”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date because it is a design choice encompassed by the prior art that would enable improved electrical operation. MPEP 2143 (I)(G). MPEP 2144 (I).
Lee fails to disclose the generic standard cell (Fig. 7: C71) is a memory instance. Thus, Lee fails to disclose “a memory instance”, as recited in the claim.
Liebman discloses a similar device where a standard cell is described as a memory instance ([0031]: “standard cells, such as inverter cells, NAND cells, NOR cells, and the like from a standard cell library”).
Modifying the generic standard cell of Lee to be a memory instance would arrive at the claimed device. Liebman teaches a design incentive for configuring a standard cell as a memory instance in that it would provide a cell according to required circuitry function ([0031]: “active devices, such as logic circuits, analog circuits, memory circuits…configured to perform one or more operations”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed memory instance because it a design incentive encompassed within the prior art, chosen according to required circuitry function. MPEP 2143 (I)(F).
Regarding claim 18, Lee in view of Liebman discloses the device of claim 17 (Lee: Fig. 7), wherein: the first rails have a first width (as measured in the X direction), and the second rails have a second width (as measured in the X direction) that is greater than the first width (greater in the X direction because it extends beyond a full overlap).
Regarding claim 19, Lee in view of Liebman discloses the device of claim 17 (Lee: Fig. 7), wherein: a first set of the long rails (selecting one of the long rails as the first set) in the first layer is coupled to ground ([0023]: “VSS” being ground consistent with the disclosure as well as the ordinary and customary meaning of VSS; as reasoned in the claim 17 rejection the claimed coupling configuration is a design choice according to required circuitry configuration),
a second set of the long rails (selecting another of the long rails as the second set) in the first layer is coupled to a first supply ([0023]: “VDD” being the first supply; as reasoned in the claim 17 rejection the claimed coupling configuration is a design choice according to required circuitry configuration),
a first set of the short rails (selecting one of the short rails as the first set) in the first layer is coupled to a second supply ([0023]: “VSS” being the second supply because it supplies a different first rail and therefore is an electrical path different from the path supplying the first set of short rails; as reasoned in the claim 17 rejection the claimed coupling configuration is a design choice according to required circuitry configuration),
and a second set of the short rails (selecting another of the short rails as the second set) in the first layer is coupled to a third supply ([0023]: “VDD” being the third supply because it supplies a different first rail and therefore is an electrical path different from the path supplying the first set of short rails; as reasoned in the claim 17 rejection the claimed coupling configuration is a design choice according to required circuitry configuration).
Regarding claim 20, Lee in view of Liebman discloses the device of claim 19 (Lee: Fig. 7), wherein: a first set of the second rails (PR71) in the second layer is coupled to ground ([0023]: “VSS” being ground consistent with the disclosure as well as the ordinary and customary meaning of VSS; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration) by way of a via coupled to the first set of the long rails in the first layer (as reasoned in the claim 1 rejection the claimed via configuration is a design choice according to required circuitry configuration),
a second set of the second rails (PR72) in the second layer is coupled to the first supply ([0023]: “VDD” being the first supply; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration) by way of another via coupled to the second set of the long rails in the first layer (as reasoned in the claim 1 rejection the claimed via configuration is a design choice according to required circuitry configuration),
a third set of the second rails (PR73) in the second layer is coupled to the second supply by way of a via (selecting the same via reasoned to couple the first set of short rails to VSS, from the claim 19 rejection; both PR71 and PR73 would be coupled to VSS thus meeting the claim) coupled to the first set of the short rails in the first layer (as reasoned in the claim 17 rejection the claimed via configuration is a design choice according to required circuitry configuration),
and a fourth set of the second rails (PR74) in the second layer is coupled to the third supply by way of another via (selecting the same via reasoned to couple the second set of short rails to VDD, from the claim 19 rejection; both PR72 and PR74 would be coupled to VDD thus meeting the claim) coupled to the second set of the short rails in the first layer (as reasoned in the claim 17 rejection the claimed via configuration is a design choice according to required circuitry configuration).
Regarding claim 25: Lee in view of Liebman discloses the device of claim 17 (Lee: Fig. 7), wherein each of the short rails is coupled to a single one of the second rails (as reasoned in the claim 17 rejection, the claimed coupling configuration is a design choice according to required circuitry configuration).
Regarding claim 26, Lee in view of Liebman discloses the device of claim 17 (Lee: Fig. 7), wherein each of the short rails overlaps at least two of the second rails (overlaps PR71 and PR72 in at least the Z direction and directions angled between the Z and Y directions).
Response to Arguments
Applicant's arguments filed 3/6/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to independent claims 11 and 17 that “Lee and Liebman Do Not Disclose “Identifying Long Rails of the First Rails with a First Length and Short Rails of the First Rails with a Second Length That Is Less Than the First Length””. Remarks at pg. 7.
Examiner’s reply:
Applicant's arguments are directed to the examiner’s interpretation of claim term “identifying” and the way the examiner has applied MPEP 2111 (broadest reasonable interpretation) to the contended term. The examiner finds “identifying” as claimed reasonably including a plurality of contexts this term could be applied to. For example, the examiner finds the claim written broadly enough to encompass:
The entire design phase, partial device fabrication, and a human manually reviewing (and identifying by pointing with a finger) the formed power rails.
An initial design phase, a simulation phase that determines unsuitability of power rail structural parameters, and a design rework phase that includes some identifying component.
An initial design phase that incorporates the claimed power rails and a human reviewing this completed design in search of these power rails.
And a scenario used for rejecting the claim, reasonably encompassed within the breadth of “identifying” as claimed, and consistent with MPEP 2111: “identifying” includes forming a structure encompassed by the prior art references (either in design or fabrication phases) and at the same time of formation these structures are identified as possessing the characteristics disclosed by the prior art.
The examiner presently finds the breadth of the claim definite, though broad enough to encompass these exemplary scenarios as well as others not mentioned. Accordingly, the outstanding rejection is maintained in the same way as before.
Applicant argues:
Applicant argues with respect to claim 1 that “Lee and Liebman Do Not Disclose “Separately Coupling the Long Rails and the Short Rails to the Second Rails with Vias That Extend Between the First Layer and the Second Layer””.
Examiner’s reply:
The examiner does not find Applicant’s arguments persuasive and points to MPEP 2143 (I)(G) which was previously cited, but also points here to MPEP 2144 (I) in response to Applicants remarks. The examiner has cited Lee as failing to expressly show the claimed via configuration connecting the first and second rails (in combination with all other limitations). However, the examiner has cited Lee as teaching:
First rails in the Fig. 7 embodiment may be connected to the second power rail ([0049]: “the power rail PR71 may include a pattern L71 of the M2 layer”).
The Fig. 1 embodiment teaches substantially similar first rails (M1 rails) and second rails (M2 rails) coupled to each other by vias (See the legend in the figure) when these rails overlap (Z direction).
Using the vias of the Fig. 1 embodiment, when creating the disclosed connections of the Fig. 7 power rails is impliedly contained in the prior art because Lee does not make any suggestion or requirement of some connection technique departing from that which has already been disclosed elsewhere in the reference and useful for the same purpose.
Lee is not relied upon to teach a literal, expressly illustrated rail and via configuration. Rather, Lee as a whole is relied upon to render obvious the claimed configuration. Accordingly, the outstanding rejection is maintained in the same way as before.
Applicant argues:
Applicant argues with respect to claim 1 that “Lee And Liebman Do Not Disclose “At Least One of the Short Rails Is Positioned to Define a Spatial Gap Located Adjacent an Edge of the Memory Instance and Extending Inward to Provide a Region for Addition of One Or More Additional Second Rails in the Second Layer””.
Examiner’s reply:
The examiner does not find Applicant’s arguments persuasive and points to MPEP 2111. The examiner finds the prior art either expressly illustrating the presence of the claimed features, or rendering obvious the claimed structures. The examiner agrees that Lee does not disclose a narrative of the design phase with particular remarks directed to the thought process of arriving at the disclosed shapes and arrangements of the illustrated structures. Nevertheless, the claim as written reasonably includes mapping the illustrated structures, and obvious variations thereof, to terms of the claim. Accordingly, the outstanding rejection is maintained in the same way as before.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
/Kretelia Graham/ Supervisory Patent Examiner, Art Unit 2817 March 18, 2026