Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/19/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-6, 11-12, and 17-27 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20180294226 A1) in view of Liebman (US 20210118798 A1).
Fig. 7 is the M2 level, Figs. 1, 2A, and 2B are related to Fig. 7 (see [0048]). Figs. 1/2A/2B teach the perpendicular relation.
Regarding claim 1, Lee discloses a method comprising:
routing buried power rails (Fig. 7: PR71-74; these rails being buried in a dielectric, [0075]: “BEOL may include…adding a dielectric, planarizing, forming holes, adding metal layers, forming vias”) underneath (selecting positive Z direction as underneath) a memory instance (C71 is relied upon here to teach a generic standard cell);
identifying (these rails are deliberately designed to have specific dimensions, shapes, and relations to produce a desired electrical path; additional remarks regarding the deliberate design are further below. Therefore, the respective lengths of each power rail would necessarily have been known, i.e., identified during the method) first rails of the buried power rails (See annotated figure) disposed in a first layer (M2) and second rails of the buried power rails (See annotated figure) disposed perpendicular to the first rails (perpendicular in the X/Y plane) in a second layer (M1);
identifying (these rails are deliberately designed to have specific dimensions, shapes, and relations to produce a desired electrical path; additional remarks regarding the deliberate design are further below. Therefore, the respective lengths of each power rail would necessarily have been known, i.e., identified during the method) long rails of the first rails (See annotated figure) with a first length (as measured in the Y direction) and short rails of the first rails (See annotated figure) with a second length (as measured in the Y direction) that is less than the first length (“less than” is determined by the long rails extending completely over and beyond the second power rails in the Y direction, while first power rails are fully confined within the cell boundary); and
separately coupling the long rails and the short rails to the second rails with vias that extend between the first layer and the second layer (Fig. 1 shows vias coupling and extending between the first and second layers),
wherein adjacent (indirectly adjacent) second rails in the second layer (the M1 components of PR71/PR73) define a porosity channel (Fig. 7: See annotated figure for the designation of this region) therebetween, and wherein at least one of the short rails in the first layer terminates (terminates in the Y direction) before extending completely across the porosity channel such that a spatial gap (See annotated figure, a collective gap, with two of many gap portions annotated) is maintained within the porosity channel for routing one or more additional second rails in the second layer (the M1 component of PR72 is routed in this channel and overlaps the gap in the Z direction).
Lee discloses vias and the first and second layers (Fig. 1: vias, M1, M2) but fails to explicitly illustrate the via configuration for the selected embodiment (Fig. 7). Thus, Lee fails to expressly disclose “separately coupling the long rails and the short rails to the second rails with vias that extend between the first layer and the second layer”.
However, Lee teaches:
The first rails can be designed to perform the function of power rails ([0049]: “the power rail PR71 may include a pattern L71 of the M2 layer”).
All of the chosen first rails (of the selected Fig. 7 embodiment) overlap the second rails (in the Z direction). Thus, the first rails are spatially capable of coupling to the second rails (of the underlying M1 layer) in situations where a via is included.
The power rail arrangement may be varied as a design choice according to required circuitry configuration (Fig. 7: cells C71-C79 have varied M2 rail configurations; [0021]: “patterns of the M2 layer and the pattern of the M3 layer may be determined in a routing operation after the standard cells C11 and C12 are placed in a design process of the standard cells”).
Thus, separately coupling the long and short rails (of the first power rails in the M2 layer) to the second rails (of the overlapping M1 layer) with vias used in the same way as those disclosed in the Fig. 1 embodiment would have been obvious to one of ordinary skill in the art before the effective filing date because it is a design choice according to required circuitry configuration. Lee provides a teaching to motivate one to include the claimed via coupling configuration in that it would enable improved electrical operation ([0049]: “an IR drop may be mitigated”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date because it is a design choice encompassed by the prior art that would enable improved electrical operation. MPEP 2143 (I)(G). MPEP 2144 (I).
Illustrated below are marked and annotated figures of Figs. 1 and 7 of Lee.
PNG
media_image1.png
533
611
media_image1.png
Greyscale
PNG
media_image2.png
569
665
media_image2.png
Greyscale
Lee fails to disclose the generic standard cell (Fig. 7: C71) is a memory instance. Thus, Lee fails to disclose “a memory instance”, as recited in the claim.
Liebman discloses a similar method where a standard cell is described as a memory instance ([0031]: “standard cells, such as inverter cells, NAND cells, NOR cells, and the like from a standard cell library”).
Modifying the generic standard cell of Lee to be a memory instance would arrive at the claimed method. Liebman teaches a design incentive for configuring a standard cell as a memory instance in that it would provide a cell according to required circuitry function ([0031]: “active devices, such as logic circuits, analog circuits, memory circuits…configured to perform one or more operations”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed memory instance because it a design incentive encompassed within the prior art, chosen according to required circuitry function. MPEP 2143 (I)(F).
Regarding claim 2, Lee in view of Liebman discloses the method of claim 1 (Lee: Fig. 7), wherein:
a first set of the long rails (selecting one of the long rails as the first set) in the first layer is coupled to ground ([0023]: “VSS” is ground, consistent with the disclosure, as well as the ordinary and customary meaning of VSS; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration), and
a second set of the long rails (selecting another of the long rails as the second set) in the first layer is coupled to a first supply ([0023]: “VDD” is the first supply; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration).
Regarding claim 3, Lee in view of Liebman discloses the method of claim 2 (Lee: Fig. 7), wherein:
a first set of the second rails (PR71) in the second layer is coupled to ground ([0023]: “VSS” is ground, consistent with the disclosure, as well as the ordinary and customary meaning of VSS; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration) by way of a via coupled to the first set of the long rails in the first layer (as reasoned in the claim 1 rejection the claimed via configuration is a design choice according to required circuitry configuration), and
a second set of the second rails (PR72) in the second layer is coupled to the first supply ([0023]: “VDD” being the first supply; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration) by way of another via coupled to the second set of the long rails in the first layer (as reasoned in the claim 1 rejection the claimed via configuration is a design choice according to required circuitry configuration).
Regarding claim 4, Lee in view of Liebman discloses the method of claim 1 (Lee: Fig. 7), wherein:
a first set of the short rails (selecting one of the short rails as the first set) in the first layer is coupled to a second supply ([0023]: “VSS” is the second supply; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration), and
a second set of the short rails (selecting another of the short rails as the second set) in the first layer is coupled to a third supply ([0023]: “VDD” being the third supply; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration).
Regarding claim 5, Lee in view of Liebman discloses the method of claim 4 (Lee: Fig. 7), wherein:
a third set of the second rails (PR71) in the second layer is coupled to the second supply ([0023]: “VSS” is ground, consistent with the disclosure, as well as the ordinary and customary meaning of VSS; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration) by way of a via coupled to the first set of the short rails in the first layer (as reasoned in the claim 1 rejection the claimed via configuration is a design choice according to required circuitry configuration), and
a fourth set of the second rails (PR72) in the second layer is coupled to the third supply ([0023]: “VDD” is the first supply; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration) by way of another via coupled to the second set of the short rails in the first layer (as reasoned in the claim 1 rejection the claimed via configuration is a design choice according to required circuitry configuration).
Regarding claim 6, Lee in view of Liebman discloses the method of claim 1 (Lee: Fig. 7), wherein: the first rails have a first width (as measured in the X direction), and the second rails have a second width (as measured in the X direction) that is greater than the first width (greater in the X direction because it extends beyond a full overlap).
Regarding claim 21, Lee in view of Liebman discloses the method of claim 1 (Lee: Fig. 7), wherein each of the short rails is coupled to a single one of the second rails (as reasoned in the claim 1 rejection, the claimed coupling configuration is a design choice according to required circuitry configuration).
Regarding claim 22, Lee in view of Liebman discloses the method of claim 1 (Lee: Fig. 7), wherein each of the short rails overlaps at least two of the second rails (overlaps PR71 and PR72 in at least the Z direction and directions angled between the Z and Y directions).
Regarding claim 27, Lee in view of Liebman discloses the method of claim 1 (Lee: Fig. 7), wherein at least one of the long rails in the first layer extends across the porosity channel (at least partially across in the Y direction) between the adjacent second rails (between in the Y direction).
Regarding independent claim 11, Lee discloses a method comprising:
fabricating a memory instance (Fig. 7: C71 is relied upon here to teach a generic standard cell);
fabricating a power distribution network having buried power rails (PR71-74; these rails being buried in a dielectric, [0075]: “BEOL may include…adding a dielectric, planarizing, forming holes, adding metal layers, forming vias”) routed underneath (selecting positive Z direction as underneath) the memory instance; and
fabricating the buried power rails with first rails (See annotated figure) in a first layer (M2) and second rails (PR71-PR74; corresponding to Fig. 1: PR11, PR12) that are arranged perpendicular to the first rails (perpendicular in the X/Y plane) in a second layer (M1), wherein:
the first rails include long rails (See annotated figure) with a first length (as measured in the Y direction) and short rails (see annotated figure) with a second length (as measured in the Y direction) that is less than the first length (“less than” is determined by the long rails extending completely over and beyond the second power rails in the Y direction, while first power rails are fully confined within the cell boundary), and
the long rails and the short rails are separately coupled to the second rails with vias that extend between the first layer and the second layer (Fig. 1 shows vias coupling and extending between the first and second layers),
wherein adjacent (indirectly adjacent) second rails in the second layer (the M1 components of PR71/PR73) define a porosity channel (Fig. 7: See annotated figure for the designation of this region) therebetween, and wherein at least one of the short rails in the first layer terminates (terminates in the Y direction) before extending completely across the porosity channel such that a spatial gap (See annotated figure, a collective gap, with two of many gap portions annotated) is maintained within the porosity channel for routing one or more additional second rails in the second layer (the M1 component of PR72 is routed in this channel and overlaps the gap in the Z direction).
Lee discloses vias and the first and second layers (Fig. 1: vias, M1, M2) but fails to explicitly illustrate the via configuration for the selected embodiment (Fig. 7). Thus, Lee fails to disclose “the long rails and the short rails are separately coupled to the second rails with vias that extend between the first layer and the second layer”.
However, Lee teaches:
The first rails can be designed to perform the function of power rails ([0049]: “the power rail PR71 may include a pattern L71 of the M2 layer”).
All of the chosen first rails (of the selected Fig. 7 embodiment) overlap the second rails (in the Z direction). Thus, the first rails are spatially capable of coupling to the second rails (of the underlying M1 layer) in situations where a via is included.
The power rail arrangement may be varied as a design choice according to required circuitry configuration (Fig. 7: C71-C79 have varied M2 rail configurations; [0021]: “patterns of the M2 layer and the pattern of the M3 layer may be determined in a routing operation after the standard cells C11 and C12 are placed in a design process of the standard cells”).
Thus, separately coupling the long and short rails (of the first power rails in the M2 layer) to the second rails (of the overlapping M1 layer) with vias used in the same way as those disclosed in the Fig. 1 embodiment would have been obvious to one of ordinary skill in the art before the effective filing date because it is a design choice according to required circuitry configuration. Lee provides a teaching to motivate one to include the claimed coupling configuration in that it would enable improved electrical operation ([0049]: “an IR drop may be mitigated”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date because it is a design choice encompassed by the prior art that would enable improved electrical operation. MPEP 2143 (I)(G). MPEP 2144 (I).
Lee fails to disclose the generic standard cell (Fig. 7: C71) is a memory instance. Thus, Lee fails to disclose “fabricating a memory instance”, as recited in the claim.
Liebman discloses a similar fabricating method where a standard cell is described as a memory instance ([0031]: “standard cells, such as inverter cells, NAND cells, NOR cells, and the like from a standard cell library”).
Modifying the standard cell of Lee to be a memory instance would arrive at the claimed method. Liebman teaches a design incentive for configuring a standard cell as a memory instance in that it would provide a cell according to required circuitry function ([0031]: “active devices, such as logic circuits, analog circuits, memory circuits…configured to perform one or more operations”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed memory instance because it a design incentive encompassed within the prior art, chosen according to required circuitry function. MPEP 2143 (I)(F).
Regarding claim 12, Lee in view of Liebman discloses the method of claim 11 (Lee: Fig. 1), further comprising:
disposing the first rails in the first layer (the first rails are in M2);
and disposing the second rails perpendicular to the first rails in the second layer (the second rails are in M1 and perpendicular in the X/Y plane);
identifying the long rails of the first rails with the first length (as reasoned in the claim 11 rejection, these rails are deliberately formed to have specific dimensions, shapes, and relations to produce a desired electrical path. Therefore, the respective lengths of each power rail would necessarily have been known, i.e., identified during the method);
identifying the short rails of the first rails with the second length that is less than the first length (as reasoned in the claim 11 rejection, these rails are deliberately formed to have specific dimensions, shapes, and relations to produce a desired electrical path. Therefore, the respective lengths of each power rail would necessarily have been known, i.e., identified during the method);
and separately coupling the long rails and the short rails to the second rails with vias that extend between the first layer and the second layer (as reasoned in the claim 11 rejection, the claimed via configuration is a design choice according to required circuitry configuration).
Regarding claim 23, Lee in view of Liebman discloses the method of claim 11 (Lee: Fig. 7), wherein each of the short rails is coupled to a single one of the second rails (as reasoned in the claim 11 rejection, the claimed coupling configuration is a design choice according to required circuitry configuration).
Regarding claim 24, Lee in view of Liebman discloses the method of claim 11 (Lee: Fig. 7), wherein each of the short rails overlaps at least two of the second rails (overlaps PR71 and PR72 in at least the Z direction and directions angled between the Z and Y directions).
Regarding independent claim 17, Lee discloses a device comprising:
a memory instance (Fig. 7: C71 is relied upon here to teach a generic standard cell); and
a power distribution network having buried power rails (PR71-74; these rails being buried in a dielectric, [0075]: “BEOL may include…adding a dielectric, planarizing, forming holes, adding metal layers, forming vias”) routed underneath (selecting positive Z direction as underneath) the memory instance, wherein:
the buried power rails have first rails (See annotated figure) disposed in a first layer (M2) and second rails (PR71-PR74; corresponding to Fig. 1: PR11, PR12) disposed perpendicular to the first rails (perpendicular in the X/Y plane) in a second layer (M1),
the first rails have long rails (See annotated figure) with a first length (as measured in the Y direction) and short rails (See annotated figure) with a second length (as measured in the Y direction) that is less than the first length (“less than” is determined by the long rails extending completely over and beyond the second power rails in the Y direction, while first power rails are fully confined within the cell boundary), and
the long rails and the short rails are separately coupled to the second rails with vias that extend between the first layer and the second layer (Fig. 1 shows vias coupling and extending between the first and second layers),
wherein adjacent (indirectly adjacent) second rails in the second layer (the M1 components of PR71/PR73) define a porosity channel (Fig. 7: See annotated figure for the designation of this region) therebetween, and wherein at least one of the short rails in the first layer terminates (terminates in the Y direction) before extending completely across the porosity channel such that a spatial gap (See annotated figure, a collective gap, with two of many gap portions annotated) is maintained within the porosity channel for routing one or more additional second rails in the second layer (the M1 component of PR72 is routed in this channel and overlaps the gap in the Z direction).
Lee discloses the vias and the first and second layers (Fig. 1: vias, M1, M2) but fails to explicitly illustrate the via configuration for the selected embodiment (Fig. 7). Thus, Lee fails to disclose “the long rails and the short rails are separately coupled to the second rails with vias that extend between the first layer and the second layer”.
However, Lee teaches:
The first rails can be designed to perform the function of power rails ([0049]: “the power rail PR71 may include a pattern L71 of the M2 layer”).
All of the chosen first rails (of the selected Fig. 7 embodiment) overlap the second rails (in the Z direction). Thus, Lee teaches the first rails are spatially capable of coupling to the second rails (of the underlying M1 layer) in situations where a via is included.
The power rail arrangement may be varied as a design choice according to required circuitry configuration (Fig. 7: C71-C79 have varied M2 rail configurations; [0021]: “patterns of the M2 layer and the pattern of the M3 layer may be determined in a routing operation after the standard cells C11 and C12 are placed in a design process of the standard cells”).
Thus, separately coupling the long and short rails (of the first power rails in the M2 layer) to the second rails (of the overlapping M1 layer) with vias used in the same way as those disclosed in the Fig. 1 embodiment would have been obvious to one of ordinary skill in the art before the effective filing date because it is a design choice according to required circuitry configuration. Lee provides a teaching to motivate one to include the claimed coupling configuration in that it would enable improved electrical operation ([0049]: “an IR drop may be mitigated”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date because it is a design choice encompassed by the prior art that would enable improved electrical operation. MPEP 2143 (I)(G). MPEP 2144 (I).
Lee fails to disclose the generic standard cell (Fig. 7: C71) is a memory instance. Thus, Lee fails to disclose “a memory instance”, as recited in the claim.
Liebman discloses a similar device where a standard cell is described as a memory instance ([0031]: “standard cells, such as inverter cells, NAND cells, NOR cells, and the like from a standard cell library”).
Modifying the generic standard cell of Lee to be a memory instance would arrive at the claimed device. Liebman teaches a design incentive for configuring a standard cell as a memory instance in that it would provide a cell according to required circuitry function ([0031]: “active devices, such as logic circuits, analog circuits, memory circuits…configured to perform one or more operations”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed memory instance because it a design incentive encompassed within the prior art, chosen according to required circuitry function. MPEP 2143 (I)(F).
Regarding claim 18, Lee in view of Liebman discloses the device of claim 17 (Lee: Fig. 7), wherein: the first rails have a first width (as measured in the X direction), and the second rails have a second width (as measured in the X direction) that is greater than the first width (greater in the X direction because it extends beyond a full overlap).
Regarding claim 19, Lee in view of Liebman discloses the device of claim 17 (Lee: Fig. 7), wherein:
a first set of the long rails (selecting one of the long rails as the first set) in the first layer is coupled to ground ([0023]: “VSS” is ground, consistent with the disclosure, as well as the ordinary and customary meaning of VSS; as reasoned in the claim 17 rejection the claimed coupling configuration is a design choice according to required circuitry configuration),
a second set of the long rails (selecting another of the long rails as the second set) in the first layer is coupled to a first supply ([0023]: “VDD” is the first supply; as reasoned in the claim 17 rejection the claimed coupling configuration is a design choice according to required circuitry configuration),
a first set of the short rails (selecting one of the short rails as the first set) in the first layer is coupled to a second supply ([0023]: “VSS” is the second supply because it supplies a different first rail and therefore is an electrical path different from the path supplying the first set of short rails; as reasoned in the claim 17 rejection the claimed coupling configuration is a design choice according to required circuitry configuration), and
a second set of the short rails (selecting another of the short rails as the second set) in the first layer is coupled to a third supply ([0023]: “VDD” is the third supply because it supplies a different first rail and therefore is an electrical path different from the path supplying the first set of short rails; as reasoned in the claim 17 rejection the claimed coupling configuration is a design choice according to required circuitry configuration).
Regarding claim 20, Lee in view of Liebman discloses the device of claim 19 (Lee: Fig. 7), wherein:
a first set of the second rails (PR71) in the second layer is coupled to ground ([0023]: “VSS” is ground, consistent with the disclosure, as well as the ordinary and customary meaning of VSS; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration) by way of a via coupled to the first set of the long rails in the first layer (as reasoned in the claim 1 rejection the claimed via configuration is a design choice according to required circuitry configuration),
a second set of the second rails (PR72) in the second layer is coupled to the first supply ([0023]: “VDD” is the first supply; as reasoned in the claim 1 rejection the claimed coupling configuration is a design choice according to required circuitry configuration) by way of another via coupled to the second set of the long rails in the first layer (as reasoned in the claim 1 rejection the claimed via configuration is a design choice according to required circuitry configuration),
a third set of the second rails (PR73) in the second layer is coupled to the second supply by way of a via (selecting the same via reasoned to couple the first set of short rails to VSS, from the claim 19 rejection; both PR71 and PR73 would be coupled to VSS thus meeting the claim) coupled to the first set of the short rails in the first layer (as reasoned in the claim 17 rejection the claimed via configuration is a design choice according to required circuitry configuration), and
a fourth set of the second rails (PR74) in the second layer is coupled to the third supply by way of another via (selecting the same via reasoned to couple the second set of short rails to VDD, from the claim 19 rejection; both PR72 and PR74 would be coupled to VDD thus meeting the claim) coupled to the second set of the short rails in the first layer (as reasoned in the claim 17 rejection the claimed via configuration is a design choice according to required circuitry configuration).
Regarding claim 25: Lee in view of Liebman discloses the device of claim 17 (Lee: Fig. 7), wherein each of the short rails is coupled to a single one of the second rails (as reasoned in the claim 17 rejection, the claimed coupling configuration is a design choice according to required circuitry configuration).
Regarding claim 26, Lee in view of Liebman discloses the device of claim 17 (Lee: Fig. 7), wherein each of the short rails overlaps at least two of the second rails (overlaps PR71 and PR72 in at least the Z direction and directions angled between the Z and Y directions).
Allowable Subject Matter
Claim 28 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claim 28 is the inclusion of the limitation “determining porosity associated with the second layer by locating empty space corresponding to the spatial gap within the porosity channel; and routing the one or more additional second rails within the second layer based on the determined porosity” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “determining porosity”, “routing”, and “based on the determined porosity” in combination with all other limitations in claims 28 and 1. This particular design rule was not disclosed, suggested, or rendered obvious by the prior art when considered in combination with the rest or the claim limitations.
Response to Arguments
Applicant's arguments filed 5/19/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claims 1, 11, and 17 that “Lee and Liebman, whether considered alone or in combination, fail to teach or suggest the amended limitations of claim 1.
Independent claims 11 and 17 include similar limitations as claim 1. Accordingly, Applicant respectfully submits that claims 1, 11, and 17 are patentable over the cited combination of Lee and Liebman”. Remarks at pg. 9.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 1, 11, and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The examiner points to MPEP 2111: Broadest Reasonable Interpretation and finds the claims as written describing structural arrangements consistent with the disclosure, however, also encompassing a plurality of alternative configurations including those cited in the instant Office action. Additionally, and beyond the guidance provided by MPEP 2111, the examiner has looked to MPEP 2115 and 2116 for guidance regarding the instant method and device claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
Prosecution Insights