Detailed Action
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/16/2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 4-7, 10, 12, 14-16 and 19-20 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon et. Al. (US 20140374797 A1 newly cited Kwon having a foreign priority date 06/24/2013) as applied to claims 1 and 6 and further in view of Pawlak et. Al. (US 20140217467 A1 hereinafter Pawlak).
Regarding claim 1, Kwon teaches in Figs. 13 with associated text an integrated circuit, comprising:
a semiconductor substrate (100 paragraph [0113]);
an n-channel fin field effect transistor (finFET) (II paragraph [0113]), comprising:
an n-channel fin 220 disposed over the semiconductor substrate, the n-channel fin including a III-V semiconductor material (paragraph [0084]);
a first gate dielectric layer 203 disposed on the n-channel fin (paragraph [0084]); and
a first gate 202 disposed on the first gate dielectric layer; and
a p-channel finFET (I paragraph [0113]), comprising:
a p-channel fin (120 and 134 or 120, 134 and 132 together) disposed over the semiconductor substrate, the p-channel fin comprising silicon-germanium (134 includes SiGeC which includes SiGe paragraph [0076]);
a second gate dielectric layer 103 disposed on the p-channel fin; and
a second gate 102 disposed on the second gate dielectric layer (Fig. 13);
and an isolation dielectric layer (105 and 205) disposed partially on the semiconductor substrate between the n-channel finFET and the p-channel finFET, the isolation dielectric layer being laterally adjacent to the n-channel fin and the p-channel fin (Fig. 13, [0054] and [0087]).
Kwon does not specify the p-channel finFET is adjacent to the n-channel finFET, a field oxide in a semiconductor substrate, the field oxide disposed between an n-channel finFET and a p-channel finFET; and the isolation dielectric layer disposed partially on the field oxide between the n-channel finFET and the p-channel finFET.
Pawlak teaches in Fig. 3B with associated text a structure similar to that of Kwon wherein a p-channel finFET 130P adjacent to an n-channel finFET 130N (Fig. 3B, [0037]), a field oxide 122 in a semiconductor substrate (parts of 108 and 116 supporting the fins) (Fig. 3B, [0037]), the field oxide disposed between the n-channel finFET and the p-channel finFET (Fig. 3B); and an isolation dielectric layer 133D disposed partially on the semiconductor substrate between the n-channel finFET and the p-channel finFET and partially on the field oxide between the n-channel finFET and the p-channel finFET (on a sidewall of the field oxide) (Fig. 3B, [0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use adjacent NMOS and PMOS transistors and the field oxide structure of Pawlak in the device of Kwon because according to Pawlak such a structure provides device designers with a new and effective way to form transistor devices with alternative channel materials in a way that is believed to be more efficient and compatible with traditional CMOS manufacturing activities and CMOS-based product designs. Thus, the methods and devices disclosed herein will enable device designers to meet the ongoing challenges of improving the performance of integrated circuit products.
Regarding claim 4, Kwon teaches a buffer layer (132 and/or 110) disposed between the p-channel fin and the semiconductor substrate, the buffer layer comprising germanium (paragraph [0063]).
Regarding claims 5, Kwon teaches the integrated circuit of claim 1, further comprising a buffer layer (240 and/or 210 of Kwon) disposed between the n-channel fin and the semiconductor substrate, the buffer layer comprising germanium (paragraph [0135]).
Regarding claim 6, Kwon teaches an integrated circuit, comprising:
a silicon substrate (100 paragraph [0113]);
an n-channel fin field effect transistor (finFET) (II paragraph [0113]) having an n-channel fin 220 over the silicon substrate,
the n-channel fin comprising a III-V semiconductor material (paragraph [0084]);
a p-channel finFET (I paragraph [0113]) having a p-channel fin (120 and possibly 130) over the silicon substrate, the p-channel fin comprising germanium or silicon-germanium (134 includes SiGeC which includes SiGe paragraph [0076]); and
an isolation dielectric layer (105 and 205) disposed partially on the silicon substrate between the n-channel finFET and the p-channel finFET, the isolation dielectric layer being laterally adjacent to the n- channel fin and the p-channel fin, wherein the n-channel fin and the p-channel fin extend above the isolation dielectric layer (paragraph [0123] and Fig. 13).
Kwon does not specify the p-channel finFET is adjacent to the n-channel finFET, a field oxide in a semiconductor substrate, the field oxide disposed between an n-channel finFET and a p-channel finFET; and the isolation dielectric layer disposed partially on the field oxide between the n-channel finFET and the p-channel finFET.
Pawlak teaches in Fig. 3B with associated text a structure similar to that of Kwon wherein a p-channel finFET 130P adjacent to an n-channel finFET 130N (Fig. 3B, [0037]), a field oxide 122 in a semiconductor substrate (parts of 108 and 116 supporting the fins) (Fig. 3B, [0037]), the field oxide disposed between the n-channel finFET and the p-channel finFET (Fig. 3B); and an isolation dielectric layer 133D disposed partially on the semiconductor substrate between the n-channel finFET and the p-channel finFET and partially on the field oxide between the n-channel finFET and the p-channel finFET (on a sidewall of the field oxide) (Fig. 3B, [0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use adjacent NMOS and PMOS transistors and the field oxide structure of Pawlak in the device of Kwon because according to Pawlak such a structure provides device designers with a new and effective way to form transistor devices with alternative channel materials in a way that is believed to be more efficient and compatible with traditional CMOS manufacturing activities and CMOS-based product designs. Thus, the methods and devices disclosed herein will enable device designers to meet the ongoing challenges of improving the performance of integrated circuit products.
Regarding claim 7, Kwon teaches the n-channel fin comprises a first buffer (240 and/or 210) disposed on the silicon substrate between the silicon substrate and the III-V semiconductor material (Fig. 13), the first buffer comprising germanium (paragraph [0135]) and the III-V semiconductor material comprising GaAs (paragraph [0084]);
the n-channel finFET further comprises: a first gate dielectric layer 203 disposed on the n-channel fin; and
a first gate 202 disposed on the first gate dielectric layer; and
the p-channel finFET further comprises: a second gate dielectric layer 103 disposed on the p-channel fin; and
a second gate 102disposed on the second gate dielectric layer.
Regarding claim 10, Kwon teaches the p-channel fin further comprises a second buffer (132, 134 and/or 110) d disposed on the silicon substrate, the second buffer comprising germanium (paragraph [0063]).
Regarding claim 12, Kwon teaches a semiconductor structure, comprising:
a silicon substrate (100 paragraph [0113]);
an n-channel fin field effect transistor (finFET) (II paragraph [0113]), comprising:
an n-channel fin 220 disposed over the silicon substrate, the n-channel fin including a III-V semiconductor material (paragraph [0084]);
a first gate dielectric layer 203 disposed on the n-channel fin; and
a first gate 202 disposed on the first gate dielectric layer; and
a p-channel finFET (I paragraph [0113]), comprising:
a p-channel fin (120 and 134 or 120, 134 and 132 together) disposed over the silicon substrate, the p-channel fin including germanium or silicon-germanium (134 includes SiGeC which includes SiGe paragraph [0076]);
a second gate dielectric layer 103 disposed on the p-channel fin; and
a second gate 102 disposed on the second gate dielectric layer (Fig. 13).
and an isolation dielectric layer (105 and 205) disposed partially on the semiconductor substrate between the n-channel finFET and the p-channel finFET (Fig. 13, [0054] and [0087]).
Kwon does not specify the p-channel finFET is adjacent to the n-channel finFET, a field oxide in a semiconductor substrate, the field oxide disposed between an n-channel finFET and a p-channel finFET; and the isolation dielectric layer disposed partially on the field oxide between the n-channel finFET and the p-channel finFET.
Pawlak teaches in Fig. 3B with associated text a structure similar to that of Kwon wherein a p-channel finFET 130P adjacent to an n-channel finFET 130N (Fig. 3B, [0037]), a field oxide 122 in a semiconductor substrate (parts of 108 and 116 supporting the fins) (Fig. 3B, [0037]), the field oxide disposed between the n-channel finFET and the p-channel finFET (Fig. 3B); and an isolation dielectric layer 133D disposed partially on the semiconductor substrate between the n-channel finFET and the p-channel finFET and partially on the field oxide between the n-channel finFET and the p-channel finFET (on a sidewall of the field oxide) (Fig. 3B, [0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use adjacent NMOS and PMOS transistors and the field oxide structure of Pawlak in the device of Kwon because according to Pawlak such a structure provides device designers with a new and effective way to form transistor devices with alternative channel materials in a way that is believed to be more efficient and compatible with traditional CMOS manufacturing activities and CMOS-based product designs. Thus, the methods and devices disclosed herein will enable device designers to meet the ongoing challenges of improving the performance of integrated circuit products.
Regarding claim 14, Kwon teaches the III-V semiconductor material comprises gallium arsenide (paragraph [0084]).
Regarding claim 15, Kwon teaches the III-V semiconductor material comprises indium gallium arsenide (paragraph [0084]).
Regarding claim 16, Kwon teaches the n-channel fin and the p- channel fin extend above the isolation dielectric layer (Fig. 13).
Regarding claim 19, Kwon teaches a buffer layer (240 and/or 210) disposed between the n-channel fin and the semiconductor substrate, the buffer layer comprising germanium (paragraph [0135]).
Regarding claim 20, Kwon teaches the n- channel fin and the p-channel fin extend above the isolation dielectric layer (Fig. 13).
Claim 3 and 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Lee as applied to claims 1 and 6 and further in view of Pawlak et. Al. (US 20140217467 A1 cited in IDS hereinafter Pawlak).
Regarding claim 3 and 9, Kwon in view of Lee teaches the integrated circuit of claims 1 and 6.
Kwon does not specify the n-channel fin comprises indium gallium arsenide however Kwon teaches the n-channel fin comprises In and/or Ga and As (paragraph [0084]).
Pawlak teaches an n-channel fin 108 comprises indium gallium arsenide (paragraph [0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use InGaAs n the n-channel fin of Kwon in view of Lee as taught by Pawlak because according to Pawlak an In.sub.xGa.sub.1-xAs layer 108 may have a lattice constant of about 5.65-6.06 .ANG.--depending on `x` parameter (paragraph [0031]) so that the lattice parameter mismatch between the fin and an underlying material may be optimized by using such a material.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Lee as applied to claim 7 further in view of Chu (US 7145167 B1 cited in IDS).
Regarding claims 11, Kwon in view of Lee teaches the integrated circuit of claim 7.
Kwon does not specify a germanium atomic fraction of the first buffer is graded.
Chu discloses in Fig. 11 with associated text a buffer formed so that a germanium atomic fraction of said buffer is graded (column 8, lines 38-50).
It would have been obvious to one of ordinary skill in the art at the time of the invention to use a graded buffer similar to that taught by Chu for the buffer of Kwon in view of Lee because according to Chu such a buffer serves to relax the strain caused by the lattice mismatch between the top surface or interface 19 of relaxed layer 12C and the underlying Si substrate (column 8, lines 38-50).
Claims 17-18 and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Lee as applied to claim 12, 1 and 6 and further in view of Goto et. Al. (US 20090008716 A1 hereinafter Goto).
Regarding claims 17, Kwon in view of Lee teaches the semiconductor structure of claim 12.
Kwon does not specify a planar n-channel metal oxide semiconductor (NMOS) transistor on the silicon substrate; and a planar p-channel metal oxide semiconductor (PMOS) transistor on the silicon substrate.
Goto discloses in Fig. 4 with associated text a planar n-channel metal oxide semiconductor (NMOS) transistor 30 on a silicon substrate 2 ([0024]) with a structure similar to that of Kwon Fig. 4); and a planar p-channel metal oxide semiconductor (PMOS) transistor 40 on the silicon substrate (Fig. 4).
It would have been obvious to one of ordinary skill in the art at the time of the invention to use planar transistors as taught by Goto on the substrate of Kwon in view of Lee because according to Goto an embedded integrated circuit has been proposed in which a fin type metal oxide semiconductor field effect transistor (MOSFET) having less dispersion in a threshold voltage is used in a static random access memory (SRAM), and a planar type MOSFET to which the prior art can be applied is used in any of other circuits [0002] so that such planar transistors would be useful in forming similar circuit in Kwon in view of Lee.
Regarding claims 18, Kwon in view of Lee and Goto teaches the semiconductor structure of claim 17.
Kwon does not specify the planar NMOS transistor and the n-channel finFET are located in a p-type well in the silicon substrate; and the planar PMOS transistor and the p-channel finFET are located in a n-type well in the silicon substrate.
Goto discloses the planar NMOS transistor and the n-channel finFET are located in a p-type well in the silicon substrate; and the planar PMOS transistor and the p-channel finFET are located in a n-type well in the silicon substrate [0044].
It would have been obvious to one of ordinary skill in the art at the time of the invention to use planar transistors as taught by Goto on the substrate of Kwon in view of Lee and Goto because according to Goto when an n-channel planar type MOSFET 10 and an n-channel fin type MOSFET 20 are formed, a p-type impurity such as B is implanted as the conductivity type impurity, thereby forming a p-type well region. On the other hand, when a p-channel planar type MOSFET 10 and a p-channel fin type MOSFET 20 are formed, a p-type impurity such as P is implanted as the conductivity type impurity, thereby forming an n-type well region [0044] so that such wells are suitable for forming these transistors.
Regarding claims 21 and 23, Kwon in view of Lee teaches the integrated circuit of claim 1 and 6, further comprising a field oxide 105 in the silicon substrate [0054].
Kwon does not specify first and second field isolation structures in the semiconductor substrate and a planar NMOS transistor and a planar PMOS transistor disposed in the silicon substrate, wherein the planar NMOS transistor is laterally separated from the n-channel finFET by the first field isolation structure and the planar PMOS transistor is laterally separated from the p-channel finFET by the second field isolation structure.
Goto discloses in Fig. 4 with associated text a planar NMOS transistor 30 and a planar PMOS transistor 40 disposed in the semiconductor substrate (Fig. 4), wherein the planar NMOS transistor is laterally separated from a n-channel finFET 50 by a first field insulating structure (3 between the 32 and 42) [0042] and the planar PMOS transistor is laterally separated from the p-channel finFET 60 by a second field insulating structure (3 between 50 and 42) (Fig. 4).
It would have been obvious to one of ordinary skill in the art at the time of the invention to use planar transistors and field oxide as taught by Goto on the substrate of Kwon in view of Lee because according to Goto an embedded integrated circuit has been proposed in which a fin type metal oxide semiconductor field effect transistor (MOSFET) having less dispersion in a threshold voltage is used in a static random. access memory (SRAM), and a planar type MOSFET to which the prior art can be applied is used in any of other circuits [0002] so that such planar transistors would be useful in forming similar circuit in Kwon.
Regarding claims 22 and 24, Kwon in view of Lee and Goto teaches the integrated circuit of claim 21 and 23.
Kwon does not specify the planar NMOS transistor and the n-channel finFET are located in a p-type well in the silicon substrate; and the planar PMOS transistor and the p-channel finFET are located in a n-type well in the silicon substrate.
Goto discloses the planar NMOS transistor and the n-channel finFET are located in a p-type well in the silicon substrate; and the planar PMOS transistor and the p-channel finFET are located in a n-type well in the silicon substrate [0044].
It would have been obvious to one of ordinary skill in the art at the time of the invention to use planar transistors as taught by Goto on the substrate of Kwon in view of Lee and Goto because according to Goto when an n-channel planar type MOSFET 10 and an n-channel fin type MOSFET 20 are formed, a p-type impurity such as B is implanted as the conductivity type impurity, thereby forming a p-type well region. On the other hand, when a p-channel planar type MOSFET 10 and a p-channel fin type MOSFET 20 are formed, a p-type impurity such as P is implanted as the conductivity type impurity, thereby forming an n-type well region [0044] so that such wells are suitable for forming these transistors.
Regarding claim 25, Kwon in view of Lee teaches the integrated circuit of claim 6.
Kwon does not specify a planar NMOS transistor and a planar PMOS transistor disposed in the silicon substrate, wherein: the planar NMOS transistor and the n-channel finFET are located in a p-type well in the silicon substrate; and the planar PMOS transistor and the p-channel finFET are located in a n-type well in the silicon substrate.
Goto discloses in Fig. 4 with associated text a planar NMOS transistor 30 and a planar PMOS transistor 40 disposed in the silicon substrate, wherein: the planar NMOS transistor and the n-channel finFET are located in a p-type well in the silicon substrate; and the planar PMOS transistor and the p-channel finFET are located in a n-type well in the silicon substrate [0044].
It would have been obvious to one of ordinary skill in the art at the time of the invention to use planar transistors and field oxide as taught by Goto on the substrate of Kwon in view of Lee because according to Goto an embedded integrated circuit has been proposed in which a fin type metal oxide semiconductor field effect transistor (MOSFET) having less dispersion in a threshold voltage is used in a static random, furthermore according to Goto an n-channel planar type MOSFET 10 and an n-channel fin type MOSFET 20 are formed, a p-type impurity such as B is implanted as the conductivity type impurity, thereby forming a p-type well region. On the other hand, when a p-channel planar type MOSFET 10 and a p-channel fin type MOSFET 20 are formed, a p-type impurity such as P is implanted as the conductivity type impurity, thereby forming an n-type well region [0044] so that such wells are suitable for forming these transistors.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-7, 9-12 and 13-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Glass et. Al. (US 20140027860 A1) teaches a device in Fig. 8 with associated text a device with SiGe in the p-channels and III-V material in the n-channels [0030] that would be relevant to the independent claims.
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/AARON J GRAY/Examiner, Art Unit 2897