DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 2, 7, 10, 12, 13, 15, 21, 22, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Griebenow (US 2011/0291269 A1) in view of Yoshida (JP03064050A, Machine Translation) in view of Mandal (US 2017/0324015 A1).
Regarding claims 1, 2, 10, and 13, Griebenow discloses a circuit comprising (See Fig. 1k):
a plurality of heat sources (123D, circuit elements [0046]) positioned on a front side of a substrate (see Fig. 1n analogous structure is present in Fig. 1k, substrate is where structure 140 is placed)
an array of thermoelectric structures (multiple p and n-type thermoelectric elements [0036][0039]) comprising:
a p-type region (128B, [0036]) positioned on the front side of the substrate; and an n-type region (130A, [0039]) positioned on the front side of the substrate;
a wire positioned on the front side of the substrate (see Fig. 1n/1p, 135) overlying each of the p-type region and the n-type region and configured to electrically couple the p-type region to the n-type region ([0044]);
a first electrical connection (141 on 128B see Fig. 1n) to electrically connect the p-type region to a first rail structure (see any one of 155, in Fig. 1p)
a second electrical connection (141 on 130A see Fig. 1n) to electrically connect the n-type region to a second rail structure (see any one of 155, in Fig. 1p).
Griebenow does not disclose that the heat source and the p-type region and n-type region are aligned in the same plane wherein the plane is defined by the front side of the substrate and wherein the heat source is between the p-type and n-type region in the same plane.
Griebenow discloses that the heat sources can be repositioned into substrate (121) (the device level 123 may represent a crystalline portion of the substrate 121 [0030], and also can be resized [0046]).
Yoshida discloses that a heat source (5 and 6) and a p-type region (4) and an n-type region (3) are aligned in the same plane wherein the plane is defined by the front side of the substrate(2) and wherein the heat source is between and adjacent to the p-type and n-type region in the same plane and thermally connected to the doped regions and also electrically isolated ([0011]).
Yoshida further discloses that having circuit heat sources arranged in this manner relative to the Peltier elements helps with reducing the size of the package of the semiconductor device and miniaturizing the electronic circuit.
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the position of any of the heat sources of Griebenow so that the heat sources and the p-type region and n-type region are aligned in the same plane wherein the plane is defined by the front side of the substrate and wherein any of the heat sources are between the p-type and n-type regions as disclosed by Yoshida because Griebenow discloses heat sources can be rearranged and Yoshida discloses that the heat sources can be in the same substrate where the thermoelectric regions are formed and this helps with reducing the size of the package of the semiconductor device and miniaturizing the electronic circuit.
Griebenow discloses a first via (see via 135C formation in Fig. 1k) electrically coupled to the p-type region (128B) and the wire (135) and extending between the p-type region and the wire in a direction perpendicular to the plane;
a second via electrically (see vias noted by dashed lines formed over 130 A and resulting structure in Fig. 1l) coupled to the n-type region and the wire and extending
between the n-type region and the wire in the direction.
Griebenow discloses a first power rail (see any one of 155 in Fig. 1p) on a back side of the substrate and comprising a first surface parallel to the plane and a second power rail (see any one of 155, in Fig. 1p) on the back side of the substrate and comprising a second surface parallel to the plane and an energy device (see Fig. 1q, 110 [0056]) coupled to each of the first and second power rail structures.
However, Griebenow does not disclose that the first and second power rails are directly connected to p and n-type thermoelectric structures with third and fourth conductive via structures.
Mandal discloses that the first and second electrical connections are via structures (see 24 and/or 54 and 56 [0028] see Figs. 5 and 6 [0017]) to backside connection structures (see railing portions which can be wirings or portions of wirings in substrate 26 which are parallel to thermoelectric elements (42 and 40)).
It would have been obvious to one of ordinary skill in the art at the time of filing to replace the contact structures between the p-type and n-type regions and the first and second power rails with the conductive via structures as disclosed by Mandal because Griebenow discloses that such connections are commonly used and Mandal discloses it is an appropriate electrical connector between p-type and n-type regions and power rails.
Regarding claims 7 and 15, modified Griebenow discloses all of the claim limitations as set forth above.
In addition, Griebenow discloses a heat sink can be added to the stacked configuration to remove additional heat ([0026]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the substrate (151) of Griebenow by adding an external heat sink as disclosed by Griebenow because Griebenow discloses it is appropriate to do so and it will remove additional heat.
Regarding claim 21, Griebenow discloses a circuit comprising (See Fig. 1k):
a plurality of heat sources (123D, circuit elements [0046]) positioned on a front side of a substrate (see Fig. 1n analogous structure is present in Fig. 1k, substrate is where structure 140 is placed)
an array of thermoelectric structures (multiple p and n-type thermoelectric elements [0036][0039]) comprising:
a p-type region (128B, [0036]) positioned on the front side of the substrate; and an n-type region (130A, [0039]) positioned on the front side of the substrate;
a wire positioned on the front side of the substrate (see Fig. 1n/1p, 135) overlying each of the p-type region and the n-type region and configured to electrically couple the p-type region to the n-type region ([0044]);
a first electrical connection (141 on 128B see Fig. 1n) to electrically connect the p-type region to a first rail structure (see any one of 155, in Fig. 1p)
a second electrical connection (141 on 130A see Fig. 1n) to electrically connect the n-type region to a second rail structure (see any one of 155, in Fig. 1p); and
an energy device (see Fig. 1q, 110 [0056]) coupled to each of the first and second power structures.
Griebenow does not disclose that the heat source and the p-type region and n-type region are aligned in the same plane wherein the plane is defined by the front side of the substrate and wherein the heat source is between the p-type and n-type region in the same plane.
Griebenow discloses that the heat sources can be repositioned into substrate (121) (the device level 123 may represent a crystalline portion of the substrate 121 [0030], and also can be resized or repositioned [0046]).
Yoshida discloses that a heat source (5 and 6) and a p-type region (4) and an n-type region (3) are aligned in the same plane wherein the plane is defined by the front side of the substrate(2) and wherein the heat source is between and adjacent to the p-type and n-type region in the same plane and thermally connected to the doped regions and also electrically isolated ([0011]).
Yoshida further discloses that having circuit heat sources arranged in this manner relative to the Peltier elements helps with reducing the size of the package of the semiconductor device and miniaturizing the electronic circuit.
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the position of any of the heat sources of Griebenow so that the heat sources and the p-type region and n-type region are aligned in the same plane wherein the plane is defined by the front side of the substrate and wherein any of the heat sources are between the p-type and n-type regions as disclosed by Yoshida because Griebenow discloses heat sources can be rearranged and Yoshida discloses that the heat sources can be in the same substrate where the thermoelectric regions are formed and this helps with reducing the size of the package of the semiconductor device and miniaturizing the electronic circuit.
Griebenow discloses a first via (see via 135C formation in Fig. 1k) electrically coupled to the p-type region (128B) and the wire (135) and extending between the p-type region and the wire in a direction perpendicular to the plane;
a second via electrically (see vias noted by dashed lines formed over 130 A and resulting structure in Fig. 1l) coupled to the n-type region and the wire and extending between the n-type region and the wire in the direction.
Griebenow discloses a first power rail (see any one of 155 in Fig. 1p) on a back side of the substrate and comprising a first surface parallel to the plane and a second power rail (see any one of 155, in Fig. 1p) on the back side of the substrate and comprising a second surface parallel to the plane and an energy device (see Fig. 1q, 110 [0056]) coupled to each of the first and second power rail structures.
However, Griebenow does not disclose that the first and second power rails are directly connected to p and n-type thermoelectric structures with third and fourth conductive via structures.
Mandal discloses that the first and second electrical connections are via structures (see 24 and 16 and/or 54 and 56 [0028]) to backside connection structures (see railing portions which can be wirings or portions of wirings in substrate 26 which are parallel to thermoelectric elements (42 and 40)).
It would have been obvious to one of ordinary skill in the art at the time of filing to replace the contact structures between the p-type and n-type regions and the first and second power rails with the conductive via structures as disclosed by Mandal because Griebenow discloses that such connections are commonly used and Mandal discloses it is an appropriate electrical connector between p-type and n-type regions and power rails.
In addition, Griebenow discloses a heat sink can be added to the stacked configuration to remove additional heat ([0026]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the substrate (151) of Griebenow by adding an external heat sink as disclosed by Griebenow because Griebenow discloses it is appropriate to do so and it will remove additional heat.
Regarding claims 12, 22, and 24, modified Griebenow discloses all of the claim limitations as set forth above.
In addition, Griebenow discloses an array of thermoelectric structures wherein the energy source (see Fig. 1q, 110) coupled to the first power structure (modification above will have a power structures on back side of substrate to be coupled to external wirings) of the array of thermoelectric structures and the second power structure of a second thermoelectric of the array of thermoelectric structures (see Fig. 1q).
Claim(s) 11 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Griebenow (US 2011/0291269 A1) in view of Yoshida (JP03064050A, Machine Translation) in view of Mandal (US 2017/0324015 A1) as applied to claims 1, 2, 7, 10, 12, 13, 15, 21, 22, and 24 above and in further view of Smythe (US 2012/0174956 A1).
Regarding claims 11 and 23, modified Griebenow discloses all of the claim limitations as set forth above.
Griebenow discloses that the array of thermoelectric structures contain multiple rows of thermoelectric structures ([0029]).
Smythe discloses multiple rows of thermoelectric structure wherein the structures can form subcircuits and subcircuits can be interconnected in series/parallel combination to achieve optimal efficiency and be connected to a single power source (see [0091] and Fig. 5 [0044][0045]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the circuit of modified Griebenow by including multiple rows of thermoelectric structures in parallel as disclosed by Smythe and by having the energy device connected to the rows because Smythe discloses it is possible to do so to achieve optimal cooling.
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Griebenow (US 2011/0291269 A1) in view of Yoshida (JP03064050A, Machine Translation) in view of Mandal (US 2017/0324015 A1) as applied to claims 1, 2, 7, 10, 12, 13, 15, 21, 22, and 24 above and in further view of Letz (US 20100079959 A1).
Regarding claim 25, modified Griebenow discloses all of the claim limitations as set forth above.
Letz discloses a power rail structure (see 250) connected with a contact element (211) embedded in a substrate to a thermoelectric device (251 [0031]) and further discloses that the power rail structure can be connected to wire bond pads ([0030]) to allow for connections.
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the connection between power rail and wiring of Griebenow and further to include wiring bonding pads on the back side of the substrate between the wiring and the power rail structure as disclosed by Letz because Letz discloses that it is known in the art to connect a power rail connected to a thermoelectric element to a wiring structure through a wiring pad.
Response to Arguments
Applicant argues that Griebenow’s elements 142 do not reasonably correspond to the power rails as recited in the claims connected to p and n-type elements through conductive vias.
Griebenow discloses power rail structures as shown in Fig. 1p as elements 155 and are connected to p and n-type elements through the contact structure 141. A modification was done with Mandal as disclosed in the above rejection to modify the contact structure between the p and n-type thermoelectric elements to the power rail structures of Griebenow by using conductive via structures as taught by Mandal.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVINA PILLAY whose telephone number is (571)270-1180. The examiner can normally be reached Monday-Friday 9:30-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey T Barton can be reached at 517-272-1307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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DEVINA PILLAY
Primary Examiner
Art Unit 1726
/DEVINA PILLAY/ Primary Examiner, Art Unit 1726
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