Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/4/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over You (US 20220013410 A1) in view of Subramanian (US 20190305111 A1).
Regarding claim 1, You discloses an integrated circuit structure (Fig. 28A), comprising:
a first gate electrode (2006, See annotated figure) over (vertically over, See annotated figure for direction designation) a first semiconductor fin (corresponding 202´);
a second gate electrode (2006, See annotated figure) over (vertically over) a second semiconductor fin (corresponding 202´);
a first gate endcap isolation structure (1004, See annotated figure) between (horizontally between, See annotated figure for direction designation) the first gate electrode and the second gate electrode, the first gate endcap isolation structure having a higher-k dielectric cap layer (1002, as shown in Fig. 10; [0031]: “the dielectric material 1002 is a high-k dielectric”) on a lower-k dielectric wall (802; [0029]: “dielectric fins…an oxide layer”);
a local conductive interconnect (2602/2604) directly on the first gate electrode (directly vertically on), directly on (directly vertically on) an uppermost surface of the higher-k dielectric cap layer (See annotated figure for up direction designation), and directly on the second gate electrode (directly vertically on), the local conductive interconnect having a bottommost surface (See annotated figure for bottom direction designation) above and in direct physical contact with the uppermost surface of the higher-k dielectric cap layer (direct vertical contact is shown), and the local conductive interconnect continuous (horizontally continuous) from the first gate electrode, across the uppermost surface of the higher-k dielectric cap layer, and to the second gate electrode;
a second gate endcap isolation structure (1004, See annotated figure) adjacent to a side of the first gate electrode opposite (horizontally opposite) the first gate endcap isolation structure, the second gate endcap isolation structure having an uppermost surface (See annotated figure for up direction designation) below the bottommost surface of the local conductive interconnect (vertically below, See annotated figure for below/bottom direction designation), wherein the uppermost surface of the second gate endcap isolation structure is at a same level (same vertical level) as the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure (these surfaces are illustrated coplanar); and
a third gate endcap isolation structure (1004, See annotated figure) adjacent (horizontally adjacent) to a side of the second gate electrode opposite (horizontally opposite) the first gate endcap isolation structure, the third gate endcap isolation structure having an uppermost surface (See annotated figure for up direction designation) below the bottommost surface of the local conductive interconnect (vertically below, See annotated figure for below/bottom direction designation), wherein the uppermost surface of the third gate endcap isolation structure is at a same level (same vertical level) as the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure (these surfaces are illustrated coplanar).
Illustrated below is a marked and annotated figure of Fig. 28A of You.
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You fails to teach the material of the dielectric wall. Thus, You fails to teach “the first gate endcap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall”.
Subramanian discloses the first gate endcap isolation structure (Fig. 11B) having a higher-k dielectric cap layer (1130; [0097]: “hafnium oxide”) on a lower-k dielectric wall (1156; [0098]: “silicon oxide”). Modifying the material of the dielectric wall of You, by selecting the lower-k dielectric wall material from the finite selection of known suitable wall materials disclosed by Subramanian, would arrive at the claimed wall configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the wall includes an oxide functioning as a dielectric (You: [0029}: “dielectric fins…an oxide layer 802”; Subramanian: [0098]: “gate endcap isolation structure…dielectric layer 1156”). Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different for the dielectric wall. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP 2143 (1)(E).
Regarding claim 2, You in view of Subramanian discloses the integrated circuit structure of claim 1 (You: Fig. 28A), wherein the first gate electrode and the second gate electrode each have an uppermost surface co-planar (vertically coplanar is shown) with the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure.
Regarding claim 3, You in view of Subramanian discloses the integrated circuit structure of claim 1 (You: Fig. 28A), wherein the local conductive interconnect electrically connects the first gate electrode and the second gate electrode (direct electrical connection is shown).
Regarding claim 4, You in view of Subramanian discloses the integrated circuit structure of claim 1 (Subramanian: Fig. 11B), wherein the first gate endcap isolation structure comprises a vertical seam (1158) centered within the lower-k dielectric wall.
Regarding independent claim 5, You discloses an integrated circuit structure (Fig. 28A), comprising:
a first trench contact (2006, See annotated figure) over (vertically over, See annotated figure for direction designation) a first epitaxial structure (208; [0020]: “epitaxial layers…may include a plurality of channel layers 208”) over a first semiconductor fin (corresponding 202´);
a second trench contact (2006, See annotated figure) over (vertically over) a second epitaxial structure (208; [0020]: “epitaxial layers…may include a plurality of channel layers 208”) over (vertically over) a second semiconductor fin (corresponding 202´);
a first gate endcap isolation structure (1004, See annotated figure) between (horizontally between, See annotated figure for direction designation) the first trench contact and the second trench contact, the first gate endcap isolation structure having a higher-k dielectric cap layer (1002, as shown in Fig. 10; [0031]: “the dielectric material 1002 is a high-k dielectric”) on a lower-k dielectric wall (802; [0029]: “dielectric fins…an oxide layer”);
a local conductive interconnect (2602/2604) directly on the first trench contact (directly vertically on), directly on (directly vertically on) an uppermost surface of the higher-k dielectric cap layer (See annotated figure for up direction designation), and directly on the second trench contact (directly vertically on), the local conductive interconnect having a bottommost surface (See annotated figure for bottom direction designation) above and in direct physical contact with the uppermost surface of the higher-k dielectric cap layer (direct vertical contact is shown), and the local conductive interconnect continuous (horizontally continuous) from the first trench contact, across the uppermost surface of the higher-k dielectric cap layer, and to the second trench contact;
a second gate endcap isolation structure (1004, See annotated figure) adjacent to a side of the first trench contact opposite the first gate endcap isolation structure (horizontally opposite), the second gate endcap isolation structure having an uppermost surface (See annotated figure for up direction designation) below the bottommost surface of the local conductive interconnect (vertically below, See annotated figure for below/bottom direction designation), wherein the uppermost surface of the second gate endcap isolation structure is at a same level (same vertical level) as the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure (these surfaces are illustrated coplanar); and
a third gate endcap isolation structure (1004, See annotated figure) adjacent (horizontally adjacent) to a side of the second trench contact opposite (horizontally opposite) the first gate endcap isolation structure, the third gate endcap isolation structure having an uppermost surface (See annotated figure for up direction designation) below the bottommost surface of the local conductive interconnect (vertically below, See annotated figure for below/bottom direction designation), wherein the uppermost surface of the third gate endcap isolation structure is at a same level (same vertical level) as the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure (these surfaces are illustrated coplanar).
You fails to teach the material of the dielectric wall. Thus, You fails to teach “the first gate endcap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall”.
Subramanian discloses the first gate endcap isolation structure (Fig. 11B) having a higher-k dielectric cap layer (1130; [0097]: “hafnium oxide”) on a lower-k dielectric wall (1156; [0098]: “silicon oxide”). Modifying the material of the dielectric wall of You, by selecting the lower-k dielectric wall material from the finite selection of known suitable wall materials disclosed by Subramanian, would arrive at the claimed wall configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the wall includes an oxide functioning as a dielectric (You: [0029}: “dielectric fins…an oxide layer 802”; Subramanian: [0098]: “gate endcap isolation structure…dielectric layer 1156”). Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different for the dielectric wall. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP 2143 (1)(E).
Regarding claim 6, You in view of Subramanian discloses the integrated circuit structure of claim 5 (You: Fig. 28A), wherein the first trench contact and the second trench contact each have an uppermost surface co-planar (vertically coplanar is shown) with the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure.
Regarding claim 7, You in view of Subramanian discloses the integrated circuit structure of claim 5 (You: Fig. 28A), wherein the local conductive interconnect electrically connects the first trench contact and the second trench contact (direct electrical connection is shown).
Regarding claim 8, You in view of Subramanian discloses the integrated circuit structure of claim 5 (Subramanian: Fig. 11B), wherein the first gate endcap isolation structure comprises a vertical seam (1158) centered within the lower-k dielectric wall.
Regarding independent claim 9, You discloses a computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure (Fig. 28A), comprising:
a first gate electrode (2006, See annotated figure) over (vertically over, See annotated figure for direction designation) a first semiconductor fin (corresponding 202´);
a second gate electrode (2006, See annotated figure) over (vertically over) a second semiconductor fin (corresponding 202´);
a first gate endcap isolation structure (1004, See annotated figure) between (horizontally between, See annotated figure for direction designation) the first gate electrode and the second gate electrode, the first gate endcap isolation structure having a higher-k dielectric cap layer (1002, as shown in Fig. 10; [0031]: “the dielectric material 1002 is a high-k dielectric”) on a lower-k dielectric wall (802; [0029]: “dielectric fins…an oxide layer”);
a local conductive interconnect (2602/2604) directly on the first gate electrode (directly vertically on), directly on (directly vertically on) an uppermost surface of the higher-k dielectric cap layer (See annotated figure for up direction designation), and directly on the second gate electrode (directly vertically on), the local conductive interconnect having a bottommost surface (See annotated figure for bottom direction designation) above and in direct physical contact with the uppermost surface of the higher-k dielectric cap layer (direct vertical contact is shown), and the local conductive interconnect continuous (horizontally continuous) from the first gate electrode, across the uppermost surface of the higher-k dielectric cap layer, and to the second gate electrode;
a second gate endcap isolation structure (1004, See annotated figure) adjacent to a side of the first gate electrode opposite (horizontally opposite) the first gate endcap isolation structure, the second gate endcap isolation structure having an uppermost surface (See annotated figure for up direction designation) below the bottommost surface of the local conductive interconnect (vertically below, See annotated figure for below/bottom direction designation), wherein the uppermost surface of the second gate endcap isolation structure is at a same level (same vertical level) as the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure (these surfaces are illustrated coplanar); and
a third gate endcap isolation structure (1004, See annotated figure) adjacent (horizontally adjacent) to a side of the second gate electrode opposite (horizontally opposite) the first gate endcap isolation structure, the third gate endcap isolation structure having an uppermost surface (See annotated figure for up direction designation) below the bottommost surface of the local conductive interconnect (vertically below, See annotated figure for below/bottom direction designation), wherein the uppermost surface of the third gate endcap isolation structure is at a same level (same vertical level) as the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure (these surfaces are illustrated coplanar).
You fails to teach the material of the dielectric wall. Thus, You fails to teach “the first gate endcap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall”.
Subramanian discloses the first gate endcap isolation structure (Fig. 11B) having a higher-k dielectric cap layer (1130; [0097]: “hafnium oxide”) on a lower-k dielectric wall (1156; [0098]: “silicon oxide”). Modifying the material of the dielectric wall of You, by selecting the lower-k dielectric wall material from the finite selection of known suitable wall materials disclosed by Subramanian, would arrive at the claimed wall configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the wall includes an oxide functioning as a dielectric (You: [0029}: “dielectric fins…an oxide layer 802”; Subramanian: [0098]: “gate endcap isolation structure…dielectric layer 1156”). Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different for the dielectric wall. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP 2143 (1)(E).
You in view of Subramanian teaches the integrated circuit structure, but fails to teach it included with “A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure”.
Subramanian teaches a computing device (Fig. 12), comprising: a board (1200); and a component coupled to the board (1204; [0106]: “processor”), the component including an integrated circuit structure ([0105]: “Embodiments disclosed herein may be used to manufacture…processors”; selecting the embodiment of Fig. 11B). Modifying the integrated circuit of You by including it in the computing device of Subramanian would arrive at the claimed computing device configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the integrated circuit includes gate electrodes over fins (You: Fig. 28A: gates 2006 over fins 202´; Subramanian: Fig. 10A: gates 1008 over fins 1005) and gate endcap isolation structures (You: Fig. 28A: endcaps 1004; Subramanian: Fig. 11B: endcaps 1150). You provides a teaching to incorporate the integrated circuit in that it would enable producing a compact device ([0016]: “allows for reduction of dimensions and such as metal gate dimensions, thereby increasing pattern density”), while also enhancing operational characteristics of the resultant device ([0015]: “improved AC performance of the device”). Therefore, it would have been obvious to have the claimed integrated circuit configuration because it would enable producing a compact device having enhanced operational characteristics. MPEP 2143 (I)(G).
Regarding claim 10, You in view of Subramanian discloses the computing device of claim 9 (Subramanian: Fig. 12), further comprising: a memory (DRAM; [0107]: “volatile memory”) coupled to the board.
Regarding claim 11, You in view of Subramanian discloses the computing device of claim 9 (Subramanian: Fig. 12), further comprising: a communication chip (1206) coupled to the board.
Regarding claim 12, You in view of Subramanian discloses the computing device of claim 9 (Subramanian: Fig. 12), further comprising: a camera (CAMERA) coupled to the board.
Regarding claim 13, You in view of Subramanian discloses the computing device of claim 9 (Subramanian: Fig. 12), wherein the component is a packaged integrated circuit die ([0109]: “an integrated circuit die packaged within the processor”).
Regarding claim 14, You in view of Subramanian discloses the computing device of claim 9 (Subramanian: Fig. 12), wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box ([0112]: “laptop”).
Regarding independent claim 15, You discloses a computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure (Fig. 28A), comprising:
a first trench contact (2006, See annotated figure) over (vertically over, See annotated figure for direction designation) a first epitaxial structure (208; [0020]: “epitaxial layers…may include a plurality of channel layers 208”) over a first semiconductor fin (corresponding 202´);
a second trench contact (2006, See annotated figure) over (vertically over) a second epitaxial structure (208; [0020]: “epitaxial layers…may include a plurality of channel layers 208”) over (vertically over) a second semiconductor fin (corresponding 202´);
a first gate endcap isolation structure (1004, See annotated figure) between (horizontally between, See annotated figure for direction designation) the first trench contact and the second trench contact, the first gate endcap isolation structure having a higher-k dielectric cap layer (1002, as shown in Fig. 10; [0031]: “the dielectric material 1002 is a high-k dielectric”) on a lower-k dielectric wall (802; [0029]: “dielectric fins…an oxide layer”);
a local conductive interconnect (2602/2604) directly on the first trench contact (directly vertically on), directly on (directly vertically on) an uppermost surface of the higher-k dielectric cap layer (See annotated figure for up direction designation), and directly on the second trench contact (directly vertically on), the local conductive interconnect having a bottommost surface (See annotated figure for bottom direction designation) above and in direct physical contact with the uppermost surface of the higher-k dielectric cap layer (direct vertical contact is shown), and the local conductive interconnect continuous (horizontally continuous) from the first trench contact, across the uppermost surface of the higher-k dielectric cap layer, and to the second trench contact;
a second gate endcap isolation structure (1004, See annotated figure) adjacent to a side of the first trench contact opposite the first gate endcap isolation structure (horizontally opposite), the second gate endcap isolation structure having an uppermost surface (See annotated figure for up direction designation) below the bottommost surface of the local conductive interconnect (vertically below, See annotated figure for below/bottom direction designation), wherein the uppermost surface of the second gate endcap isolation structure is at a same level (same vertical level) as the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure (these surfaces are illustrated coplanar); and
a third gate endcap isolation structure (1004, See annotated figure) adjacent (horizontally adjacent) to a side of the second trench contact opposite (horizontally opposite) the first gate endcap isolation structure, the third gate endcap isolation structure having an uppermost surface (See annotated figure for up direction designation) below the bottommost surface of the local conductive interconnect (vertically below, See annotated figure for below/bottom direction designation), wherein the uppermost surface of the third gate endcap isolation structure is at a same level (same vertical level) as the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure (these surfaces are illustrated coplanar).
You fails to teach the material of the dielectric wall. Thus, You fails to teach “the first gate endcap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall”.
Subramanian discloses the first gate endcap isolation structure (Fig. 11B) having a higher-k dielectric cap layer (1130; [0097]: “hafnium oxide”) on a lower-k dielectric wall (1156; [0098]: “silicon oxide”). Modifying the material of the dielectric wall of You, by selecting the lower-k dielectric wall material from the finite selection of known suitable wall materials disclosed by Subramanian, would arrive at the claimed wall configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the wall includes an oxide functioning as a dielectric (You: [0029}: “dielectric fins…an oxide layer 802”; Subramanian: [0098]: “gate endcap isolation structure…dielectric layer 1156”). Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different for the dielectric wall. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP 2143 (1)(E).
You in view of Subramanian teaches the integrated circuit structure, but fails to teach it included with “A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure”.
Subramanian teaches a computing device (Fig. 12), comprising: a board (1200); and a component coupled to the board (1204; [0106]: “processor”), the component including an integrated circuit structure ([0105]: “Embodiments disclosed herein may be used to manufacture…processors”; selecting the embodiment of Fig. 11B). Modifying the integrated circuit of You by including it in the computing device of Subramanian would arrive at the claimed computing device configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the integrated circuit includes gate electrodes over fins (You: Fig. 28A: gates 2006 over fins 202´; Subramanian: Fig. 10A: gates 1008 over fins 1005) and gate endcap isolation structures (You: Fig. 28A: endcaps 1004; Subramanian: Fig. 11B: endcaps 1150). You provides a teaching to incorporate the integrated circuit in that it would enable producing a compact device ([0016]: “allows for reduction of dimensions and such as metal gate dimensions, thereby increasing pattern density”), while also enhancing operational characteristics of the resultant device ([0015]: “improved AC performance of the device”). Therefore, it would have been obvious to have the claimed integrated circuit configuration because it would enable producing a compact device having enhanced operational characteristics. MPEP 2143 (I)(G).
Regarding claim 16, You in view of Subramanian discloses the computing device of claim 15 (Subramanian: Fig. 12), further comprising: a memory (DRAM; [0107]: “volatile memory”) coupled to the board.
Regarding claim 17, You in view of Subramanian discloses the computing device of claim 15 (Subramanian: Fig. 12), further comprising: a communication chip (1206) coupled to the board.
Regarding claim 18, You in view of Subramanian discloses the computing device of claim 15 (Subramanian: Fig. 12), further comprising: a camera (CAMERA) coupled to the board.
Regarding claim 19, You in view of Subramanian discloses the computing device of claim 15 (Subramanian: Fig. 12), wherein the component is a packaged integrated circuit die ([0109]: “an integrated circuit die packaged within the processor”).
Regarding claim 20, You in view of Subramanian discloses the computing device of claim 15 (Subramanian: Fig. 12), wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box ([0112]: “laptop”).
Response to Arguments
Applicant's arguments filed 3/4/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended independent claims 1, 5, 9, and 15 that “Subramanian does not disclose an integrated circuit structure including…as is required by Applicant's claims”. Remarks at pg. 13.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 1, 5, 9, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Combinations of You and Subramanian are relied upon in the instant Office action to render obvious the contended combination of limitations.
Conclusion
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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