Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cho (US 20220020859 A1).
Regarding claim 1, Cho discloses an integrated circuit structure (Fig. 11), comprising:
a first gate electrode (GE1) over (“over” in the D3 direction) a first semiconductor fin (1st Fin, See annotated figure);
a first trench isolation structure (1st ST, See annotated figure) adjacent (“adjacent” in the D1 direction) to a lower portion of the first semiconductor fin;
a second gate electrode (GE2) over (“over” in the D3 direction) a second semiconductor fin (2nd Fin, See annotated figure);
a second trench isolation structure (2nd ST, See annotated figure) adjacent (“adjacent” in the D1 direction) to a lower portion of the second semiconductor fin;
a first gate endcap isolation structure (TC1) between (“between” in the D1 direction) the first gate electrode and the second gate electrode,
the first gate endcap isolation structure having a higher-k dielectric cap layer (UC; [0062]: “SiN”. Note: SiN is well known to have a dielectric constant higher than the below cited SiO2) on (“on” in the D3 direction) a lower-k dielectric wall (LC; [0062]: “SiO2”. Note: SiO2 is well known to have a dielectric constant lower than the above cited SiN), and
the first gate endcap isolation structure having a bottom surface (TC1-b, See annotated figure) below (“below” in the D3 direction) a top of the first trench isolation structure (1st ST-t, See annotated figure) and below (“below” in the D3 direction, See dashed reference line) a top surface of the second trench isolation structure (2nd ST-t, See annotated figure);
a local conductive interconnect (GC) directly on (“on” in the D3 direction) the first gate electrode, directly on (“on” in the D3 direction) an uppermost surface of the higher-k dielectric cap layer (TC1-u, See annotated figure), and directly on (“on” in the D3 direction) the second gate electrode,
the local conductive interconnect having a bottommost surface (GC-b, See annotated figure) above (“above” in the D3 direction) and in direct physical contact with the uppermost surface of the higher-k dielectric cap layer (“direct contact” is illustrated), and the local conductive interconnect continuous (electrically and physically “continuous”) from the first gate electrode, across the uppermost surface of the higher- k dielectric cap layer, and to the second gate electrode (“from…across…and to” in the D1 direction);
a second gate endcap isolation structure (TC2 on left) adjacent (“adjacent” D1 direction) to a side of the first gate electrode (left side) opposite the first gate endcap isolation structure (TC1 is on the opposite/right side of GE1),
the second gate endcap isolation structure having an uppermost surface (TC2-u) below (“below” in the D3 direction, See dashed reference line) the bottommost surface of the local conductive interconnect, wherein the uppermost surface of the second gate endcap isolation structure is at a same level (See dashed reference line) as the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure; and
a third gate endcap isolation structure (TC2 on right) adjacent (“adjacent” D1 direction) to a side of the second gate electrode (right side) opposite the first gate endcap isolation structure (TC1 is on the opposite/left side of GE2),
the third gate endcap isolation structure having an uppermost surface (TC2-u) below (“below” in the D3 direction, See dashed reference line) the bottommost surface of the local conductive interconnect, wherein the uppermost surface of the third gate endcap isolation structure is at a same level (See dashed reference line) as the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure.
Illustrated below is a marked and annotated figure of Fig. 11 of Cho.
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Regarding claim 2, Cho discloses the integrated circuit structure of claim 1 (Fig. 11), wherein the first gate electrode and the second gate electrode each have an uppermost surface co-planar (“co-planar” at the dashed reference line) with the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure.
Regarding claim 3, Cho discloses the integrated circuit structure of claim 1 (Fig. 11), wherein the local conductive interconnect electrically connects the first gate electrode and the second gate electrode ([0037]: “electrically connected”).
Regarding independent claim 5, Cho discloses an integrated circuit structure, comprising:
a first trench contact (GE1 is a conductive terminal at least partially in a trench, thus “a trench contact”) over (at least indirectly “over” in at least some direction) a first epitaxial structure ([0029]: “epitaxial patterns”) over (at least indirectly “over” in at least some direction) a first semiconductor fin (1st Fin, See annotated figure);
a first trench isolation structure (1st ST, See annotated figure) adjacent (“adjacent” in the D1 direction) to a lower portion of the first semiconductor fin;
a second trench contact (GE2 is a conductive terminal at least partially in a trench, thus “a trench contact”) over (at least indirectly “over” in at least some direction) a second epitaxial structure ([0029]: “epitaxial patterns”) over (at least indirectly “over” in at least some direction) a second semiconductor fin (2nd Fin, See annotated figure);
a second trench isolation structure (2nd ST, See annotated figure) adjacent (“adjacent” in the D1 direction) to a lower portion of the second semiconductor fin;
a first gate endcap isolation structure (TC1) between (“between” in the D1 direction) the first trench contact and the second trench contact,
the first gate endcap isolation structure having a higher-k dielectric cap layer (UC; [0062]: “SiN”. Note: SiN is well known to have a dielectric constant higher than the below cited SiO2) on (“on” in the D3 direction) a lower-k dielectric wall (LC; [0062]: “SiO2”. Note: SiO2 is well known to have a dielectric constant lower than the above cited SiN), and
the first gate endcap isolation structure having a bottom surface (TC1-b, See annotated figure) below (“below” in the D3 direction) a top of the first trench isolation structure (1st ST-t, See annotated figure) and below (“below” in the D3 direction, See dashed reference line) a top surface of the second trench isolation structure (2nd ST-t, See annotated figure);
a local conductive interconnect (GC) directly on the first trench contact, directly on an uppermost surface of the higher-k dielectric cap layer, and directly on the second trench contact,
the local conductive interconnect having a bottommost surface (GC-b, See annotated figure) above (“above” in the D3 direction) and in direct physical contact with the uppermost surface of the higher-k dielectric cap layer (“direct contact” is illustrated), and the local conductive interconnect continuous (electrically and physically “continuous”) from the first trench contact, across the uppermost surface of the higher- k dielectric cap layer, and to the second trench contact (“from…across…and to” in the D1 direction);
a second gate endcap isolation structure (TC2 on left) adjacent (“adjacent” D1 direction) to a side of the first trench contact (left side) opposite the first gate endcap isolation structure (TC1 is on the opposite/right side of GE1),
the second gate endcap isolation structure having an uppermost surface (TC2-u) below (“below” in the D3 direction, See dashed reference line) the bottommost surface of the local conductive interconnect, wherein the uppermost surface of the second gate endcap isolation structure is at a same level (See dashed reference line) as the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure; and
a third gate endcap isolation structure (TC2 on right) adjacent (“adjacent” D1 direction) to a side of the second trench contact (right side) opposite the first gate endcap isolation structure (TC1 is on the opposite/left side of GE2),
the third gate endcap isolation structure having an uppermost surface (TC2-u) below (“below” in the D3 direction, See dashed reference line) the bottommost surface of the local conductive interconnect, wherein the uppermost surface of the third gate endcap isolation structure is at a same level (See dashed reference line) as the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure.
Regarding claim 6, Cho discloses the integrated circuit structure of claim 5 (Fig. 11), wherein the first trench contact and the second trench contact each have an uppermost surface co-planar (“co-planar” at the dashed reference line) with the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure.
Regarding claim 7, Cho discloses the integrated circuit structure of claim 5 (Fig. 11), wherein the local conductive interconnect electrically connects the first trench contact and the second trench contact ([0037]: “electrically connected”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Cho as applied to claim 1 above, and further in view of Ko (US 20210343597 A1).
Regarding claim 4, Cho teaches the lower-k dielectric wall, but fails to teach particular methods of forming the wall, or any resultant features produced during formation. Thus, Cho fails to teach “wherein the first gate endcap isolation structure comprises a vertical seam centered within the lower-k dielectric wall”.
Ko teaches wherein the first gate endcap isolation structure (Fig. 22) comprises a vertical seam (62) centered within the lower-k dielectric wall (58; [0032]: “SiO2”). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success including a vertical seam because it is a resultant feature produced when forming the lower-k dielectric wall (Ko: [0048]: “Seam 62 may be, or may not be formed in dielectric layer 58”) of the same material (Cho: [0062]: “SiO2”; Ko: [0032]: “SiO2”). Therefore, the claimed seam configuration would have been obvious to one of ordinary skill in the art before the effective filing date because it is a known resultant feature produced when forming a similar lower-k dielectric wall. MPEP 2143 (I)(C).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Cho as applied to claim 5 above, and further in view of Ko.
Regarding claim 4, Cho teaches the lower-k dielectric wall, but fails to teach particular methods of forming the wall, or any resultant features produced during formation. Thus, Cho fails to teach “wherein the first gate endcap isolation structure comprises a vertical seam centered within the lower-k dielectric wall”.
Ko teaches wherein the first gate endcap isolation structure (Fig. 22) comprises a vertical seam (62) centered within the lower-k dielectric wall (58; [0032]: “SiO2”). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success including a vertical seam because it is a resultant feature produced when forming the lower-k dielectric wall (Ko: [0048]: “Seam 62 may be, or may not be formed in dielectric layer 58”) of the same material (Cho: [0062]: “SiO2”; Ko: [0032]: “SiO2”). Therefore, the claimed seam configuration would have been obvious to one of ordinary skill in the art before the effective filing date because it is a known resultant feature produced when forming a similar lower-k dielectric wall. MPEP 2143 (I)(C).
Claims 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Subramanian (US 20190305111 A1).
Regarding independent claim 9, Cho discloses a computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure (Fig. 11), comprising:
a first gate electrode (GE1) over (“over” in the D3 direction) a first semiconductor fin (1st Fin, See annotated figure);
a first trench isolation structure (1st ST, See annotated figure) adjacent (“adjacent” in the D1 direction) to a lower portion of the first semiconductor fin;
a second gate electrode (GE2) over (“over” in the D3 direction) a second semiconductor fin (2nd Fin, See annotated figure);
a second trench isolation structure (2nd ST, See annotated figure) adjacent (“adjacent” in the D1 direction) to a lower portion of the second semiconductor fin;
a first gate endcap isolation structure (TC1) between (“between” in the D1 direction) the first gate electrode and the second gate electrode,
the first gate endcap isolation structure having a higher-k dielectric cap layer (UC; [0062]: “SiN”. Note: SiN is well known to have a dielectric constant higher than the below cited SiO2) on (“on” in the D3 direction) a lower-k dielectric wall (LC; [0062]: “SiO2”. Note: SiO2 is well known to have a dielectric constant lower than the above cited SiN), and
the first gate endcap isolation structure having a bottom surface (TC1-b, See annotated figure) below (“below” in the D3 direction) a top of the first trench isolation structure (1st ST-t, See annotated figure) and below (“below” in the D3 direction, See dashed reference line) a top surface of the second trench isolation structure (2nd ST-t, See annotated figure);
a local conductive interconnect (GC) directly on (“on” in the D3 direction) the first gate electrode, directly on (“on” in the D3 direction) an uppermost surface of the higher-k dielectric cap layer (TC1-u, See annotated figure), and directly on (“on” in the D3 direction) the second gate electrode,
the local conductive interconnect having a bottommost surface (GC-b, See annotated figure) above (“above” in the D3 direction) and in direct physical contact with the uppermost surface of the higher-k dielectric cap layer (“direct contact” is illustrated), and the local conductive interconnect continuous (electrically and physically “continuous”) from the first gate electrode, across the uppermost surface of the higher- k dielectric cap layer, and to the second gate electrode (“from…across…and to” in the D1 direction);
a second gate endcap isolation structure (TC2 on left) adjacent (“adjacent” D1 direction) to a side of the first gate electrode (left side) opposite the first gate endcap isolation structure (TC1 is on the opposite/right side of GE1),
the second gate endcap isolation structure having an uppermost surface (TC2-u) below (“below” in the D3 direction, See dashed reference line) the bottommost surface of the local conductive interconnect, wherein the uppermost surface of the second gate endcap isolation structure is at a same level (See dashed reference line) as the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure; and
a third gate endcap isolation structure (TC2 on right) adjacent (“adjacent” D1 direction) to a side of the second gate electrode (right side) opposite the first gate endcap isolation structure (TC1 is on the opposite/left side of GE2),
the third gate endcap isolation structure having an uppermost surface (TC2-u) below (“below” in the D3 direction, See dashed reference line) the bottommost surface of the local conductive interconnect, wherein the uppermost surface of the third gate endcap isolation structure is at a same level (See dashed reference line) as the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure.
Cho teaches the integrated circuit structure, but fails to teach it included with “A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure”.
Subramanian teaches a computing device (Fig. 12), comprising: a board (1200); and a component coupled to the board (1204; [0106]: “processor”), the component including an integrated circuit structure ([0105]: “Embodiments disclosed herein may be used to manufacture…processors”; selecting the embodiment of Fig. 11B). Modifying the integrated circuit of Cho by including it in the computing device of Subramanian would arrive at the claimed computing device configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the integrated circuit includes gate electrodes over fins (Cho: Fig. 11: gates GE over the annotated fins; Subramanian: Fig. 10A: gates 1008 over fins 1005) and gate endcap isolation structures (Cho: Fig. 11: endcaps TC1/TC2; Subramanian: Fig. 11B: endcaps 1150). Cho provides a teaching to incorporate the integrated circuit in that it would enable producing a compact device ([0004]: “increased integration density”), while also enhancing operational characteristics of the resultant device ([0004]: “improved reliability”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed integrated circuit configuration because it would enable producing a compact device having enhanced operational characteristics. MPEP 2143 (I)(G).
Regarding claim 10, Cho in view of Subramanian discloses the computing device of claim 9 (Subramanian: Fig. 12), further comprising: a memory (DRAM; [0107]: “volatile memory”) coupled to the board.
Regarding claim 11, Cho in view of Subramanian discloses the computing device of claim 9 (Subramanian: Fig. 12), further comprising: a communication chip (1206) coupled to the board.
Regarding claim 12, Cho in view of Subramanian discloses the computing device of claim 9 (Subramanian: Fig. 12), further comprising: a camera (CAMERA) coupled to the board.
Regarding claim 13, Cho in view of Subramanian discloses the computing device of claim 9 (Subramanian: Fig. 12), wherein the component is a packaged integrated circuit die ([0109]: “an integrated circuit die packaged within the processor”).
Regarding claim 14, Cho in view of Subramanian discloses the computing device of claim 9 (Subramanian: Fig. 12), wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box ([0112]: “laptop”).
Regarding independent claim 15, Cho discloses a computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure (Fig. 11), comprising:
a first trench contact (GE1 is a conductive terminal at least partially in a trench, thus “a trench contact”) over (at least indirectly “over” in at least some direction) a first epitaxial structure ([0029]: “epitaxial patterns”) over (at least indirectly “over” in at least some direction) a first semiconductor fin (1st Fin, See annotated figure);
a first trench isolation structure (1st ST, See annotated figure) adjacent (“adjacent” in the D1 direction) to a lower portion of the first semiconductor fin;
a second trench contact (GE2 is a conductive terminal at least partially in a trench, thus “a trench contact”) over (at least indirectly “over” in at least some direction) a second epitaxial structure ([0029]: “epitaxial patterns”) over (at least indirectly “over” in at least some direction) a second semiconductor fin (2nd Fin, See annotated figure);
a second trench isolation structure (2nd ST, See annotated figure) adjacent (“adjacent” in the D1 direction) to a lower portion of the second semiconductor fin;
a first gate endcap isolation structure (TC1) between (“between” in the D1 direction) the first trench contact and the second trench contact,
the first gate endcap isolation structure having a higher-k dielectric cap layer (UC; [0062]: “SiN”. Note: SiN is well known to have a dielectric constant higher than the below cited SiO2) on (“on” in the D3 direction) a lower-k dielectric wall (LC; [0062]: “SiO2”. Note: SiO2 is well known to have a dielectric constant lower than the above cited SiN), and
the first gate endcap isolation structure having a bottom surface (TC1-b, See annotated figure) below (“below” in the D3 direction) a top of the first trench isolation structure (1st ST-t, See annotated figure) and below (“below” in the D3 direction, See dashed reference line) a top surface of the second trench isolation structure (2nd ST-t, See annotated figure);
a local conductive interconnect (GC) directly on the first trench contact, directly on an uppermost surface of the higher-k dielectric cap layer, and directly on the second trench contact,
the local conductive interconnect having a bottommost surface (GC-b, See annotated figure) above (“above” in the D3 direction) and in direct physical contact with the uppermost surface of the higher-k dielectric cap layer (“direct contact” is illustrated), and the local conductive interconnect continuous (electrically and physically “continuous”) from the first trench contact, across the uppermost surface of the higher- k dielectric cap layer, and to the second trench contact (“from…across…and to” in the D1 direction);
a second gate endcap isolation structure (TC2 on left) adjacent (“adjacent” D1 direction) to a side of the first trench contact (left side) opposite the first gate endcap isolation structure (TC1 is on the opposite/right side of GE1),
the second gate endcap isolation structure having an uppermost surface (TC2-u) below (“below” in the D3 direction, See dashed reference line) the bottommost surface of the local conductive interconnect, wherein the uppermost surface of the second gate endcap isolation structure is at a same level (See dashed reference line) as the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure; and
a third gate endcap isolation structure (TC2 on right) adjacent (“adjacent” D1 direction) to a side of the second trench contact (right side) opposite the first gate endcap isolation structure (TC1 is on the opposite/left side of GE2),
the third gate endcap isolation structure having an uppermost surface (TC2-u) below (“below” in the D3 direction, See dashed reference line) the bottommost surface of the local conductive interconnect, wherein the uppermost surface of the third gate endcap isolation structure is at a same level (See dashed reference line) as the uppermost surface of the higher-k dielectric cap layer of the first gate endcap isolation structure.
Cho teaches the integrated circuit structure, but fails to teach it included with “A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure”.
Subramanian teaches a computing device (Fig. 12), comprising: a board (1200); and a component coupled to the board (1204; [0106]: “processor”), the component including an integrated circuit structure ([0105]: “Embodiments disclosed herein may be used to manufacture…processors”; selecting the embodiment of Fig. 11B). Modifying the integrated circuit of Cho by including it in the computing device of Subramanian would arrive at the claimed computing device configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the integrated circuit includes gate electrodes over fins (Cho: Fig. 11: gates GE over the annotated fins; Subramanian: Fig. 10A: gates 1008 over fins 1005) and gate endcap isolation structures (Cho: Fig. 11: endcaps TC1/TC2; Subramanian: Fig. 11B: endcaps 1150). Cho provides a teaching to incorporate the integrated circuit in that it would enable producing a compact device ([0004]: “increased integration density”), while also enhancing operational characteristics of the resultant device ([0004]: “improved reliability”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed integrated circuit configuration because it would enable producing a compact device having enhanced operational characteristics. MPEP 2143 (I)(G).
Regarding claim 16, Cho in view of Subramanian discloses the computing device of claim 15 (Subramanian: Fig. 12), further comprising: a memory (DRAM; [0107]: “volatile memory”) coupled to the board.
Regarding claim 17, Cho in view of Subramanian discloses the computing device of claim 15 (Subramanian: Fig. 12), further comprising: a communication chip (1206) coupled to the board.
Regarding claim 18, Cho in view of Subramanian discloses the computing device of claim 15 (Subramanian: Fig. 12), further comprising: a camera (CAMERA) coupled to the board.
Regarding claim 19, Cho in view of Subramanian discloses the computing device of claim 15 (Subramanian: Fig. 12), wherein the component is a packaged integrated circuit die ([0109]: “an integrated circuit die packaged within the processor”).
Regarding claim 20, Cho in view of Subramanian discloses the computing device of claim 15 (Subramanian: Fig. 12), wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box ([0112]: “laptop”).
Response to Arguments
Applicant's arguments filed 7/30/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claims 1, 5, 9, and 15 that “You does not disclose an integrated circuit structure including a first semiconductor fin, a first trench isolation structure adjacent to a lower portion of the first semiconductor fin, a second semiconductor fin, a second trench isolation structure adjacent to a lower portion of the second semiconductor fin, and a first gate endcap isolation structure having a bottom surface below a top of the first trench isolation structure and below a top surface of the second trench isolation structure, as is required by Applicant's claims”. Remarks at pg. 13.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 1, 5, 9, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Newly found reference Cho is relied upon in the instant Office action, as necessitated by the claim amendments.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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