DETAILED ACTION
Claims 1-20 are pending.
Claims 1-6 have been elected and examined.
Claims 7-20 are withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 12, 2025, has been entered.
Claim Objections
Claim 1 is objected to because of the following informalities:
In line 8, replace “the each parallel processing unit” with --each parallel processing unit in the first subset-- for improved grammar/readability.
In the last paragraph, line 1, replace “links” with --link--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Referring to claim 1:
Applicant now claims that the third pair of links are configured as a ring(s). This appears to be new matter. Recall that applicant has elected FIG.7. In FIG.7, not every third pair is part of a ring. For instance, link 740, which is part of the third pair, is not part of a ring. To now claim it is constitutes new matter.
Additionally, the claimed links may be part of a ring, but are not configured as a ring per se. Any individual link is simply a link between two processing units and is not a ring. To claim they are configured as rings is also new matter. The examiner recommends rewording as --…are configured to couple the parallel processing units in the given set to form communication rings, such that…--.
Claims 2-6 are rejected due to their dependence in a claim lacking adequate written description.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 1, each instance of “the first subset” since there is a first subset in line 5 and another in line 7. The examiner recommends replacing “in a” with --in the-- in line 7.
In claim 1, last paragraph, “the one communication link…in the second subset”. Applicant only previously established this one link in the first subset.
In claim 1, last paragraph, “the first pair of communication links…in the second subset”. Applicant only previously established this first pair in the first subset.
In claim 1, last paragraph, “the second pair of communication links…in the second subset”. Applicant only previously established this second pair in the first subset.
In claim 1, last paragraph, “the third pair of communication links between the corresponding parallel processing units of the first and seconds subsets”. Which third pair is applicant referring to? For instance, when referencing FIG.7, this third pair could be the pair connecting 310 and 315, or the pair connecting 330 and 335, or the pair connecting 325 and 340, or the pair connecting 305 and 320.
In claim 2, “the third pair of communication links to couple the corresponding parallel processing units in the seconds subset”. Which third pair is applicant referring to? For instance, when referencing FIG.7, this third pair could be the pair connecting 310 and 315, or the pair connecting 330 and 335, or the pair connecting 325 and 340, or the pair connecting 305 and 320. Also, what is the second pair for the second subset?
In claim 3, “the parallel processing units”, because this could refer to those in the one or more sets, the given set, the first subset, or the second subset, or to those in the last line of claim 1. Should --of the given set-- be inserted after “units”” in claim 3, line 4?
Claims 2-6 are rejected due to their dependence on an indefinite claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Liao, U.S. Patent Application Publication No. 2018/0181536 A1, in view of the examiner’s taking of Official Notice.
Referring to claim 1, Liao, under a first interpretation, has taught a compute system comprising:
one or more sets of parallel processing units (see FIG.4, and note the set of CPUs), wherein the parallel processing units in a given set are organized into subsets of parallel processing units (see FIG.4, which shows two subsets, each with four CPUs (the first subset including CPUs 0, 1, 2, and 3; and the second subset including CPUs 4, 5, 6, and 7)),
wherein each parallel processing unit in a first subset of parallel processing units is configurably couplable to a first of two nearest neighbor parallel processing units in a first subset by a first communication link (sees FIG.5B, which builds on FIG.4 by allowing for additional links between CPUs/nodes (paragraph [0106]). CPU0 and CPU1 are coupled as nearest neighbors by a first link and CPU2 and CPU3 are coupled as nearest neighbors by a first link).
While Liao has not taught that the first communication link comprises a pair of links, Official Notice is taken that one link comprising multiple links, one for each bit to be transmitted, was well known in the art before applicant’s invention. That is, for a CPU to transmit 32 bits, for example, it is fastest to send all 32 bits in parallel, which requires 32 1-bit links that make up an overall communication link. As a result, to maximize transfer speed, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Liao such that the aforementioned first nearest neighbor links in FIG.5B are each made up of multiple 1-bit links, thereby realizing nearest neighbor coupling by two (or more) communication links).
Liao has further taught wherein each parallel processing unit is configurably couplable to a second of the two nearest neighbor parallel processing units in the first subset by a second communication link (from FIG.5B, CPU0 and CPU2 are coupled as nearest neighbors by a second link, and CPU1 and CPU3 are coupled as nearest neighbors by a second link).
While Liao has not taught that the second communication link comprises a pair of links, this is an obvious modification for similar reasoning given above.
Liao has further taught wherein each parallel processing unit in the first subset is configurably couplable to a farthest neighbor parallel processing unit in the first subset by one communication link (see FIG.5B. Farthest neighbors CPU0 and CPU3 are coupled, via one link, as farthest neighbors. And, farthest neighbors CPU1 and CPU2 are similarly coupled via one link).
Liao has further taught wherein the each parallel processing unit in the first subset is configurably couplable to a corresponding parallel processing unit in a second subset by a third communication link (see FIG.5B and paragraph [0106]. Each CPU is connected to another node (and the CPUs therein) via third link.
While Liao has not taught that the third communication link comprises a pair of links, this is an obvious modification for similar reasoning given above.
Note, that each node (subset) may have similar couplings (paragraph [0106]).
Liao, as modified, has further taught wherein the one communication links in each of the first and second subsets, the first pair of communication links in each of the first and second subsets, the second pair of communication links in each of the first and second subsets, and the third pair of communication links between the corresponding parallel processing units of the first and second subsets are configured as communication rings to couple the parallel processing units in the given set, such that each parallel processing unit, in a given communication ring, is connected to only two parallel processing units (each of these links may form part of a ring. For instance, in FIG.5B, the link between CPU0 and CPU3 in the first subset (the one communication link) is part of a ring including CPU0-CPU3-CPU1-CPU0. A similar ring would exist in the second subset/node. For the first and second pairs of links, similar rings are formed, e.g. in FIG.5B, each first pair and second pair would form a ring (e.g. CPU0-CPU1-CPU2-CPU3-CPU0, or CPU0-CPU1-CPU2-CPU0, and so on). Similar rings would exist in the second subset. For the third pair of links, rings are also formed. For instance, from FIG.9, a ring would be CPU0-CPU5-CPU4-CPU3-CPU2-CPU0. Another ring would be CPU0-CPU5-CPU7-CPU2-CPU0 (FIG.9). Various rings may be realized; the examiner has merely given examples.
Referring to claim 1, Liao, under a second interpretation, has taught a compute system comprising:
one or more sets of parallel processing units (see FIG.4, and note the set of CPUs), wherein the parallel processing units in a given set are organized into subsets of parallel processing units (see FIG.4, which shows two subsets, each with four CPUs (the first subset including CPUs 0, 1, 2, and 3; and the second subset including CPUs 4, 5, 6, and 7)), wherein a parallel processing unit in a first subset of parallel processing units is configurably couplable to a first of two nearest neighbor parallel processing units in a first subset by a first pair of communication links (see FIG.10B. CPU0 can be coupled (is configurably couplable) to nearest neighbor CPU1, in the same first subset, with two communication links, when the load on CPU0 is high (paragraph [0143])), and wherein the parallel processing unit is configurably couplable to a second of the two nearest neighbor parallel processing units in the first subset by a second pair of communication links (again, see FIG.10B. CPU0 can be coupled (is configurably couplable) to second nearest neighbor CPU2, in the first subset, with two communication links, when the load on CPU0 is high (paragraph [0143])), wherein each parallel processing unit in the first subset is configurably couplable to a farthest neighbor parallel processing unit in the first subset by one communication link (see FIG.10B. CPU0 can be connected (is configurably coupled) to farthest neighbor CPU3 by one link (either of the two links shown is “one link”). CPU1 and CPU2 are similarly connected The examiner notes that the claim does not say “only one link”. This could be done using the switches of FIG.4).
Liao has not explicitly taught that each parallel processing unit in the first subset is configurably couplable to two nearest neighbor parallel processing units in a first subset by a first and second pair of communication links. However, one of ordinary skill in the art would recognize that FIG.10B shows an example and that any configuration could be implemented, depending on load (see paragraph [0145]). That is, if CPU3 is also experiencing high load, it too can include two links to its nearest neighbors so as to improve latency and reduce load. As a result, in order to reduce load on all CPUs, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Liao such that each parallel processing unit in the first subset is configurably couplable to two nearest neighbor parallel processing units in a first subset by a first and second pair of communication links.
With respect to the limitation “wherein the each parallel processing unit in the first subset is configurably couplable to a corresponding parallel processing unit in a second subset by a third pair of communication links”, this is not patentable for multiple reasons:
Under a first interpretation, see FIG.10B, which has inter-node connections (the arrows under CPU2 and CPU3) that allow connections to CPUs of at least one other node (e.g. see FIG.9 and paragraph [0106]). The three arrows/connections shown in FIG.10B include a pair of links that connect every processing element (CPU0, 1, 2, and 3 to a unit in another node (either directly or indirectly). Any CPU can be connected by multiple links depending on load (paragraph [0143]).
Under a second interpretation where only direct connections are considered, Liao has not taught the limitation in question. Instead, Liao shows that each CPU in one node may be couplable to a CPU in another node (e.g. see FIGs.4 and 9). However, Official Notice is taken that one link comprising multiple links, one for each bit, was well known in the art before applicant’s invention. That is, for a CPU to transmit 32 bits, for example, it is fastest to send all 32 bits in parallel, which requires 32 1-bit links that make up an overall communication link. As a result, to maximize transfer speed, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Liao such that the one taught communication link is made up of multiple 1-bit links, thereby realizing coupling by two (or more) communication links.
Liao has further taught wherein the one communication links in each of the first and second subsets, the first pair of communication links in each of the first and second subsets, the second pair of communication links in each of the first and second subsets, and the third pair of communication links between the corresponding parallel processing units of the first and second subsets are configured as communication rings to couple the parallel processing units in the given set, such that each parallel processing unit, in a given communication ring, is connected to only two parallel processing units (when each of these links exists, it may be seen as part of a ring. For instance, in FIG.8, the link between CPU0 and CPU3 in the first subset is part of a ring including CPU0-CPU3-CPU1-CPU0. A similar ring would exist in the second subset in FIG.8. For the first and second pairs of links, similar rings are formed (again, from FIG.10B, each CPU can have two links to each other CPU to reduce load). Thus, in FIG.10B, each first pair and second pair would form a ring (e.g. CPU0-CPU1-CPU2-CPU3-CPU0, or CPU0-CPU1-CPU2-CPU0, and so on). Similar ring would exist in the second subset. For the third pair of links, when they exist, rings are also formed. For instance, from FIG.9, a ring would be CPU0-CPU5-CPU4-CPU3-CPU2-CPU0. Other similar rings exist. In any given ring, as pointed out in the examples above, each CPU is connected to only two other CPUs).
Referring to claim 2, Liao, as modified, has taught the compute system of Claim 1, wherein the third pair of communication links to couple the corresponding parallel processing unit in the second subset comprise bi-directional communication links (see FIG.10B and any other FIG that shows interconnections. All links are bi-directional).
Referring to claim 3, Liao, as modified, has taught the compute system of Claim 1, wherein one or more compute clusters are formed by the given set of parallel processing units and different communication links of the given set of parallel processing units (see paragraphs [0130]-[0132]. Note examples in the FIGs. For instance, in FIG.1C, a partition of eight CPUs is shown. However, if the terminals 111 are coupled to 112, two partitions (clusters) are formed since nodes 20 and 30 would be disconnected), and wherein the one or more compute clusters include a corresponding number of the communication rings based on a specified compute parameter (see FIG.4, for instance. At least one specified compute parameter is used to control switches A1, A2 in order to create a communication ring. Other FIGs show rings as well).
Referring to claim 4, Liao, as modified, has taught the compute system of Claim 3, but has not taught wherein each of the one or more compute clusters is configured to compute a corresponding Reduce or All_Reduce function on corresponding input data using a parallel ring Reduce or All_Reduce algorithm. However, such functions are well known in the art. For instance, All_Reduce uses distributed processing to speed up a reduction problem and then distribute/broadcast the result to all processors. Liao is a fully-connected distributed system that may be used for such a task to allow it to quickly reduce larger problems. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Liao such that each of the one or more compute clusters are configured to compute a corresponding Reduce or All_Reduce function on corresponding input data using a parallel ring Reduce or All_Reduce algorithm.
Referring to claim 5, Liao, as modified, has taught the compute system of Claim 3, wherein the specified compute parameter comprises a number of parallel processing units of a given compute cluster (see FIG.4. The specifies compute parameter controls all switches. The switches may be configured such that there are two clusters of four independent CPUs. The switches may also be configured such that there is one cluster of eight CPUs. Thus, the parameter indicates a number of units in a cluster).
Referring to claim 6, Liao, as modified, has taught the compute system of Claim 3, wherein the specified compute parameter comprises an amount of compute processing bandwidth (the parameter may also comprise a parameter that causes additional links to be established (e.g. to go from FIG.5B to 10B). Such a parameter indicates more bandwidth because there are more links between the CPUs).
Response to Arguments
On pages 13-14 of applicant’s response, applicant argues that there is no description of a single embodiment in which the one communication link in two nodes, the first pair of links, the second pair of links, and the third pair of links are all configured to form communication rings. Applicant further argues that, in Liao, either the farthest CPUs within a node are connected with no inter-node lines (FIG.8), or some CPUs have inter-node lines with no line connecting the farthest CPUs with a node (FIG.9).
The examiner initially notes that claim 1 does not require that all communication links be established at the same time, nor does claim 1 require that all of the claimed rings be established at the same time. The examiner notes that the topology can be changed in Liao and, in doing so, different rings may be formed, including at different times. The claim encompasses this operation and is thus non-distinguishing. This is addressed in the second rejection of claim 1 above.
On page 14 of applicant’s response, applicant argues that, in the configurations of FIGs.8 and 10B, there is no connection between CPUs of different nodes.
For FIG.8, the examiner agrees. In FIG.5B, the examiner would disagree. In FIG.10B, the examiner disagrees as well, since the nodes underneath CPU2 and CPU3 are inter-node connections, which couple the entire node (and all CPUs therein) to another node (and all CPUs therein). It is the examiner’s understanding of Liao that, in FIG.10B, if an extra link were implemented between CPU3 and each of CPU1 and CPU2, then there would be no internode connections. However, as stated above, not all links and rings need to be present at the same time in applicant’s claimed system (hence, the second rejection of claim 1).
On pages 14-15 of applicant’s response, applicant argues that there is no direct connection between the CPUs of different nodes.
The examiner first notes that direct connection is not required. However, FIGs.3-4 do effectively teach direct coupling based on switch configuration.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/David J. Huisman/Primary Examiner, Art Unit 2183
Prosecution Insights