Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/18/2025 has been entered.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 11, 15, 19, 20, 23-26 and 28-30 rejected under 35 U.S.C. 103 as being unpatentable over Alter (U.S. Patent No. 4,914,546) of record, in view of Bez (U.S. Patent No. 6,222,245) of record, in view of Chung (U.S. Patent Pub. No. 2019/0105840).
Regarding Claim 1
FIG. 3 of Alter discloses an integrated circuit comprising: a substrate (40) including first (left end of 42), second (right end of 42), and third doped (middle portion of 42) regions, the third doped region being between the first and second doped regions, and the first and second doped region having dopants of a same polarity; an insulation layer (50) over the substrate; and a multi-layer metal (Ti, TiW or SiCr) interconnect structure on the substrate and covered by the insulation layer, the multi-layer metal interconnect structure including :a first terminal (contact of 58 to 42) electrically coupled to the first doped region, the first terminal being in a first metal layer of the multi-layer metal interconnect structure; a first metal interconnect (48) in a second metal layer of the multi-layer metal interconnect structure, in which the first metal interconnect directly opposes the third doped region and is outside footprints of the first and second doped regions, the first metal interconnect is separated from the substrate by part of the insulation layer and is electrically coupled to the first terminal, the first metal layer being between the second metal layer and the substrate; and a second metal interconnect (54) in a third metal layer of the multi-layer metal interconnect structure, in which the first metal layer is between the third metal layer and the substrate, the second metal interconnect directly opposes the first metal interconnect and is outside the footprints of the first and second doped regions.
Alter fails to disclose “a second terminal electrically coupled to the second doped region, the second terminal being in the first metal layer”; and “the second metal interconnect is electrically coupled to a second terminal”.
FIG. 1 of Bez discloses a similar system, comprising a second metal interconnect (POLY2) in a third metal layer of the multi-layer metal interconnect structure, in which the second metal interconnect directly opposes the first metal interconnect (POLY1); the second metal interconnect is electrically (capacitively) coupled to a second terminal (TC3), and the first and second metal interconnects are configured to capacitively couple signals between them.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Alter, as taught by Bez. The ordinary artisan would have been motivated to modify Alter in the above manner for the purpose of forming monolithically integrated circuit with high capacitance (Col. 1, Lines 9-17 of Bez).
Alter as modified by Bez fails to disclose “the first metal interconnect includes aluminum or copper” and “the second metal interconnect includes aluminum or copper”.
Alter discloses FIG. 3 of Chung discloses a similar system, wherein the first metal interconnect includes aluminum or copper; and the second metal interconnect includes aluminum or copper [0069].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Alter such that the titanium of first metal interconnect and the second metal interconnect is replaced by copper or aluminum, as taught by Chung, because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values ([00053] of Chung), MPEP 2144.0. The ordinary artisan would have been motivated to modify Alter in the above manner, because copper or aluminum has excellent conductivity, which remains stable as frequency increases.
The claim “the first metal interconnect and the second metal interconnect are configurable capacitively couple signals having a frequency in a gigahertz (GHz) range between them” containing a recitation with respect to the manner in which a claimed apparatus is intended to be employed. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Alter teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Regarding Claim 2
FIG. 3 of Alter discloses the first, second, and third doped regions are part of a continuous uniform doped region in the substrate.
Regarding Claim 11
FIG. 3 of Alter discloses a system comprising: isolation circuitry having a first data terminal (60), a second data terminal (62); a first reference terminal (portion of 58 in contact to 42), and including: a semiconductor substrate (40) including first (left end of 42), second (right end of 42), and third doped (middle portion of 42) regions, the third doped region being between the first and second doped regions, the first and second doped regions having dopants of a same polarity, the first doped region electrically coupled to the first reference terminal; an insulation layer (50) over the semiconductor substrate; and a multi-layer metal (Ti, TiW or SiCr) interconnect structure on the semiconductor substrate and covered by the insulation layer, the multi-layer metal interconnect structure including: a first metal layer including the first and second reference terminals; a first metal interconnect (48) in a second metal layer of the multi-layer metal interconnect structure, in which the first metal layer is between the second metal layer and the substrate, the first metal interconnect directly opposes the third doped region and is outside footprints of the first and second doped regions, the first metal interconnect is separated from the semiconductor substrate by part of the insulation layer, and the first metal interconnect and is electrically coupled to the first data terminal; and a second metal interconnect (54) in a third metal layer of the multi-layer metal interconnect structure, in which the first metal layer is between the third metal layer and the substrate, the second metal interconnect directly opposes the first metal interconnect, the second metal interconnect is electrically coupled to the second data terminal, and the first and second metal interconnects are configured to capacitively couple signals between them.
Alter fails to disclose “a second reference termina” and “the second doped region electrically coupled to the second reference terminal”.
FIG. 1 of Bez discloses a similar system, comprising a second metal interconnect (POLY2) in a third metal layer of the multi-layer metal interconnect structure, in which the second metal interconnect directly opposes the first metal interconnect (POLY1); the second metal interconnect is electrically (capacitively) coupled to a second reference terminal (TC3), and the first and second metal interconnects are configured to capacitively couple signals between them.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Alter, as taught by Bez. The ordinary artisan would have been motivated to modify Alter in the above manner for the purpose of forming monolithically integrated circuit with high capacitance (Col. 1, Lines 9-17 of Bez).
Alter as modified by Bez fails to disclose “the first metal interconnect includes aluminum or copper” and “the second metal interconnect includes aluminum or copper”.
Alter discloses FIG. 3 of Chung discloses a similar system, wherein the first metal interconnect includes aluminum or copper; and the second metal interconnect includes aluminum or copper [0069].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Alter such that the titanium of first metal interconnect and the second metal interconnect is replaced by copper or aluminum, as taught by Chung, because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values ([00053] of Chung), MPEP 2144.0. The ordinary artisan would have been motivated to modify Alter in the above manner, because copper or aluminum has excellent conductivity, which remains stable as frequency increases.
The claim “the first metal interconnect and the second metal interconnect are configurable capacitively couple signals having a frequency in a gigahertz (GHz) range between them” containing a recitation with respect to the manner in which a claimed apparatus is intended to be employed. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Alter teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Regarding Claim 15
FIG. 3 of Alter discloses the first, second, and third doped regions are part of a continuous uniform doped region in the substrate.
Regarding Claim 19
FIG. 3 of Alter discloses a method of making an integrated circuit comprising: forming, in a substrate (40), a first doped region (left end of 42); forming, in the substrate, a second doped region (right end of 42), the first and second doped regions having dopants of a same polarity; forming, in the substrate, a third doped region (middle portion of 42) between the first and second doped regions; forming an insulation layer (50) on the substrate; and forming a multi-layer metal (Ti, TiW or SiCr) interconnect structure on the substrate and covered by the insulation layer, the multi-layer metal interconnect structure including: a first metal layer including a first reference terminal (contact of 58 to 42) electrically coupled to the first doped region; a first metal interconnect (48) in a second metal layer of the multi-layer metal interconnect structure, in which the first metal layer is between the second metal layer and the substrate, the first metal interconnect directly opposes the third doped region and is outside footprints of the first and second doped regions, the first metal interconnect is separated from the substrate by part of the insulation layer and is electrically coupled to a first data terminal (60); and a second metal interconnect (54) in a third metal layer of the multi-layer metal interconnect structure, in which the first metal layer is between the third metal layer and the substrate, the second metal interconnect directly opposes the first metal interconnect, and the second metal interconnect is electrically coupled to a second data terminal (62).
Alter fails to disclose “a second reference terminal electrically coupled to the second doped region”
FIG. 1 of Bez discloses a similar method, comprising a second metal interconnect (POLY2) in a third metal layer of the multi-layer metal interconnect structure, in which the second metal interconnect directly opposes the first metal interconnect (POLY1); the second metal interconnect is electrically (capacitively) coupled to a second reference terminal (TC3), and the first and second metal interconnects are configured to capacitively couple signals between them.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the method of Alter, as taught by Bez. The ordinary artisan would have been motivated to modify Alter in the above manner for the purpose of forming monolithically integrated circuit with high capacitance (Col. 1, Lines 9-17 of Bez).
Alter as modified by Bez fails to disclose “the first metal interconnect includes aluminum or copper” and “the second metal interconnect includes aluminum or copper”.
Alter discloses FIG. 3 of Chung discloses a similar system, wherein the first metal interconnect includes aluminum or copper; and the second metal interconnect includes aluminum or copper [0069].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Alter such that the titanium of first metal interconnect and the second metal interconnect is replaced by copper or aluminum, as taught by Chung, because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values ([00053] of Chung), MPEP 2144.0. The ordinary artisan would have been motivated to modify Alter in the above manner, because copper or aluminum has excellent conductivity, which remains stable as frequency increases.
Regarding Claim 20
FIG. 3 of Alter discloses the first, second, and third doped regions are part of a continuous doped region in the substrate.
Regarding Claim 23
Modified Alter discloses each of the first and second reference terminals is configured to be coupled to a respective voltage reference.
Regarding Claim 24
FIG. 2 of Bez discloses a ground terminal electrically coupled to each of the first and second reference terminals [0064].
Regarding Claim 25
FIG. 3 of Alter discloses the first metal layer is directly over the third doped region.
Regarding Claim 26
Modified Alter discloses the first and second metal layers are configured to transmit a signal. The dopant concentration of the third doped region determines the conductivity of the lower electrode of the capacitor, and consequently, the quality factor of the capacitor (the quality factor depends on the capacitor’s parasitic resistance). Therefore, Modified Alter reads on the claimed limitations.
Regarding Claim 28
FIG. 2 of Bez discloses the first metal layer is separated from the second metal layer by the insulation layer.
Regarding Claim 29
FIG. 1 of Bez discloses the first metal layer is separated from the second metal layer by the insulation layer.
Regarding Claim 30
FIG. 1 of Bez discloses the first metal layer is separated from the second metal layer by the insulation layer.
Claims 3-7, 9, 10, 16, 18, 21 and 22 rejected under 35 U.S.C. 103 as being unpatentable over Alter, Bez and Chung, in view of Schade (U.S. Patent No. 4,211,941) of record.
Regarding Claim 3
Alter as modified by Bez and Chung discloses Claim 1.
Alter as modified by Bez and Chung fails to disclose “the substrate is a p-type substrate, and the continuous uniform doped region is a p+ doped region”.
FIG. 2 of Schade discloses a similar system, wherein the substrate (50) is a p-type substrate, and the continuous uniform doped region (51) is a p+ doped region.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Alter, as taught by Schade. The ordinary artisan would have been motivated to modify Alter in the above manner for the purpose of improving the flow of leakage current (Abstract of Schade).
Regarding Claim 4
FIG. 1 of Bez discloses the substrate is a n-type substrate, and the continuous doped region is a n+ doped region.
Regarding Claim 5
FIG. 2 of Schade discloses the substrate includes a well (52), and the third doped region (57) in the well.
Regarding Claim 6
FIG. 1 of Bez discloses the substrate (3) is a p-type substrate, the well (4) is an n-well. FIG. 3 of Alter discloses each of the first and second doped regions includes a respective n+ doped region, and the third doped region includes a n+ doped region.
Regarding Claim 7
FIG. 1 of Bez discloses the substrate (3) is a p-type substrate, the well (4) is an n-well. FIG. 3 of Alter discloses each of the first and second doped regions includes a respective n+ doped region, and the third doped region includes a n+ doped region. With respect to “the substrate is an n-type substrate, the well is a p-well, each of the first and second doped regions includes a p+ doped region, and the third doped region includes an p+ doped region”, the configuration of the claimed “n-type” was a matter of choice, which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed “n-type” was significant; thus the particular claimed configuration is one of numerous configurations a person of ordinary skill in the art would find obvious for the purpose of equivalent replacement (Para. 58 of Du). In re Dailey, 149 USPQ 47, 50 (CCPA 1966). See also Glue Co. v. Upton, 97 US 3, 24 (USSC 1878). MPEP § 2144.04.
Regarding Claim 9
FIG. 3 of Alter discloses each of the first and second regions includes a respective non-patterned region.
Regarding Claim 10
FIG. 1 of Bez discloses each of the first and second regions includes a respective patterned region.
Regarding Claim 16
FIG. 2 of Schade discloses the substrate is a p-type substrate (50), and the continuous uniform doped region (57) is a p+ doped region. With respect to “the substrate is a n-type substrate, and the continuous doped region is a n+ doped region”. The configuration of the claimed “n-type” was a matter of choice, which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed “n-type” was significant; thus, the particular claimed configuration is one of numerous configurations a person of ordinary skill in the art would find obvious for the purpose of equivalent replacement (Para. 58 of Du). In re Dailey, 149 USPQ 47, 50 (CCPA 1966). See also Glue Co. v. Upton, 97 US 3, 24 (USSC 1878). MPEP § 2144.04.
Regarding Claim 18
FIG. 2 of Schade discloses the semiconductor substrate (52) is an n-type substrate including a p-well (56) between the first and second doped regions (63), wherein the third doped region (57) is a p+ doped region; and each of the first and second doped regions includes a respective n+ doped region.
Regarding Claim 21
FIG. 2 of Schade discloses forming a well (52) in the part of the substrate, and forming a third doped region (57) in the well.
Regarding Claim 22
FIG. 2 of Schade discloses each of the first and second doped regions includes a respective p+ doped region or a respective n+ doped region.
Claim 8 rejected under 35 U.S.C. 103 as being unpatentable over Alter, Bez and Chung, in view of Divakaruni (U.S. Patent No. 6,429,068) of record.
Regarding Claim 8
Alter as modified by Bez and Chung discloses Claim 1.
Alter as modified by Bez and Chung fails to disclose “each of the first and second doped regions includes a respective silicided region”.
FIG. 5 of Divakaruni discloses a similar integrated circuit, wherein each of the first and second doped regions (357) includes a respective silicided region (309).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Alter, as taught by Divakaruni. The ordinary artisan would have been motivated to modify Alter in the above manner for the purpose of minimizing parasitic resistance.
Claims 12-14 rejected under 35 U.S.C. 103 as being unpatentable over Alter, Bez and Chung, in view of Sankaran (U.S. Patent Pub. No. 2018/0278229) of record.
Regarding Claim 12
Alter as modified by Bez and Chung discloses Claim 11, wherein the isolation circuitry is first isolation circuitry, the semiconductor substrate is a first semiconductor substrate, the insulation layer is a first insulation layer.
It would have been obvious to one of ordinary skill in the art that the system further comprising: second isolation circuitry, the second isolation circuitry having a third data terminal, a fourth data terminal, a third reference terminal, and a fourth reference terminal, and including: a second semiconductor substrate including fourth, fifth, and sixth doped regions, the sixth doped region being between the fourth and fifth doped region, the fourth doped region electrically coupled to the third reference terminal, and the fifth doped region electrically coupled to the fourth reference terminal, a second insulation layer on the second semiconductor substrate and a second multi-layer metal interconnect structure on the second semiconductor substrate and covered by the second insulation layer, the second multi- layer metal interconnect structure including: a first metal layer including the third and fourth reference terminals; a third metal interconnect in a second metal layer of the second multi-layer metal interconnect structure, in which the third metal interconnect directly opposes the sixth doped region and is separated from the second semiconductor substrate by part of the second insulation layer, and the third metal interconnect is electrically coupled to the third data terminal; and a fourth metal interconnect in a third metal layer of the second multi-layer metal interconnect structure, in which the fourth metal interconnect directly opposes the third metal interconnect, the fourth metal interconnect is electrically coupled to the fourth data terminal, and the third and fourth metal interconnects are configured to capacitively couple data signals between them; and wherein the first isolation circuitry is part of a first integrated circuit, and the second isolation circuitry is part of a second integrated circuit, because mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See MPEP 2144.04.
Alter as modified by Bez and Chung fails to explicitly disclose “the first isolation circuitry is part of a first integrated circuit, and the second isolation circuitry is part of a second integrated circuit”.
FIG. 1 of Sankaran discloses a similar system, wherein the first isolation circuitry is part of a first integrated circuit, and the second isolation circuitry is part of a second integrated circuit.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Alter, as taught by Sankaran. The ordinary artisan would have been motivated to modify Alter in the above manner for the purpose of improving common mode performance (Para. 1 of Sankaran).
Regarding Claim 13
Alter as modified by Bez and Chung discloses Claim 11, wherein the isolation circuitry is first isolation circuitry, the isolation capacitor is a first isolation capacitor.
It would have been obvious to one of ordinary skill in the art that the system further comprising: second isolation circuitry having a third data terminal, a fourth data terminal, a third reference terminal, and a fourth reference terminal, the third and fourth reference terminals being in the first metal layer of the multi-layer metal interconnect structure, and the second isolation circuitry including: a third metal interconnect in the second metal layer of the first multi-layer metal interconnect structure, in which the third metal interconnect directly opposes the third doped region and is separated from the semiconductor substrate by part of the insulation layer, and the third metal interconnect is electrically coupled to the third data terminal; and a fourth metal interconnect in the third metal layer of the multi-layer metal interconnect structure, in which the fourth metal interconnect directly opposes the third metal interconnect, the fourth metal interconnect is electrically coupled to the fourth data terminal, and the third and fourth metal interconnects, because mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See MPEP 2144.04.
Alter as modified by Bez and Chung fails to explicitly disclose “second isolation circuitry electrically coupled to the first isolation circuitry” and “the first isolation circuitry and the second isolation circuitry are part of an integrated circuit”.
FIG. 1 of Sankaran discloses a similar system, wherein the second isolation circuitry electrically coupled to the first isolation circuitry, the first isolation circuitry and the second isolation circuitry are part of an integrated circuit.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Alter, as taught by Sankaran. The ordinary artisan would have been motivated to modify Alter in the above manner for the purpose of improving common mode performance (Para. 1 of Sankaran).
Regarding Claim 14
FIG. 1 of Sankaran discloses the first isolation circuitry and the second isolation circuitry are part of a first integrated circuit, the system further comprising: a second integrated circuit including transmit circuitry coupled to the second digital data terminal; and a third integrated circuit including receive circuitry coupled to the fourth digital data terminal.
Claim 17 rejected under 35 U.S.C. 103 as being unpatentable over Alter, Bez and Chung, in view of Monticelli (U.S. Patent No. 4,758,873) of record.
Regarding Claim 17
Alter as modified by Bez and Chung discloses Claim 11, wherein the substrate is a p-type substrate including an n-well, an n+ doped region within the n-well.
Alter as modified by Bez and Chung fails to disclose the n-well between the first and second doped regions, each of the first and second doped regions includes a respective p+ doped region”.
FIG. 3 of Monticelli discloses a similar integrated circuit, wherein the substrate (17) is a p-type substrate including an n-well in the part of the semiconductor substrate between the first (18) and second doped (18) regions.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Alter, as taught by Monticelli. The ordinary artisan would have been motivated to modify Alter in the above manner for the purpose of providing a balanced capacitor having low stray capacitance and resisting ESD damage (Col. 1, Lines 56-59 of Monticelli).
Claim 27 rejected under 35 U.S.C. 103 as being unpatentable over Alter, Bez and Chung, in view of Candelier (U.S. Patent Pub. No. 2007/0114596) of record.
Regarding Claim 27
Alter as modified by Bez and Chung discloses Claim 1.
Alter as modified by Bez and Chung fails to disclose “a first dopant concentration of the third doped region is at least 100 times of a second dopant concentration of the substrate”.
FIG. 1 of Candelier discloses a similar integrated circuit, wherein a first dopant concentration of the third doped region [0018] is at least 100 times of a second dopant concentration of the substrate [0042].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Alter, as taught by Candelier. The ordinary artisan would have been motivated to modify Alter in the above manner for the purpose of increasing the integration level and reducing the cost (Para. 10 of Candelier).
Pertinent Art
US 6788574 discloses the first conductive layer electrically coupled to a first digital data terminal; and the second conductive between the first conductive laver and the third doped region, the second conductive layer electrically coupled to a second data digital terminal, the first and second conductive layers configured to capacitively couple digital data signals between them. US 5761121 discloses the substrate is a p-type substrate, the well is an n-well, and the third doped region includes a p+ doped region. US 4831431 discloses a multi-layer metal interconnect structure on the substrate and covered by the insulation layer. US 4290186 discloses an integrated circuit comprising: a substrate including first, second, and third doped regions, the third doped region being between the first and second doped regions, and the first and second doped region having dopants of a same polarity; an insulation layer on the substrate; and a metal interconnect structure on the substrate and covered by the insulation layer, the metal interconnect structure including: a first terminal electrically coupled to the first doped region; a second terminal electrically coupled to the second doped region. Tsai (U.S. Patent Pub. No. 2005/0263813) discloses a second metal interconnect (122) in a third metal layer of the multi-layer metal interconnect structure, in which the second metal interconnect directly opposes the first metal interconnect (116), the first metal interconnect is electrically coupled to a third terminal (128); the second metal interconnect is electrically coupled to a second terminal (132), and the first and second metal interconnects are configured to capacitively couple signals between them. US 6104080 discloses a first terminal electrically coupled to the first doped region, the first terminal being in a first metal layer of the multi-layer metal interconnect structure; a second terminal electrically coupled to the second doped region, the second terminal being in the first metal layer. US 6404269 discloses an integrated circuit comprising: a substrate including first, second, and third doped regions, the third doped region being between the first and second doped regions, and the first and second doped region having dopants of a same polarity; a metal interconnect structure on the substrate; a first terminal electrically coupled to the first doped region; a second terminal electrically coupled to the second doped region; the first metal interconnect directly opposes the third doped region and is electrically coupled to a first terminal.
Response to Arguments
Applicant’s arguments with respect to Claims 1, 11 and 19 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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