DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 5/01/26. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-10, and 23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dias et al. (US PGPub 2003/0104679, hereinafter referred to as “Dias”).
Dias discloses the semiconductor device substantially as claimed. See figures 1-14 and corresponding text, where Dias teaches, in claim 1, a microelectronic device comprising:
an active surface (104) (figure 3; [0035]);
a side surface (122) extending vertically from the active surface (104), the side surface (122) including:
a first portion (126) comprising at least about 50% of the side surface, the first portion having a reflective conductive surface throughout the first portion (figure 3; [0036], the V-shaped notch is preferably about one-half of the thickness of the microelectronic device wafer. In addition, applicant describes the reflective materials to be tungsten, titanium, etc. [0037], thus Dias teaches titanium, tungsten [0034] as the metallization layer (128)); and
a second, vertically adjacent portion (124’) (at the corner surfaces of both the (124) and (124’) are vertically adjacent) having an uneven non-reflective surface (122) (figures 3 and 4; [0034-0035], the semiconductor surfaces underneath the metallization layer are the uneven non-reflective surfaces).
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Dias teaches, in claim 2, wherein the reflective conductive surface comprises a metal material ([0034]).
Dias teaches, in claim 3, wherein the metal material is selected from the group consisting of copper, tungsten, and titanium ([0034]).
Dias teaches, in claim 5, wherein the uneven non-reflective surface comprises a fractured surface of semiconductor material ([0033-0034], the examiner views the portion being removed to form the V-notch is the fracture surface of the semiconductor wafer).
Dias teaches, in claim 6, wherein the first portion includes two superimposed materials (figure 3; [0030]).
Dias teaches, in claim 7, wherein the two superimposed materials include a diffusion barrier adjacent a semiconductor material and a conductive material over the diffusion barrier (figure 3; [0030]).
Dias teaches, in claim 8, wherein the diffusion barrier comprises a material selected from a group consisting of nitride, silicon nitride, tantalum, tantalum nitride ([0030]).
Dias teaches, in claim 9, wherein the conductive material comprises a metal ([0030]).
Dias teaches, in claim 10, wherein the conductive material comprises a material selected from the group consisting of copper, tungsten, titanium ([0030]).
Dias teaches, in claim 23, a microelectronic device package comprising:
a stack of microelectronic devices (144, 144’), each including:
an active surface (104) (figure 5; [0035])
a side surface (at the corner surfaces of both the (124) and (124’) are vertically adjacent) extending vertically from the active surface (104), the side surface including:
a first metal portion (128) of the side surface exhibiting a reflective surface, the first metal portion comprising at least 50% of the side surface (figure 3; [0036], the V-shaped notch is preferably about one-half of the thickness of the microelectronic device wafer; In addition, applicant describes the reflective materials to be tungsten, titanium, etc. [0037], thus Dias teaches titanium, tungsten [0034] as the metallization layer (128))); and
a second portion of the side surface, the second portion comprising a semiconductor material (102) and exhibiting a rough non-reflective surface (figures 3 and 4; [0034-0035], non-reflective surfaces underneath the reflective conductive surfaces)). (Please see modified illustration below)
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Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3, 5-10, and 23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s amendment has necessitated new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 May 21, 2026
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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