DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114 was filed in this application after a decision by the Patent Trial and Appeal Board, but before the filing of a Notice of Appeal to the Court of Appeals for the Federal Circuit or the commencement of a civil action. Since this application is eligible for continued examination under 37 CFR 1.114 and the fee set forth in 37 CFR 1.17(e) has been timely paid, the appeal has been withdrawn pursuant to 37 CFR 1.114 and prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant’s submission filed on 2/27/2026 has been entered.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-6 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Cheng et al. (US 2011/0303915 A1) in view of Lin (US 2011/0193141 A1).
Regarding claim 1, Cheng discloses an integrated circuit structure (Fig. 10), comprising:
a fin (corresponding to bottom 21 extending left to right in Fig. 9) consisting essentially of silicon (¶ 0037), the fin having a top and sidewalls, wherein the top has a longest dimension along a first direction (left to right);
an isolation structure (left 50) separating a first portion (left third) of the fin from a second portion of the fin along the first direction, the isolation structure having a width along the first direction (see Fig. 10);
a first gate structure (left 70) comprising a first gate electrode (“gate” in ¶ 0018) over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin, and the first gate structure further comprising a first dielectric layer (“gate dielectric” in ¶ 0018) between the first gate electrode and the first portion of the fin and along sidewalls of the first gate electrode, wherein the first gate structure has a width along the first direction, and wherein a center of the first gate structure is spaced apart from a center of the isolation structure by a pitch along the first direction;
a second gate structure (middle 70) comprising a second gate electrode (“gate” in ¶ 0018) over the top of and laterally adjacent to the sidewalls of a first region of the second portion of the fin, and the second gate structure further comprising a second dielectric layer (“gate dielectric” in ¶ 0018) between the second gate electrode and the second portion of the fin and along sidewalls of the second gate electrode, wherein the second gate structure has a width along the first direction, and wherein a center of the second gate structure is spaced apart from a center of the isolation structure by a pitch along the first direction.
Cheng does not show in Fig. 10 a third gate structure over a second region of the second portion of the fin as claimed.
However, Cheng discloses an embodiment that additional gate structures may be interposed between isolation structures 50 (¶ 0042).
In such an embodiment, a third gate structure (formed to the immediate right of the second gate structure) comprising a third gate electrode will be formed over the top of and laterally adjacent to the sidewalls of a second region of the second portion of the fin, and the third gate will further comprise a third dielectric layer between the third gate electrode and the second portion of the fin and along sidewalls of the third gate electrode, wherein the third gate structure has a width along the first direction and wherein a center of the third gate structure is spaced apart from the center of the second gate structure by a pitch along the first direction.
Cheng does not disclose the specific widths of the isolation structure and the gate structures to determine if they have the same width.
However, Cheng teaches that the isolation structure transmits stress to the fin by exerting pressure (¶ 0004). The efficacy of the isolation structure for this result depends on the size of the isolation structure (i.e., the width). If the width is too large, the pressure and, correspondingly, the imbued stress will be too high. If the width is too small, there will be insufficient stress on the fin. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to optimize the width of the isolation region to be the width of gate structures. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." (In re Aller, 105 USPQ 233 (C.C.P.A. 1955); MPEP § 2144.05(II)(A)).
Cheng does not explicitly state that a center of the first gate structure is spaced apart from a center of the isolation structure by the same pitch as a center of the second gate structure to the center of the isolation structure and a center of the third gate structure from the center of the second gate structure.
However, one having ordinary skill in the art at the time the invention was made would have found it obvious to form the first gate structure, second gate structure, third gate structure, and isolation structure to be at an equal pitch for the benefit of reducing the complexity of an alignment process during manufacturing.
Cheng does not disclose embedded epitaxial semiconductor regions formed in the portions of the fin consisting essentially of silicon germanium.
However, it is known in the art to form embedded epitaxial semiconductor regions in portions of fins consisting essentially of silicon germanium (¶ 0047 and Figs. 4F and 4G of Lin).
Lin discloses a benefit to using epitaxial layers as such in that it improves facet profile control (¶ 0025).
One having ordinary skill in the art at the time the invention was made would have therefore found it obvious to include a first embedded epitaxial semiconductor region in the first portion of the fin between the first gate structure and the isolation structure, a second embedded epitaxial semiconductor region in the second portion of the fin between the second gate structure and the isolation structure, and a third embedded epitaxial semiconductor region in the second portion of the fin between the second gate structure and the third gate structure, with each of the epitaxial regions consisting essentially of SiGe, for this benefit.
In the resulting configuration, the first, second, and third embedded epitaxial semiconductor regions will have a bottommost surface above the bottommost surface of the isolation structure (as the bottommost surface of the embedded epitaxial semiconductor regions are above the bottommost surfaces of the fins (see Figs. 4F and 4G of Lin) and the bottommost surfaces of the fins are coplanar with the bottommost surfaces of the isolation structure (see Figs. 9 and 10 of Cheng).
Regarding claims 2-4, Lin discloses that the embedded epitaxial semiconductor regions extend outwardly from the sides of the underlying fin (see Fig. 4G). As such, the first, second, and third epitaxial semiconductor regions will have widths along a second direction orthogonal to the first direction, the width along the second direction wider than a width of the first and second portions of the fin along the second direction beneath the first and second gate structures.
Regarding claim 5, Cheng discloses that the isolation structure separating the first portion of the fin from the second portion of the fin along the first direction induces a stress on the first portion of the fin and on the second portion of the fin (¶ 0003).
Regarding claim 6, this stress is compressive stress (¶ 0003 of Cheng).
Claim 9 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Cheng in view of Lin as applied to claim 1 above, and further in view of Achuthan et al. (US 2004/0253775 A1).
Regarding claim 9, Cheng does not disclose that the isolation structure has a top substantially co-planar with the tops of the gate structures.
However, it is known in the art to using chemical mechanical polishing (CMP) on finFET devices to planarize the top surface (¶ 0034 of Achuthan).
There is a benefit to planarizing the top surfaces of the structures such that they are co-planar in that it will reduce the overall device thickness.
One having ordinary skill in the art at the time the invention was made would have found it obvious to make the isolation structure and gate structures have co-planar top surfaces for this benefit.
Claim 10 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Cheng in view of Lin as applied to claim 1 above, and further in view of Sugii et al. (US 2004/0108559 A1).
Regarding claim 10, Cheng does not disclose that the fin has a crystallographic continuity with a semiconductor substrate.
However, it is known in the art to form fins in finFET devices to have crystallographic continuity with underlying semiconductor substrates (Fig. 17 of Sugii).
There is a benefit to have the fin being in crystallographic continuity with the underlying semiconductor substrate in that it can assist in the inclusion of strain into the fin.
One having ordinary skill in the art at the time the invention was made would have found it obvious to form the fin of Cheng to have a crystallographic continuity with the underlying substrate for this benefit.
Claims 12-17 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Cheng et al. (US 2011/0303915 A1) in view of Lin (US 2011/0193141 A1) and Achuthan et al. (US 2004/0253775 A1).
Regarding claim 12, Cheng discloses an integrated circuit structure (Fig. 10), comprising:
a fin (corresponding to bottom 21 extending left to right in Fig. 9) comprising silicon (¶ 0037):
an isolation structure (left 50) above the fin and extending into the fin, the isolation structure separating a first portion (left third) of the fin from a second portion (remainder) of the fin, the isolation structure having an upper surface (see Fig. 10);
a first gate structure (left 70) over the first portion of the fin;
a first source or drain structure in the first portion of the fin (¶ 0018), the first source or drain structure between the isolation structure and the first gate structure;
a second gate structure (middle 70) over the second portion of the fin; and
a second source or drain structure in the second portion of the fin (¶ 0018), the second source or drain structure between the isolation structure and the second gate electrode.
Cheng does not disclose that the isolation structure has a top substantially co-planar with the tops of the gate structures.
However, it is known in the art to using chemical mechanical polishing (CMP) on finFET devices to planarize the top surface (¶ 0034 of Achuthan).
There is a benefit to planarizing the top surfaces of the structures such that they are co-planar in that it will reduce the overall device thickness.
One having ordinary skill in the art at the time the invention was made would have found it obvious to make the isolation structure and gate structures have co-planar top surfaces for this benefit.
Cheng does not disclose first and second source or drain structures are embedded epitaxial structures formed in the portions of the fin consisting essentially of silicon germanium.
However, it is known in the art to form embedded epitaxial source or drain structures in portions of fins consisting essentially of silicon germanium (¶ 0047 and Figs. 4F and 4G of Lin).
Lin discloses a benefit to using epitaxial layers as such in that it improves facet profile control (¶ 0025).
One having ordinary skill in the art at the time the invention was made would have therefore found it obvious to include a first embedded epitaxial source or drain portion in the first portion of the fin and a second embedded source or drain structure in the second portion of the fin between the second gate structure and the isolation structure, with each of the epitaxial regions consisting essentially of SiGe, for this benefit.
In the resulting configuration, the first and second embedded epitaxial semiconductor regions will have a bottommost surface above the bottommost surface of the isolation structure (as the bottommost surface of the embedded epitaxial semiconductor regions are above the bottommost surfaces of the fins (see Figs. 4F and 4G of Lin) and the bottommost surfaces of the fins are coplanar with the bottommost surfaces of the isolation structure (see Figs. 9 and 10 of Cheng).
Regarding claim 13, Cheng further discloses a third gate structure (right 70 in Fig. 10) over the second portion of the fin.
Cheng does not disclose that the isolation structure has a top substantially co-planar with the tops of the gate structures.
However, it is known in the art to using chemical mechanical polishing (CMP) on finFET devices to planarize the top surface (¶ 0034 of Achuthan).
There is a benefit to planarizing the top surfaces of the structures such that they are co-planar in that it will reduce the overall device thickness.
One having ordinary skill in the art at the time the invention was made would have found it obvious to make the isolation structure and gate structures have co-planar top surfaces for this benefit.
Regarding claim 14, Cheng further discloses a third source or drain structure in the second portion of the fin (¶ 0018), the third source or drain structure between the second gate electrode and the third gate structure.
Cheng does not disclose the third source or drain structure is an embedded epitaxial structure formed in the portions of the fin consisting essentially of silicon germanium.
However, it is known in the art to form embedded epitaxial source or drain structures in portions of fins consisting essentially of silicon germanium (¶ 0047 and Figs. 4F and 4G of Lin).
Lin discloses a benefit to using epitaxial layers as such in that it improves facet profile control (¶ 0025).
One having ordinary skill in the art at the time the invention was made would have therefore found it obvious to include a third embedded epitaxial source or drain portion in the third portion of the fin consisting essentially of SiGe, for this benefit.
Regarding claim 15, Cheng discloses that the first gate structure and the second gate structure each comprise a gate dielectric (“gate dielectric” in ¶ 0018) and a gate electrode (“gate” in ¶ 0018).
Regarding claim 16, Cheng discloses that the isolation structure separating the first portion of the fin from the second portion of the fin induces a stress on the first portion of the fin and on the second portion of the fin (¶ 0004).
Regarding claim 17, this stress is compressive stress (¶ 0003 of Cheng).
Claims 19-24 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Cheng et al. (US 2011/0303915 A1) in view of Lin (US 2011/0193141 A1).
Regarding claim 19, Cheng discloses an integrated circuit structure (Fig. 10), comprising:
a fin (corresponding to bottom 21 extending left to right in Fig. 9) comprising silicon (¶ 0037):
an isolation structure (left 50) through the fin, the isolation structure separating a first portion (left third) of the fin from a second portion of the fin, the isolation structure having a first side (left side), a second side (right side), and a center;
a first gate structure (left 70) over the first portion of the fin, the first gate structure a nearest gate structure to the first side of the isolation structure, the first gate structure having a center;
a first source or drain structure (¶ 0018) in the first portion of the fin between the isolation structure and the first gate structure,
a second gate structure (middle 70) over the second portion of the fin, the second gate structure a nearest gate structure to the second side of the isolation structure, the second gate structure having a center, and
a second source or drain structure (¶ 0018) in the first portion of the fin between the isolation structure and the second gate structure.
Cheng does not explicitly state that a center of the first gate structure is spaced apart from a center of the isolation structure by the same pitch as a center of the second gate structure to the center of the isolation structure.
However, one having ordinary skill in the art at the time the invention was made would have found it obvious to form the first gate structure, second gate structure, and isolation structure to be at an equal pitch for the benefit of reducing the complexity of an alignment process during manufacturing.
Cheng does not disclose first and second source or drain structures are embedded epitaxial structures formed in the portions of the fin consisting essentially of silicon germanium.
However, it is known in the art to form embedded epitaxial source or drain structures in portions of fins consisting essentially of silicon germanium (¶ 0047 and Figs. 4F and 4G of Lin).
Lin discloses a benefit to using epitaxial layers as such in that it improves facet profile control (¶ 0025).
One having ordinary skill in the art at the time the invention was made would have therefore found it obvious to include a first embedded epitaxial source or drain portion in the first portion of the fin and a second embedded source or drain structure in the second portion of the fin between the second gate structure and the isolation structure, with each of the epitaxial regions consisting essentially of SiGe, for this benefit.
In the resulting configuration, the first and second embedded epitaxial semiconductor regions will have a bottommost surface above the bottommost surface of the isolation structure (as the bottommost surface of the embedded epitaxial semiconductor regions are above the bottommost surfaces of the fins (see Figs. 4F and 4G of Lin) and the bottommost surfaces of the fins are coplanar with the bottommost surfaces of the isolation structure (see Figs. 9 and 10 of Cheng).
Regarding claim 20, Cheng does not show in Fig. 10 a third gate structure over the second portion of the fin as claimed.
However, Cheng discloses an embodiment that additional gate structures may be interposed between isolation structures 50 (¶ 0042).
In such an embodiment, a third gate structure (formed to the immediate right of the second gate structure) will be formed over the second portion of the fin, the third gate structure having a center, the center of the third gate structure spaced apart from the center of the second gate structure by a third distance, the third distance substantially the same as the first distance (see discussion of pitch in the rejection of claim 19, above).
Regarding claim 21, Cheng further discloses a third source or drain structure in the second portion of the fin (¶ 0018), the third source or drain structure between the second gate electrode and the third gate structure.
Cheng does not disclose the third source or drain structure is an embedded epitaxial structure formed in the portions of the fin consisting essentially of silicon germanium.
However, it is known in the art to form embedded epitaxial source or drain structures in portions of fins consisting essentially of silicon germanium (¶ 0047 and Figs. 4F and 4G of Lin).
Lin discloses a benefit to using epitaxial layers as such in that it improves facet profile control (¶ 0025).
One having ordinary skill in the art at the time the invention was made would have therefore found it obvious to include a third embedded epitaxial source or drain portion in the third portion of the fin consisting essentially of SiGe, for this benefit.
Regarding claim 22, the first and second gate structures of Cheng each comprise a gate dielectric (“gate dielectric” in ¶ 0018) and a gate electrode (“gate” in ¶ 0018).
Regarding claim 23, Cheng discloses that the isolation structure separating the first portion of the fin from the second portion of the fin along the first direction induces a stress on the first portion of the fin and on the second portion of the fin (¶ 0003).
Regarding claim 24, this stress is compressive stress (¶ 0003 of Cheng).
Response to Arguments
Applicant's arguments filed 2/27/2026 have been fully considered but they are not persuasive.
Applicant argues that Cheng does not disclose the newly added limitations concerning the embedded epitaxial regions. This argument is not persuasive as Cheng is not relied upon for embedded epitaxial regions. Applicant further argues “the other cited references of record fail to cure the above noted deficiencies of Cheng.” This argument is not persuasive as the obvious combination of Cheng and Lin discloses the newly added limitations, as discussed in the rejections above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5.
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/CHRISTOPHER A CULBERT/Examiner, Art Unit 2815
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