DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/12/25 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 12-14, and 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mishra et al. (U.S. 2013/0264578 A1; “Mishra”) in view of Suh (U.S. 2013/0313561 A1) and Hsiung et al. (U.S. 2014/0131720 A1; “Hsiung”).
Regarding claim 1, Mishra discloses a semiconductor device, comprising:
A buffer layer (12, Fig. 3B) ([0030]);
A first III-N material (14, Fig. 3B) over the buffer layer ([0031]);
A second III-N material (26, Fig. 3B) over the first III-N material ([0031]);
A third III-N material (28, Fig. 3B) disposed over the second III-N material ([0032]);
A cap layer (32, Fig. 3B) of III-N material ([0036]);
A gate recess (recess containing 30 and 33, Fig. 3B) extending through the cap layer, wherein the gate recess does not extend through the third III-N material (28, Fig. 3B) ([0029]);
A drain contact (22, Fig. 3B) coupled (broadly interpreted as “contacting”) to the second III-N material (26, Fig. 3B);
A gate dielectric layer (30, Fig. 3B) disposed over the third III-N material (28, Fig. 3B) in the gate recess ([0037]); and
A gate structure (33, Fig. 3B) disposed over the gate dielectric layer (30, Fig. 3B) in the gate recess ([0029]).
Yet, Mishra does not disclose the following:
An indium aluminum nitride layer over the third III-N material;
A dielectric isolation disposed adjacent to the drain contact.
Regarding (a), Mishra does not disclose an indium aluminum nitride layer over the third III-N material and underlying the cap layer. However, Suh discloses an indium aluminum nitride layer (108, Fig. 7) over a III-N material (106, Fig. 7) and underlying a cap layer (110, Fig. 7) ([0027]-[0029]). This has the advantage of providing the semiconductor device with a lower on-resistance. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Mishra with an indium aluminum nitride layer over the third III-N material and underlying the cap layer, as taught by Suh, so as to provide the semiconductor device with a lower on-resistance.
Regarding (b), Mishra does not disclose a dielectric isolation structure adjacent to the drain contact. However, Hsiung discloses a dielectric isolation structure (120, Fig. 1A) disposed adjacent to a drain contact (18, Fig. 1A) ([0016]). This has the advantage of providing electrical isolation around a periphery of a semiconductor device. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Mishra with a dielectric isolation structure disposed adjacent to a drain contact, as taught by Hsiung, so as to provide electrical isolation around a periphery of the semiconductor device.
Incorporating the dielectric isolation structure of Hsiung into the semiconductor device of Mishra as modified by Suh would result in the dielectric isolation layer extending through at least the cap layer, the indium aluminum nitride layer, and the third III-N material because the dielectric isolation structure (Hsiung: 120, Fig. 1A) in Hsiung extends from a top of the device down though to a buffer layer (Hsiung: 104, Fig. 1B) and the cap layer (Mishra: 32, Fig. 1B), the indium aluminum nitride layer (Suh: 108, Fig. 7), and the third III-N material (Mishra: 28, Fig. 1B) of Mishra as modified by Suh are located above the buffer layer (Mishra: 12, Fig. 3B).
Regarding claim 2, Mishra discloses the third III-N material (28, Fig. 3B) has a thickness of between 2 nm and 6 nm ([0033]) and a general formula of AlGaN ([0032]) but does not disclose the stoichiometry is specifically Al0.10Ga0.90N to Al0.30Ga0.70N. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select a third III-N material stoichiometry of Al0.10Ga0.90N to Al0.30Ga0.70N and thickness between 1 nm and 5 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 3, Suh discloses the indium aluminum nitride layer (108, Fig. 7), with an implicit thickness, ([0027]-[0029]) has a stoichiometry of In0.18Al0.82N ([0030]) but does not disclose its thickness is 3.5 nm to 4.5 nm. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select an indium aluminum nitride layer thickness of 3.5 nm to 4.5 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 4, Mishra discloses the cap layer has a general formula of AlGaN with an implicit thickness ([0036]) but does not disclose the stoichiometry is specifically Al0.05Ga0.95N to Al0.30Ga0.70N and the thickness is 4 nm to 20 nm. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select a cap layer stoichiometry of Al0.05Ga0.95N to Al0.30Ga0.70N and thickness of 4 nm to 20 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 5, Mishra discloses the gate dielectric layer (30, Fig. 3B) includes silicon dioxide, silicon nitride, or aluminum oxide ([0037]).
Regarding claim 6, Mishra as modified by Suh and Hsiung disclose a gate structure comprising polysilicon (Hsiung: [0014]).
Regarding claim 21, Suh discloses the indium aluminum nitride layer (108, Fig. 7), with an implicit thickness, ([0027]-[0029]) but does not disclose it must have less than 1 atomic percent indium. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select an indium concentration of less than 1 atomic percent in the indium aluminum nitride layer, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 22, Suh discloses the indium aluminum nitride layer (108, Fig. 7), with an implicit thickness, ([0027]-[0029]) has a stoichiometry of In0.18Al0.82N ([0030]) but does not disclose its thickness is 1 nm to 5 nm. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select indium aluminum nitride layer thickness of 1 nm to 5 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 7, Mishra discloses a semiconductor device, comprising:
A buffer layer (12, Fig. 3B) ([0030]);
A first GaN layer (14, Fig. 3B) over the buffer layer ([0031]);
A second GaN layer (26, Fig. 3B) over the first GaN layer ([0031]);
A first AIGaN layer (28, Fig. 3B) disposed over the second GaN layer ([0032]),
A cap layer (32, Fig. 3B) is a second AlGaN layer ([0036]);
A gate recess (recess containing 30 and 33, Fig. 3B) extending through the cap layer (32, Fig. 3B) in an enhancement mode GaN FET, wherein the gate recess does not extend through the first AIGaN layer (28, Fig. 3B) ([0029]);
A drain contact (22, Fig. 3B) of the enhancement mode GaN FET coupled to (broadly interpreted as “contacting”) the second GaN layer (26, Fig. 3B);
A gate dielectric layer (30, Fig. 3B) of the enhancement mode GaN FET disposed over the first AIGaN layer in the gate recess ([0037]); and
A gate (33, Fig. 3B) of the enhancement mode GaN FET disposed over the gate dielectric layer in the gate recess ([0029]);
Wherein, the second GaN layer (26, Fig. 3B) includes a 2-dimensional electron gas (2DEG) (29, 39, Fig. 3B) at least in a portion of the second GaN corresponding to an access region [laterally] between the gate recess (recess containing 30 and 33, Fig. 3B) and the drain contact (22, Fig. 3B).
Yet, Mishra does not disclose the following:
An indium aluminum nitride layer over the first AIGaN layer and underlying the cap layer/second AlGaN layer;
A dielectric isolation disposed adjacent to the drain contact.
Regarding (a), Suh discloses an indium aluminum nitride layer (108, Fig. 7) over a III-N material (106, Fig. 7) and underlying a cap layer (110, Fig. 7) ([0027]-[0029]). This has the advantage of providing the semiconductor device with a lower on-resistance. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Mishra with an indium aluminum nitride layer over the first AIGaN layer and underlying the cap layer/second AlGaN layer, as taught by Suh, so as to provide the semiconductor device with a lower on-resistance.
Regarding (b), Mishra does not disclose a dielectric isolation structure adjacent to the drain contact. However, Hsiung discloses a dielectric isolation structure (120, Fig. 1A) disposed adjacent to a drain contact (18, Fig. 1A) ([0016]). This has the advantage of providing electrical isolation around a periphery of a semiconductor device. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Mishra with a dielectric isolation structure disposed adjacent to a drain contact, as taught by Hsiung, so as to provide electrical isolation around a periphery of the semiconductor device.
Incorporating the dielectric isolation structure of Hsiung into the semiconductor device of Mishra as modified by Suh would result in the dielectric isolation layer extending through at least the second AlGaN layer, the indium aluminum nitride layer, and the first AlGaN layer because the dielectric isolation structure (Hsiung: 120, Fig. 1A) in Hsiung extends from a top of the device down though to a buffer layer (Hsiung: 104, Fig. 1B) and the second AlGaN layer (Mishra: 32, Fig. 1B), the indium aluminum nitride layer (Suh: 108, Fig. 7), and the first AlGaN layer (Mishra: 28, Fig. 1B) of Mishra as modified by Suh are located above the buffer layer (Mishra: 12, Fig. 3B).
Regarding claim 12, Mishra discloses the first AlGaN layer (28, Fig. 3B) ([0032]) may have a thickness of between 2 nm and 6 nm ([0033]) but Mishra does not disclose the stoichiometry is specifically Al0.10Ga0.90N to Al0.30Ga0.70N. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select a first AlGaN layer stoichiometry of Al0.10Ga0.90N to Al0.30Ga0.70N and thickness between 1 nm and 5 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 13, Suh discloses the indium aluminum nitride layer (108, Fig. 7), with an implicit thickness, ([0027]-[0029]) has a stoichiometry of In0.18Al0.82N ([0030]) but does not disclose its thickness is 3.5 nm to 4.5 nm. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select an indium aluminum nitride layer thickness of 3.5 nm to 4.5 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 14, Mishra discloses the cap layer has a general formula of AlGaN with an implicit thickness ([0036]) but does not disclose its stoichiometry is specifically Al0.05Ga0.95N to Al0.30Ga0.70N and its thickness is 4 nm to 20 nm. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select a cap layer stoichiometry of Al0.05Ga0.95N to Al0.30Ga0.70N and thickness of 4 nm to 20 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Allowable Subject Matter
Claims 15-20 are allowed.
Claims 8-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1-7, 12-14, and 21-22 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
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/REEMA PATEL/Primary Examiner, Art Unit 2812 11/20/2025
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