Tech Center 2800 • Art Units: 2811 2812
This examiner grants 89% of resolved cases
Reema Patel is an examiner in Tech Center 2800 and Art Unit 2811. She has a high volume of 1136 resolved cases, providing a strong statistical foundation for her prosecution profile. Her allowance rate is 88.8%, which suggests that a significant majority of applications she reviews result in a patent grant. This high rate indicates a relatively favorable environment for applicants in her art unit.
The median days to allowance for Patel is 759, which is a useful benchmark for predicting the duration of the prosecution process. Additionally, the data shows an interview lift of 6.4%. This positive lift suggests that conducting an interview with the examiner is associated with an increased probability of securing an allowance. Practitioners should consider requesting an interview to resolve potential issues, as it has historically provided a benefit. With 1136 cases, the 88.8% allowance rate and 759 days to allowance represent a consistent and efficient examination history. This large data set ensures reliable metrics.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18777300 | IMAGE SENSOR WITH VARYING GRID WIDTH | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18751384 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE | Non-Final OA | Samsung Electronics Co., Ltd. |
| 18428264 | VERTICAL SEMICONDUCTOR DEVICES | Non-Final OA | Samsung Electronics Co., Ltd. |
| 18647178 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE DISPLAY DEVICE | Non-Final OA | Samsung Display Co., LTD. |
| 18443311 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF | Non-Final OA | Samsung Display Co., Ltd. |
| 18372990 | DISPLAY APPARATUS | Non-Final OA | Samsung Display Co., LTD. |
| 18638329 | CONDUCTIVE PASTE VSS SHORTING FOR GROUND BUMPS | Non-Final OA | QUALCOMM Incorporated |
| 18668042 | MULTI-HEIGHT & MULTI-WIDTH INTERCONNECT LINE METALLIZATION FOR INTEGRATED CIRCUIT STRUCTURES | Non-Final OA | Intel Corporation |
| 18381887 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING BOTTOM-UP OXIDATION APPROACH | Non-Final OA | Intel Corporation |
| 18292893 | PIXEL ASSEMBLY AND DISPLAY DEVICE | Non-Final OA | KYOCERA Corporation |
| 18696972 | COMPONENT WITH A PLURALITY OF SEMICONDUCTOR CHIPS | Non-Final OA | ams-OSRAM International GmbH |
| 18110330 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME | Final Rejection | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
| 18620133 | METHODOLOGY FOR INCREASE OF BRIGHTNESS OF LIGHT PRODUCED BY A NANOSCALE SEMICONDUCTOR-BASED HETEROSTRUCTURE | Non-Final OA | UNIVERSITY OF SOUTH FLORIDA |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy