DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 04/04/2025 has been entered. Claims 1-19 remain pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “at least one semi-stochastic neuron with an input domain divided into regions of stochastic and deterministic behavior”. The specification at no point describes what an input domain is and how the input domain is divided into regions of stochastic and deterministic behavior. The specification just discloses “Deterministic behavior—We say that the neuron is at equilibrium if all its inputs and output are in agreement (the same). At equilibrium, the neuron output remains constant in time (deterministic). Stochastic behavior—In the out-of-equilibrium situations, the neuron output changes stochastically. In this way, the neurons explore their phase space until the solution (corresponding to the circuit equilibrium) is found” ([0055]-[0056]). Therefore, the specification does not provide a disclosure of sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention including how the inventor intended for the disclosed computing circuit to perform all of the claimed functions. For the purpose of a prior art search, Examiner obliged to give the terms or phrases their broadest interpretation definition awarded by one of an ordinary skill in the art unless applicant has provided some indication of the definition of the claimed terms or phrases. Therefore, examiner interprets a Boolean-neural hybrid computing circuit comprising: at least one invertible logic gate and at least one semi-stochastic neuron.
Claim 2 recites “at least one standard logic gate from a direct calculation circuit”. The specification at no point discloses a standard logic gate or a direct calculation circuit. The specification discloses in Boolean-neural hybrids, the original logic gates representing the direct calculation are “loaded” with semi-stochastic neurons and feedback circuitry and FIG. 2 presents a conventional logic circuit that implements the direct calculation ([0045]). Therefore, the specification does not provide a disclosure of sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention including how the inventor intended for the disclosed computing circuit to comprise and perform all of the claimed functions. For the purpose of a prior art search, Examiner obliged to give the terms or phrases their broadest interpretation definition awarded by one of an ordinary skill in the art unless applicant has provided some indication of the definition of the claimed terms or phrases. Therefore, examiner interprets “at least one logic gate”.
Claim 8 recites “comprising feedback circuitry based on three-state signals “0”, “1”, “0 or 1” and disclosed tables of inverse operations”. The specification at no point discloses any feedback circuitry based on three-state signals “0”, “1”, “0 or 1” and disclosed tables of inverse operations. Therefore, the specification does not provide a disclosure of sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention including how the inventor intended for the disclosed computing circuit to comprise and perform all of the claimed functions. For the purpose of a prior art search, Examiner obliged to give the terms or phrases their broadest interpretation definition awarded by one of an ordinary skill in the art unless applicant has provided some indication of the definition of the claimed terms or phrases. Therefore, examiner interprets “comprising feedback circuitry”.
Claim 10 recites “A method of forming a Boolean-neural hybrid computing circuit”, “forming at least one invertible logic gate”, “forming at least one semi-stochastic neuron”. The specification at no point describes what “forming” means. Additionally, the specification at no point describes how the invertible logic gate that operates in reverse and how input data are applied to at least one output pin and a result is read from the input and the specification at no point describes what an input domain is and how the input domain is divided into regions of stochastic and deterministic behavior as similar issue addressed for claim 1 above. Therefore, the specification does not provide a disclosure of sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention including how the inventor intended for the disclosed computing circuit to perform all of the claimed functions. For the purpose of a prior art search, Examiner obliged to give the terms or phrases their broadest interpretation definition awarded by one of an ordinary skill in the art unless applicant has provided some indication of the definition of the claimed terms or phrases. Therefore, examiner interprets a Boolean-neural hybrid computing circuit forming at least one invertible logic gate and at least one semi-stochastic neuron.
Claim 11 recites “comprising at least one direct calculation logic gate”. The specification at no point discloses a direct calculation logic gate. The specification discloses in Boolean-neural hybrids, the original logic gates representing the direct calculation are “loaded” with semi-stochastic neurons and feedback circuitry and FIG. 2 presents a conventional logic circuit that implements the direct calculation ([0045]). Therefore, the specification does not provide a disclosure of sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention including how the inventor intended for the disclosed computing circuit to comprise and perform all of the claimed functions. For the purpose of a prior art search, Examiner obliged to give the terms or phrases their broadest interpretation definition awarded by one of an ordinary skill in the art unless applicant has provided some indication of the definition of the claimed terms or phrases. Therefore, examiner interprets “comprising at least one logic gate”.
Claims 3-7, 9 and 12-19 are rejected as being dependent upon the rejected base claims 1 and 10.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-7 and 14-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 5 and 14 recite “the at least one semi-stochastic neuron searches for a problem solution stochastically and stores the problem solution deterministically when found”. These limitations are indefinite because it’s unclear to Examiner what a problem is, how the semi-stochastic neuron searches for a solution for the problem and where it stores the problem solution. The specification mentions in the Background that in memcomputing, the problem solution is found with the help of self-organizing logic gates, which for a given output self-organize to provide the solution input. For the purpose of a prior art search, self-organizing logic gates and circuits can provide solution for complex problems.
Claims 6 and 15 recite the equations without reciting the definition for each element in the equations. These limitations are indefinite because it’s unclear to Examiner how the semi-stochastic neuron is described from the equation. Given the broadest reasonable interpretation of the claim elements in light of the specification, the output of the semi-stochastic binary neuron is calculated based on a function in term of a combined input.
Claims 7 and 16 recite the equations without reciting the definition for each element in the equations. These limitations are indefinite because it’s unclear to Examiner how the semi-stochastic neuron combined input V is calculated. Given the broadest reasonable interpretation of the claim elements in light of the specification, the semi-stochastic neuron combined input V is calculated based on the summation of some input in the presence of at least one input.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8-11 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Alvarez-Icaza et al. (hereinafter Alvarez-Icaza), US 20150039546 A1, in view of Smithson et al. (hereinafter Smithson), "Efficient CMOS Invertible Logic Using Stochastic Computing," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 6, pp. 2263-2274, June 2019, doi: 10.1109/TCSI.2018.2889732, further in view of Psarrou, “Computational properties of cerebellar nucleus neurons: Effects of stochastic ion channel gating and input location”, (2018), https://uhra.herts.ac.uk/id/eprint/16984.
Regarding independent claim 1, Alvarez-Icaza teaches a Boolean-neural hybrid computing circuit (Fig. 5; [0075] FIG. 5 illustrates an example neurosynaptic core circuit 650) comprising:
at least one logic gate (Fig. 3, 265; [0043] The AND unit 265 is configured to receive input (e.g., an incoming neuronal firing event targeting the neuron 11).);
at least one semi-stochastic neuron with an input domain divided into regions of stochastic and deterministic behavior ([0026] FIG. 1 illustrates an example dual stochastic and deterministic digital neuron 11. The neuron 11 comprises a computation logic circuit 100. The circuit 100 receives and processes incoming neuronal firing events (e.g., incoming spiking events/packets) targeting the neuron 11; [0027] The circuit 100 comprises an integrator unit (i.e., integrator device) 150 for integrating synaptic input. The circuit 100 further comprises a synaptic unit (i.e., synaptic device) 250 configured to receive incoming neuronal firing events targeting the neuron 11. For at least one incoming neuronal firing event received, the synaptic unit 250 is further configured to provide the integrator unit 150 with a corresponding synaptic input. As described in detail later herein, a synaptic input may be a deterministic value or a stochastic value);
wherein the at least one semi-stochastic neuron is formed by either digital or analog electronics or a combination of digital and analog electronics ([0025] In one embodiment, a neuromorphic system comprises a system that implements neuron models, synaptic models, neural algorithms, and/or synaptic algorithms. In one embodiment, a neuromorphic system comprises software components and/or hardware components, such as digital hardware, analog hardware or a combination of analog and digital hardware (i.e., mixed-mode)) and comprises at least one artificial neuron exhibiting either stochastic or deterministic behavior dependent on the input to the at least one semi-stochastic neuron ([0087] FIG. 9 illustrates a flowchart of an example process 850 for generating a threshold value for a dual stochastic and deterministic neuron, in accordance with an embodiment of the invention. In process block 851, draw a pseudo-random value if a threshold value generated is stochastic. In process block 852, bitwise AND a mask value and the drawn pseudo-random value to generate an intermediate pseudo-random value. In process block 853, add the intermediate pseudo-random value and a stored threshold value to generate a deterministic or stochastic threshold value; [0088] FIG. 10 illustrates a flowchart of an example process 900 for integrating a leak/synaptic weight value in a dual stochastic and deterministic neuron, in accordance with an embodiment of the invention. In process block 901, determine if the neuron is operating in stochastic mode. If the neuron is operating in deterministic mode (i.e., not stochastic mode), proceed to process block 902 where a stored leak/synaptic weight value for the neuron is integrated into a membrane potential variable of the neuron);
Alvarez-Icaza does not explicitly disclose at least one invertible logic gate including feedback circuitry that operates in reverse wherein input data are applied to at least one output pin and a result is read from an input.
However, in the same field of endeavor, Smithson teaches at least one invertible logic gate including feedback circuitry that operates in reverse wherein input data are applied to at least one output pin and a result is read from the input (Fig. 1; page 2263, Illustrated in Fig. 1 for the aforementioned case of an invertible AND gate operating in reverse; Fig. 5; page 2266, every node in the graph is fully connected to all others through bidirectional links; Fig. 6; page 2266-2267, as an illustrative example, consider the invertible AND function of Fig. 6. There are three nodes, those denoted A and B refer to binary inputs and Y, the output. In invertible logic, we define such nodes as being bidirectionally connected; what is traditionally considered an input may behave as such, and can also be used as output terminals … If one or more of the nodes is clamped to a certain value, the other nodes will fluctuate among all the valid states in which the clamped values are present. For instance, when Y is clamped to “0”, the valid states of (A, B) are (0, 0), (0, 1), and (1, 0), since those are the input combinations which cause the output of an AND-gate to be equal to “0”, as shown in Fig. 6a. Likewise, when Y is clamped to “1”, the only valid state of (A, B) is (1, 1) as shown in Fig. 6b. The tendency of the system to fluctuate between valid states given a clamped output makes it possible to operate the gate in reverse to compute the original inputs).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of a family of invertible logic circuits based on stochastic computing circuits as the underlying processing elements which can be easily manufactured in standard Complimentary Metal-Oxide-Semiconductor (CMOS) processes as suggested in Smithson into Alvarez-Icaza’s system because both of these systems are addressing Stochastic Computing. This modification would have been motivated by the desire to reduce hardware costs through re-using invertible logic circuits for multiple purposes (Smithson, page 2263).
The combination of Alvarez-Icaza and Smithson does not explicitly disclose wherein the input domain is deterministic when the at least one semi-stochastic neuron is at equilibrium and the input and an output are the same and an at least one semi-stochastic neuron output remains constant in time; and wherein the input domain is stochastic when the input and output are not the same and the at least one semi-stochastic neuron output changes stochastically until a solution corresponding to a circuit equilibrium is found.
However, in the same field of endeavor, Psarrou teaches
wherein the input domain is deterministic when the at least one semi-stochastic neuron is at equilibrium and the input and an output are the same and an at least one semi-stochastic neuron output remains constant in time (page 66 “In the deterministic channel model, the equilibrium is achieved when the membrane potential stays at the exact same level of depolarization until a new event (for example, an external stimulus) is presented to the system”); and
wherein the input domain is stochastic when the input and output are not the same and the at least one semi-stochastic neuron output changes stochastically until a solution corresponding to a circuit equilibrium is found (page 66 “In the stochastic channel model, the depolarization level of the membrane alters through time as a result of the probabilistic channel gating and consequently electrical noise, expressed as fluctuations around the equilibrium point, is introduced. However, the stochastic temporal mean of the voltage (or current) gives an estimation of the average equilibrium point over a time window. Alternatively, an equilibrium value, equivalent to the stochastic temporal mean, could be reached with a very large number of channels, because the resulting fluctuations would even out”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of an equilibrium state in the deterministic channel model and the stochastic channel model as suggested in Psarrou into Alvarez-Icaza and Smithson’s system because both of these systems are addressing stochastic and deterministic models. This modification would have been motivated by the desire to contribute to an understanding of the arithmetic operations performed by neurons in the cerebellar nuclei (Psarrou, page iv, Abstract).
Regarding dependent claim 2, the combination of Alvarez-Icaza, Smithson and Psarrou teaches all the limitations as set forth in the rejection of claim 1 that is incorporated. Smithson further teaches further comprising wherein the at least one invertible logic gate comprises:
at least one standard logic gate from a direct calculation circuit (Section V. INVERTIBLE LOGIC CIRCUITS, Boltzmann machine configurations for all basic gates (three terminal AND, NAND, OR, NOR, etc.) can be derived following the same steps as those to design the AND gate structure of Fig. 5); and
the feedback circuitry transfers information in a reverse direction (Fig. 5; page 2266, every node in the graph is fully connected to all others through bidirectional links).
Regarding dependent claim 8, the combination of Alvarez-Icaza, Smithson and Psarrou teaches all the limitations as set forth in the rejection of claim 1 that is incorporated. Smithson further teaches further comprising feedback circuitry based on three-state signals “0”, “1”, “0 or 1” and disclosed tables of inverse operations (Fig. 6, page 2265-2266, Section IV. PROPOSED HARDWARE MODEL, A. Boltzmann Machine Logic Representation).
Regarding dependent claim 9, the combination of Alvarez-Icaza, Smithson and Psarrou teaches all the limitations as set forth in the rejection of claim 1 that is incorporated. Alvarez-Icaza further teaches further comprising a flip-flop-based design of semi-stochastic neurons (Fig. 1, 150; [0029] The integrator unit 150 comprises a multiplexer 160, an adder 170, and a register 180. The register 180 maintains a temporary variable representing the membrane potential variable V of the neuron 11. The multiplexer 160 selects a parameter to integrate into the membrane potential variable V. Specifically, when the circuit 100 is processing an incoming neuronal firing event, the multiplexer 160 selects a corresponding synaptic input to integrate into the membrane potential variable V. When the circuit 100 has processed all incoming neuronal firing events received during a time step, the multiplexer 160 selects an output leak weight value Lk.sub.OUT to integrate into the membrane potential variable V).
Regarding independent claim 10, it is a method claim that corresponding to the computing circuit of claim 1. Therefore, it is rejected for the same reason as claim 1 above.
Regarding dependent claim 11, it is a method claim that corresponding to the computing circuit of claim 2. Therefore, it is rejected for the same reason as claim 2 above.
Regarding dependent claim 17, the combination of Alvarez-Icaza, Smithson and Psarrou teaches all the limitations as set forth in the rejection of claim 10 that is incorporated. Alvarez-Icaza further teaches a software simulation of the Boolean-neural hybrid computing circuit ([0024] The term digital neuron as used herein represents an framework configured to simulate a biological neuron. An digital neuron creates connections between processing elements that are roughly functionally equivalent to neurons of a biological brain. As such, a neuromorphic and synaptronic computation comprising digital neurons, according to embodiments of the invention, may include various electronic circuits that are modeled on biological neurons. Further, a neuromorphic and synaptronic computation comprising digital neurons, according to embodiments of the invention, may include various processing elements (including computer simulations) that are modeled on biological neurons. Although certain illustrative embodiments of the invention are described herein using digital neurons comprising digital circuits, the present invention is not limited to digital circuits. A neuromorphic and synaptronic computation, according to embodiments of the invention, can be implemented as a neuromorphic and synaptronic framework comprising circuitry and additionally as a computer simulation).
Regarding dependent claim 18, the combination of Alvarez-Icaza, Smithson and Psarrou teaches all the limitations as set forth in the rejection of claim 10 that is incorporated. Alvarez-Icaza further teaches further comprising a hardware implementation of the Boolean-neural hybrid computing circuit ([0024] embodiments of the invention can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment containing both hardware and software elements; [0025] In one embodiment, a neuromorphic system comprises software components and/or hardware components, such as digital hardware, analog hardware or a combination of analog and digital hardware (i.e., mixed-mode)).
Regarding dependent claim 19, it is a method claim that corresponding to the computing circuit of claim 9. Therefore, it is rejected for the same reason as claim 9 above.
Claims 3-5 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Alvarez-Icaza, in view of Smithson, in view of Psarrou as applied in claims 1 and 10, further in view of Di Ventra et al. (hereinafter Di Ventra), US 20180144239 A1.
Regarding dependent claim 3, the combination of Alvarez-Icaza, Smithson and Psarrou teaches all the limitations as set forth in the rejection of claim 1 that is incorporated. The combination of Alvarez-Icaza, Smithson and Psarrou does not explicitly disclose further comprising at least one invertible logic gate that supports both direct and inverse calculations.
However, in the same field of endeavor, Di Ventra teaches comprising at least one invertible logic gate that supports both direct and inverse calculations ([0046] Direct and Inverse Protocols; [0047] We further define two ways (protocols) to find a solution of such problems. The first one can be implemented within the Turing machine paradigm through standard Boolean circuits. The second one can only be implemented with DMMs; [0048]-[0050] define the Direct Protocol (DP); [0051] An Inverse Protocol (IP) is that which finds a solution of a given CB problem by encoding the Boolean system f into a machine capable of accepting as input b, and giving back as output y, solution of f(y)=b. The IP can be considered an “inversion” of f using special purpose machines).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of memcomputing architectures that provide forward logic like a traditional logic chip, and also provide reverse logic to solve complex problems using the forward and reverse logic at the same time as suggested in Di Ventra into Alvarez-Icaza, Smithson and Psarrou’s system because both of these systems are addressing logic gate to speeds up the solutions of the NP problems. This modification would have been motivated by the desire to provide a fast and less costly solution (Di Ventra, [0003]).
Regarding dependent claim 4, the combination of Alvarez-Icaza, Smithson and Psarrou teaches all the limitations as set forth in the rejection of claim 1 that is incorporated. The combination of Alvarez-Icaza, Smithson and Psarrou does not explicitly disclose wherein at least one invertible logic gate is based on two- or three-state logic and/or emerging electronic devices.
However, in the same field of endeavor, Di Ventra teaches wherein at least one invertible logic gate is based on two- or three-state logic and/or emerging electronic devices (Figs. 1A-1B; [0075] The DMM includes a plurality of memprocessors 10 and a control unit 14. The control unit 14 maps the topology of connections from an input state to an output state. The memprocessors 10 are two-state interconnected elements that change their state according to both the external signal fed by the Control Unit 14 and the signals from the other memprocessors through their connections. δ is the composition of all transition functions involved in the computation).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of digital memcomputing machines (DMM) memprocessors which are two-state interconnected elements as suggested in Di Ventra into Alvarez-Icaza, Smithson and Psarrou’s system because both of these systems are addressing logic gate to speeds up the solutions of the hard problems. This modification would have been motivated by the desire to provide a fast and less costly solution (Di Ventra, [0003]).
Regarding dependent claim 5, the combination of Alvarez-Icaza, Smithson and Psarrou teaches all the limitations as set forth in the rejection of claim 1 that is incorporated. The combination of Alvarez-Icaza and Smithson does not explicitly disclose wherein the at least one semi-stochastic neuron searches for a problem solution stochastically and stores the problem solution deterministically when found.
However, in the same field of endeavor, Di Ventra teaches wherein the at least one semi-stochastic neuron searches for a problem solution stochastically and stores the problem solution deterministically when found ([0025] An embodiment of the invention is a self-organizing logic gate and circuit. Preferred embodiments are memcomputing architectures that provide forward logic (input to output) like a traditional logic chip, and also provide reverse (output to input) logic. The use of SO logic speeds up the solutions of the NP problems; [0027] Preferred embodiments provide self-organizing logic gates (SOLGs). Preferred embodiments provide a complete set of logic gates. Preferred SOLG of the invention include memristors and standard transistors, and others include transistor circuits that form memristor devices by providing memristive behavior. SOLG of the invention include memristors, emulators of memristors, and standard transistors configured to provide memristive behavior. The gates of the invention are able to function as regular logic gates by solving for the input bits, but importantly, the gates of the invention can also work reversibly by fixing the output bit and finding the input bits that give rise to that output. The gates of the invention self-organize themselves into the final solution. Self-organizing logic circuits of the invention employ SOLGs to enable many operations that standard logic circuits cannot perform; [0031] Preferred embodiments also provide self-organizing logic circuits (SOLC). A group of SOLGs is combined to provide a preferred SOLC. An example of self-organizing logic circuit is formed by a network of self-organizing AND gates. The external inputs are sent to some nodes related to the computational task required. The self-organizing circuit organizes itself by finding a stable configuration that satisfies the logic proposition and then the solution is read at the output nodes; [0036] The SOLGs form a complete basis set of Boolean algebra, so any Boolean function can be expressed as a combination of self-organizing AND, OR and NOT and any other gate. Self-organizing logic gates of the invention are capable of solving standard computational problems as well as computational problems with polynomial resources (space, time and energy) problems that, using normal Boolean logic, are solved with exponential resources).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of a self-organizing logic gate (SOLG) to solve complex problem as suggested in Di Ventra into Alvarez-Icaza, Smithson and Psarrou’s system because both of these systems are addressing logic gate to speeds up the solutions of the hard problems. This modification would have been motivated by the desire to provide a fast and less costly solution (Di Ventra, [0003]).
Regarding dependent claim 12, it is a method claim that corresponding to the computing circuit of claim 3. Therefore, it is rejected for the same reason as claim 3 above.
Regarding dependent claim 13, it is a method claim that corresponding to the computing circuit of claim 4. Therefore, it is rejected for the same reason as claim 4 above.
Regarding dependent claim 14, it is a method claim that corresponding to the computing circuit of claim 5. Therefore, it is rejected for the same reason as claim 5 above.
Claims 6-7 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Alvarez-Icaza, in view of Smithson, in view of Psarrou as applied in claims 1 and 10, further in view of Pervaiz et al. (hereinafter Pervaiz), "Probabilistic Computing with Binary Stochastic Neurons," 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), Nashville, TN, USA, 2019, pp. 1-6, doi: 10.1109/BCICTS45179.2019.8972719.
Regarding dependent claim 6, the combination of Alvarez-Icaza, Smithson and Psarrou teaches all the limitations as set forth in the rejection of claim 1 that is incorporated. The combination of Alvarez-Icaza, Smithson and Psarrou does not explicitly disclose wherein the semi-stochastic neuron is described by equation:
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70
251
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However, in the same field of endeavor, Pervaiz teaches wherein the semi-stochastic neuron is described by equation:
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251
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(pages 1-2, Section II. IDEAL DESCRIPTION OF P-BITS AND P-COMPUTERS, equation (1)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of the behavior of a p-bit which resembles that of a binary stochastic neuron as suggested in Pervaiz into Alvarez-Icaza, Smithson and Psarrou’s system because both of these systems are addressing probabilistic computing with Binary Stochastic Neurons. This modification would have been motivated by the desire to build asynchronously operating rudimentary pcomputers to explore potential difficulties that could arise in scaled nanodevice based p-computers (Pervaiz, page 1, Abstract).
Regarding dependent claim 7, the combination of Alvarez-Icaza, Smithson and Psarrou teaches all the limitations as set forth in the rejection of claim 1 that is incorporated. The combination of Alvarez-Icaza, Smithson and Psarrou does not explicitly disclose wherein the semi-stochastic neuron combined input Vis calculated by equation:
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228
726
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However, in the same field of endeavor, Pervaiz teaches wherein the semi-stochastic neuron combined input Vis calculated by equation:
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306
975
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(pages 1-2, Section II. IDEAL DESCRIPTION OF P-BITS AND P-COMPUTERS, equation (2)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of the behavior of a p-bit which resembles that of a binary stochastic neuron as suggested in Pervaiz into Alvarez-Icaza, Smithson and Psarrou’s system because both of these systems are addressing probabilistic computing with Binary Stochastic Neurons. This modification would have been motivated by the desire to build asynchronously operating rudimentary pcomputers to explore potential difficulties that could arise in scaled nanodevice based p-computers (Pervaiz, page 1, Abstract).
Regarding dependent claim 15, it is a method claim that corresponding to the computing circuit of claim 6. Therefore, it is rejected for the same reason as claim 6 above.
Regarding dependent claim 16, it is a method claim that corresponding to the computing circuit of claim 7. Therefore, it is rejected for the same reason as claim 7 above.
Response to Arguments
Applicant's arguments filed 04/04/2025 have been fully considered.
(1) Amended claims include additional elements that are sufficient to amount to significantly more. Rejections under 35 U.S.C 101 to claims 10-19 for being directed to judicial except without significantly more are withdrawn.
(2) The 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph rejections to Claims 1-4, 8-10, 11-13 and 17-19 are respectfully withdrawn in response to Applicant's amendment to these claims.
(3) Applicant’s prior art arguments with respect to the pending claims have been considered but they are moot in view of the new ground(s) of rejections presented above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant is required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action.
Mansinghka et al. (US 20090228238 A1) discloses circuits that solve stochastic problems and techniques for operating them.
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMY P HOANG whose telephone number is (469)295-9134. The examiner can normally be reached M-TH 8:30-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JENNIFER WELCH can be reached at 571-272-7212. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AMY P HOANG/Examiner, Art Unit 2143
/JENNIFER N WELCH/Supervisory Patent Examiner, Art Unit 2143
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