The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 7 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation of “wherein the in-situ insulating layer is a laminated structure, which comprises, from bottom to top, a SiN layer and a SiAIN layer, a SiAIN layer and a SiN layer, or a SiN layer, a SiAIN layer and a SiN layer”, as recited in claim 1, is unclear as to how a laminated structure can comprise a SiN layer. It is further unclear what is meant by the phrase “a SiAIN layer and a SiN layer, or a SiN layer”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7 and 15, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Kai (CN104051522, provided as IDS on 03/16/2021) in view of Ogimoto (2013/020457), Kikkawa et al. (2009/0173951), Cheng (2015/0144955) and Then et al. (2015/0171205).Regarding claim 1, Kai teaches in figure 1 and related text semiconductor structure, comprising:
a semiconductor substrate 1, a heterojunction 23/24, and an in-situ insulating layer 4, which are arranged from bottom to top, wherein the in-situ insulating layer 4 comprises at least one of SiN or SiAlN and is in direct contact with the heterojunction 23/24;
a groove passing through the in-situ insulating layer 4 to the heterojunction 23/24;
a transition layer 51, disposed in the groove and on the in-situ insulating layer, wherein the transition layer 52 comprises semiconductor Nickel oxide;
a P-type semiconductor layer 52, disposed on the transition layer, wherein the P-type semiconductor layer does not fully fill the groove,
wherein the P-type semiconductor layer comprises Nickel oxide; and
a gate 53, disposed on the P-type semiconductor layer;
wherein the transition layer is configured to prevent a selective growth of the P- type semiconductor layer on the in-situ insulating layer (inherently therein), and prevent atoms in the in-situ insulating layer from being diffused into the P-type semiconductor layer.
Kai does not teach that wherein the in-situ insulating layer is a laminated structure, comprises, from bottom to top, a SiN layer and a SiAIN layer, a SiAIN layer and a SiN llayer, or a
SiN layer, a SiAIN layer and a SiN layer, and
wherein the transition layer is a laminated structure, which comprises at least two layers of an AIN layer, a SiAIN layer, and an AlGaN layer, and
an upper surface of the in-situ insulating layer is completely covered by the transition layer, and
wherein an ohmic contact is formed between the gate and the P-type semiconductor layer.
Cheng teaches in figure 5e and related text an in-situ insulating layer is a laminated structure, comprises, from bottom to top, a SiN layer and a SiAIN layer, a SiAIN layer and a SiN llayer, or a SiN layer, a SiAIN layer and a SiN layer.
Kikkawa et al. teach in related related text (see e.g. paragraph [069]) using a laminated structure, which comprises AlN/AlGaN instead of a single layer of AlN.
Ogimto teaches in figure 2 and related text forming an in-situ insulating layer 31A completely covered by a transition layer comprising 22A.
Then et al. teach in figure 3F and related text an ohmic contact 114 is formed between contact 114 and the P-type semiconductor layer 112.
Ogimoto, Kikkawa et al., Cheng, Then et al. and Kai are analogous art because they are directed to semiconductor devices comprising heterojunctions and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kai because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the in-situ insulating layer is a laminated structure,comprises, from bottom to top, a SiN layer and a SiAIN layer, a SiAIN layer and a SiN llayer, or a SiN layer, a SiAIN layer and a SiN layer, as taught by Cheng, to form the transition layer as a laminated structure, which comprises at least two layers of an AIN layer, a SiAIN layer, and an AlGaN layer, as taught by Kikkawa et al., to have an upper surface of the in-situ insulating layer completely covered by the transition layer, as taught by Ogimoto, and to form an ohmic contact between the gate and the P-type semiconductor layer, as taught by Then et al., in prior art’s device in order to improve the device characteristics by using conventional materials, in order to provide better protection to the device, and in order to simplify the processing steps of making the device, respectively.
Regarding the claimed limitations of using specific materials, it is noted that substitution of materials is not patentable even when the substitution is new and useful. Safetran Systems Corp. v. Federal Sign & Signal Corp. (DC NIII, 1981) 215 USPQ 979.
It is further held that it is within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 2, Kai teaches in figure 1 and related text a source 31 and a drain 32 disposed respectively on either side of the gate.
Regarding claims 3 and 7, Kai teaches in figure 1 and related text that the heterojunction comprises, from bottom to top, a channel layer 24 and a barrier layer 23 and wherein both the source and the drain contact the channel layer or the barrier layer. Kai does not teach that a thickness of the barrier layer ranges from 1 nm to 15 nm and wherein both the source and the drain contact the channel layer or the barrier layer.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a thickness of the barrier layer ranges from 1 nm to 15 nm and wherein both the source and the drain contact the channel layer or the barrier layer, in Kai’s device in order to use the device in application which requires specific current flow and in order to optimize the device characteristics, respectively.
Regarding claims 4 and 15, Kai teaches in figure 1 and related text that the heterojunction comprises a GaN-based material.
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because of the new ground of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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O.N. /ORI NADAV/
9/20/2025 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
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