DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3-14 and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over (US 2010/0078637 A1; hereinafter, “Matsumoto”, which of record) in view of Boer et al. (US 2008/0121442 A1; hereinafter, “Boer”, which is of record).
Regarding claim 1:
Matsumoto discloses (in Fig. 3) an array substrate, comprising:
a thin film transistor layer 41/42/82 comprising a first thin film transistor 163/81/82 [0033]; and
an infrared detection element 151 [0032-0033]) disposed on a first side (top side in Fig. 3) of the thin film transistor layer, wherein the infrared detection element 151 comprises a first electrode 170 [0037], a light-absorbing layer 151c [0038], and a second electrode 171 [0038] sequentially stacked on the first side of the thin film transistor layer, wherein the infrared detection element 151 is electrically connected to the first thin film transistor 163/81/82, and wherein a material of the light-absorbing layer 151c is microcrystalline silicon [0039];
Matsumoto is silent as to a thickness of the light-absorbing layer; however, it is noted a band gap of microcrystalline silicon (which is the material of the light-absorbing layer in Matsumoto) is around 1.12 eV.
Boer teaches it was well known in the art to incorporate a microcrystalline silicon layer with a thickness of 300 nm into an infrared sensor (e.g., see tables in [0057-0058]).
It would have been obvious to one of ordinary skill in the art to specifically incorporate a thickness of 300 nm for Matsumoto’s light-absorbing layer, because Boer shows/teaches such a thickness is well-suited for a device similar to that in Matsumoto. In other words, since Matsumoto is silent as to a thickness, it would have been obvious to incorporate any well-known thickness, such as that shown/taught by Boer.
Regarding claims 4-14 and 15-20, Matsumoto discloses:
re claim 4, the array substrate according to claim 1, wherein an orthographic projection of the infrared detection element 151 (Fig. 3) on the thin film transistor layer is positioned within a boundary of the first thin film transistor 163/81/82 (e.g., an orthographic projection of the right side edge of “151” is positioned within a boundary of transistor 163/81/82);
re claim 5, the array substrate of claim 1, wherein the first electrode 170 (Fig. 3) is electrically connected to a source/drain 1d/82 [0045] of the first thin film transistor;
re claim 6, the array substrate according to claim 1, wherein the infrared
detection element 151 (Fig. 3) further comprises a first semiconductor layer 151e [0038], and the first semiconductor layer 151e (Fig. 3) is positioned between the first electrode 170 and the light-absorbing layer 151c;
re claim 7, the array substrate according to claim 1, wherein the infrared detection element 151 (Fig. 3) further comprises a second semiconductor layer 151a [0038], and the second semiconductor layer 151a is positioned between the light-absorbing layer 151c and the second electrode 171;
re claim 8, the substrate according to claim 1, wherein the infrared detection element 151 further comprises a first semiconductor layer 151e (Fig. 3) and a second semiconductor layer 151a, the first semiconductor layer 151e is positioned between the first electrode 170 and the light-absorbing layer 151c, and the second semiconductor layer 151a is positioned between the light-absorbing layer 151c and the second electrode 171;
re claim 9, initially with regard to this claim, claims 1 and 8 will be remapped as:
re claim 1, a thin film transistor layer 41/42/82 comprising a first thin film transistor 163/81/82 [0033]; and
an infrared detection element 151 [0032-0033]) disposed on a first side (top side in Fig. 3) of the thin film transistor layer, wherein the infrared detection element 151 comprises a first electrode 171 [0038], a light-absorbing layer 151c [0038], and a second electrode 170 [0037] sequentially stacked on the first side of the thin film transistor layer, wherein the infrared detection element 151 is electrically connected to the first thin film transistor 163/81/82, and wherein a material of the light-absorbing layer 151c is microcrystalline silicon [0039];
re claim 8, the substrate according to claim 1, wherein the infrared detection element 151 further comprises a first semiconductor layer 151a (Fig. 3) and a second semiconductor layer 151e, the first semiconductor layer 151a is positioned between the first electrode 171 and the light-absorbing layer 151c, and the second semiconductor layer 151e is positioned between the light-absorbing layer 151c and the second electrode 170; and
the array substrate according to claim 8, wherein a material of the first semiconductor layer 151a is n-type amorphous silicon [0009], and a material of the second semiconductor layer 151e is p-type amorphous silicon [0042];
re claim 10, initially with regard to this claim, claims 1 and 8 will be remapped as:
re claim 1, a thin film transistor layer 41/42/82 (in Fig. 6) comprising a first thin film transistor 163/81/82 [0033]; and
an infrared detection element 151X (Fig. 6 and [0049]) disposed on a first side (top side in Fig. 4) of the thin film transistor layer, wherein the infrared detection element 151C comprises a first electrode 171, a light-absorbing layer 151c [0049], and a second electrode 170 sequentially stacked on the first side of the thin film transistor layer, wherein the infrared detection element 151X is electrically connected to the first thin film transistor 163/81/82 (Fig. 6), and wherein a material of the light-absorbing layer 151c is microcrystalline silicon [0039];
re claim 8, the substrate according to claim 1, wherein the infrared detection element 151X further comprises a first semiconductor layer 151x1 (Fig. 6) and a second semiconductor layer 151x2, the first semiconductor layer 151x1 is positioned between the first electrode 171 and the light-absorbing layer 151c, and the second semiconductor layer 151x2 is positioned between the light-absorbing layer 151c and the second electrode 170; and
the array substrate according to claim 8, wherein a material of the first semiconductor layer 15x1 is n-type microcrystalline silicon [0050], and a material of the second semiconductor 15x2 layer is p-type microcrystalline silicon [0050];
re claim 11, the array substrate according to claim 1, wherein the array substrate further comprises a second thin film transistor and a pixel electrode electrically connected to the second thin film transistor, and the pixel electrode and the second electrode are positioned in a same layer (in Fig. 1, the array substrate comprises a plurality of unit areas 550, each of which includes a photosensor shown in Fig. 3; accordingly, a second thin film transistor and pixel electrode will be positioned in a same layer);
re claim 12, the array substrate according to claim 11, wherein a source/drain of the first thin film transistor and a source/drain of the second thin film transistor are positioned in a same layer of the array substrate, a gate of the first thin film transistor and a gate of the second thin film transistor are positioned in a same layer of the array substrate, and an active layer of the first thin film transistor and an active layer of the second thin film transistor are positioned in a same layer of the array substrate (in Fig. 1, the array substrate comprises a plurality of unit areas 550, each of which includes a photosensor shown in Fig. 3; accordingly, the source/drains, gates and active layers of the array of photosensors will be positions in a same layer); and
re claims 13 and 17-20, these claims are essentially drawn to a method of manufacturing an array substrate of claims 1, 4, 5, 8 and 9, wherein all pertinent limitations in the current claims are recited in claims 1, 4, 5, 8 and 9. Therefore, all limitations in the current claims are disclosed by Matsumoto as explained in detail with respect to claims 1, 4, 5, 8 and 9 hereinbefore.
Therefore, claims 4-14 and 15-20 are rendered obvious by Matsumoto (in view of Boer).
Regarding claims 3 and 16:
Boer teaches it was well known in the art to incorporate a microcrystalline silicon layer with a thickness of 300 nm into an infrared detector (e.g., see [0043] and tables in [0057-0058]).
It would have been obvious to one of ordinary skill in the art to specifically incorporate a thickness of 300 nm for Matsumoto’s light-absorbing layer, because Boer shows/teaches such a thickness is well-suited for a device similar to that in Matsumoto. In other words, since Matsumoto is silent as to a thickness, it would have been obvious to incorporate any well-known thickness, such as that shown/taught by Boer.
Regarding claim 14:
Boer teaches it was well known in the art to deposit/form a microcrystalline silicon layer by plasma enhanced chemical vapor deposition, PECVD, [0054].
It would have been obvious to one of ordinary skill in the art to form Matsumoto’s microcrystalline silicon using PECVD, because Boer shows/teaches PECVD was well known and suitable for forming a microcrystalline silicon layer. In other words, since Matsumoto is silent as to a deposition process, it would have been obvious to incorporate any well-known deposition process, such as that shown/taught by Boer.
Remarks
The objection to the title is withdrawn in view of the amendment.
Applicant’s remarks have been carefully reviewed and considered; however, they are not persuasive primarily because Matsumoto discloses the claimed invention except for explicitly disclosing any specific range(s) in thickness for the light-absorbing layer. Therefore, given Matsumoto, one of ordinary skill in the art would find it obvious to incorporate a thickness that was well known in the art for a similar device. Boer discloses a similar device (e.g., a photodiode based IR sensor, e.g., see [0014]) having a thickness falling within the claimed range is well suited; therefore, it would have been obvious for one of ordinary skill in the art to specifically incorporate a thickness as shown by Boer into Matsumoto’s device.
Regarding applicant’s remarks with regard to absence of intermediate layers, it is note the current claims recite an array “comprising”; accordingly, the current claims cannot exclude intermediate layers. Regarding applicant’s remarks that Boer’s infrared sensor is an entirely different device from that of Matsumoto, the examiner respectfully disagrees because, with respect to claims 1 and 13, Boer is cited only to show what was well-known in the art regarding a thickness for a microcrystalline silicon layer incorporated into a photosensor device.
Regarding claim 14, applicant asserts a specific combination of H2/SiH4, temperature range, and pressure range is non-trivial and Boer does not teach, suggest or render such a combination obvious. The examiner respectfully notes that, although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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