DETAILED ACTION
This Office Action is in response to the claims filed on October 19, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 8, 10, and 17-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lum et al. (US Pub. 2021/0364861 A1).
In re claim 1, Lum et al. shows (figs. 6, 8) a backlight module, wherein the backlight module comprises: a substrate (84) comprising at least two first bonding regions (each having P1, P2, P3, P4, etc); at least one first conductive pad (P3) in each of the first bonding regions of the substrate; at least two second conductive pads (P2, P4) disposed in each of the first bonding regions of the substrate; first wires (104-1) disposed on the substrate and each of which is connected to at least two of the first conductive pads (P3) in the first bonding regions; a second wire disposed (108-1) on the substrate and connected to two of the second conductive pads (P4) located in two of the first bonding regions respectively; and driver chips (82-1, 82-2) connected to the first conductive pad and the second conductive pads in each of the first bonding regions; wherein two of the second conductive pads connected to the second wire are located on the same side of each of the first wires (each pad P2 and P4 is located on the right side of the first wire 104-1).
In re claim 2, Lum et al. shows (figs. 6, 8) wherein the driver chips (82-1, 82-2) are disposed in each of the first bonding regions respectively, an orthographic projection (scene from the top view) of each of the driver chips on the substrate comprises a first parallel edge (left) and a second parallel edge (right) that are parallel to an extension direction (up/down 212) of each of the first wires, and the first parallel edge are opposite to the second parallel edge; the at least one first conductive pad (P3) in each of the first bonding regions is connected to at least one of the first wires (104-1) respectively; wherein at most two of the first conductive pads are disposed along the first parallel edge (left), and/or, at most two of the first conductive pads are disposed along the second parallel edge.
In re claim 3, Lum et al. shows (figs. 6, 8) wherein the substrate further comprises second bonding regions (in region 102), the backlight module further comprises: at least one third conductive pad (P1) disposed in each of the first bonding regions of the substrate, the at least one third conductive pad is connected to the driver chips; light emitting units (102) disposed in each of the second bonding regions of the substrate; and a third wire (not labeled, at P1 to 102), an end of the third wire is connected to the third conductive pad (P1), another end of the third wire is connected to an end of the light emitting units (102), and the third wire extends from a position on which the third conductive pad is located to a side of the second parallel edge away from the first parallel edge (extends diagonally towards the second parallel edge-right side); wherein each of the first wires is located on a side of the second parallel edge near the first parallel edge, and in each of the first bonding regions, the at least one third conductive pad is disposed on a side of each of the first wires near the second parallel edge (all components are in proximity and complete the structure).
In re claim 4, Lum et al. shows (figs. 6, 8) each of the first bonding regions, at least one of the second conductive pads connected to the second wire and at most one of the first conductive pad are disposed along the second parallel edge; and/or, in each of the first bonding regions (at 82-1), at least one of the second conductive pads (P2, p4) connected to the second wire and at most two of the first conductive pads (P3) are disposed along the first parallel edge (left); wherein at most two of the first conductive pads disposed along the first parallel edge are located on a side (left side) of at least one of the second conductive pads (P2, P4) disposed along the first parallel edge or the second parallel edge away from the second wire (108-1) connected to the second conductive pads, at most one of the first conductive pad disposed along the second parallel edge is located on a side of at least one of the second conductive pads disposed along the first parallel edge or the second parallel edge away from the second wire connected to the second conductive pads.
In re claim 5, Lum et al. shows (figs. 6, 8) first conductive pads comprise a first type first conductive pad (P3) and a second type first conductive pad (P1); in each of the first bonding regions, the first type first conductive pad and the second type first conductive pad are disposed along the same edge (left edge) of an orthographic projection of each of the driver chips on the substrate; or in each of the first bonding regions, the first type first conductive pad and the second type first conductive pad are disposed along different edges of the orthographic projection of each of the driver chips on the substrate respectively.
In re claim 6, Lum et al. shows (figs. 6, 8) wherein under a condition that the first type first conductive pad (P3) and the second type first conductive pad (P1) are disposed along the same edge (left edge) of an orthographic projection of each of the driver chips (104-1) on the substrate, the first type first conductive pad and the second type first conductive pad are disposed along the first parallel edge (left edge), and one of the first wires (104-1) connected to the first type conductive pad and one of the first wires (additional wire at P1) connected to the second type first conductive pad are located on two sides of the first parallel edge respectively.
In re claim 8, Lum et al. shows (figs. 6, 8) wherein in each of the first bonding regions, the at least two second conductive pads (P2, P4) are disposed along the second parallel edge (right side).
In re claim 10, Lum et al. shows (figs. 6, 8) wherein the orthographic projection of each of the driver chips (82-1, 82-2) on the substrate further comprises a first perpendicular edge (top) and a second perpendicular edge (bottom) that opposite to each other, the first perpendicular edge is perpendicular to the first parallel edge (left), and the second perpendicular edge is perpendicular to the first parallel edge; and in each of the first bonding regions, two of the second conductive pads (P2, P4) connected to the second wire are disposed along the first perpendicular edge and the second perpendicular edge respectively.
In re claim 17, Lum et al. shows (figs. 6, 8) wherein the orthographic projection of each of the driver chips (82-1, 82-2) on the substrate further comprises a first perpendicular edge (top) and a second perpendicular edge (bottom) that are opposite to each other, the first perpendicular edge is perpendicular to the first parallel edge (left), and the second perpendicular edge (right) is perpendicular to the first parallel edge; and in each of the first bonding regions, the at least one third conductive pad (P1) is disposed along at least one of the first perpendicular edge (top) and the second perpendicular edge, and/or, the at least one first conductive pad (P3) is disposed along at least one of the first perpendicular edge and the second perpendicular edge (bottom).
In re claim 18, Lum et al. shows (figs. 6, 8) wherein each of the driver chips comprises (82-1) a first pin (pin at P3) connected to one of the first conductive pads (P3), a second pin (pin at P2) connected correspondingly to one of the second conductive pads (P2, P4), and a third pin (pin at P1) connected to one of the third conductive pads (P1); another end of each of the light emitting units (102) is connected to a fourth wire (106); the first conductive pad, the first wires, the second conductive pads, the second wire, the third conductive pad, and the third wire are in the same metal layer (these elements are formed on the surface of the substrate (84 in fig. 14).
In re claim 19, Lum et al. shows (figs. 6, 8) display panel, wherein the display panel comprises: a substrate (84) comprising at least two first bonding regions (each having P1, P2, P3, P4, etc); at least one first conductive pad (P3) in each of the first bonding regions of the substrate; at least two second conductive pads (P2, P4) disposed in each of the first bonding regions of the substrate; first wires (104-1) disposed on the substrate and each of which is connected to at least two of the first conductive pads (P3) in the first bonding regions; a second wire disposed (108-1) on the substrate and connected to two of the second conductive pads (P4) located in two of the first bonding regions respectively; and driver chips (82-1, 82-2) connected to the first conductive pad and the second conductive pads in each of the first bonding regions; wherein two of the second conductive pads connected to the second wire are located on the same side of each of the first wires (each pad P2 and P4 is located on the right side of the first wire 104-1).
In re claim 20, Lum et al. shows (figs. 6, 8) an array substrate, wherein the array substrate comprises: a substrate (84) comprising at least two first bonding regions (each having P1, P2, P3, P4, etc); at least one first conductive pad (P3) in each of the first bonding regions of the substrate; at least two second conductive pads (P2, P4) disposed in each of the first bonding regions of the substrate; first wires (104-1) disposed on the substrate and each of which is connected to at least two of the first conductive pads (P3) in the first bonding regions; a second wire disposed (108-1) on the substrate and connected to two of the second conductive pads (P4) located in two of the first bonding regions respectively; and driver chips (82-1, 82-2) connected to the first conductive pad and the second conductive pads in each of the first bonding regions; wherein two of the second conductive pads connected to the second wire are located on the same side of each of the first wires (each pad P2 and P4 is located on the right side of the first wire 104-1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7, 9, and 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lum et al. (US Pub. 2021/0364861 A1) as applied to claim 1 above, and further in view of the cited case law.
In re claims 7, 9, and 11-16, Lum shows all of the elements of the claims except additional conductive pads and configurations of the bonding region, conductive pads, wires and edges. It would have been obvious to one of ordinary skill in the art to use three, four, etc., conductive pads since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04 VI. (B). Furthermore, it would have been obvious to one of ordinary skill in the art to form the pads and wires along any edges of the bonding region and in any desired configuration to provide suitable connections for the device. It has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chaji (US Pub. 2020/0013761 A1), Tso (US Pub. 2018/0090037 A1), Lin (US Pub. 2009/0244469 A1), Tian (US 12,520,641 B2), Liu (WO-2022160220 A1), Young (KR-20220078777-A), and Cheng (CN-114530121-A) disclose various elements of the claims.
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/MATTHEW E WARREN/Primary Examiner, Art Unit 2815