Prosecution Insights
Last updated: July 17, 2026
Application No. 17/292,462

ARRAY SUBSTRATE AND DISPLAY DEVICE

Non-Final OA §102
Filed
Apr 30, 2024
Priority
Jan 29, 2021 — CN 202110122863.6 +1 more
Examiner
LEBENTRITT, MICHAEL
Art Unit
Tech Center
Assignee
TCL Technology Group Corporation
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
924 granted / 1002 resolved
+32.2% vs TC avg
Moderate +6% lift
Without
With
+6.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
19 currently pending
Career history
1026
Total Applications
across all art units

Statute-Specific Performance

§101
4.1%
-35.9% vs TC avg
§103
60.4%
+20.4% vs TC avg
§102
13.3%
-26.7% vs TC avg
§112
1.4%
-38.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1002 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 09/25/2022 was filed after the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 6-8 and 11-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by : CN 110993651 A : CN 110993651 A discloses (description, paragraphs 31-56, and figures l-3E) an array substrate, comprising: as shown in figure 1, a light shielding layer arranged on a base substrate at intervals; and a thin film transistor provided on the light shielding layer. The thin film transistor comprises a gate, a source, and a drain. An interlayer insulating layer is provided on the gate, and the source and the drain are provided on the interlayer insulating layer. The gate comprises a first sub-gate layer and a second sub-gate layer which are stacked. The source comprises a first sub-source layer and a second sub-source layer which are stacked. The drain comprises a first sub-drain layer and a second sub-drain layer which are stacked. The first sub-gate layer, the first sub-source layer, and the first sub-drain layer may be made of a transition metal material; The second sub-gate layer, the second sub-source layer, and the second sub-drain layer are made of a metal material. The light shielding layer may be made of a metal such as a single-layer Mo, Al, and Cu, a metal alloy, etc., and may also be made of a double-layer combination of the materials. The light shielding layer is insulated from the gate by means of a buffer layer and the like. It is determined according to figure 1 that the source and the drain are provided on the side of the gate away from the base substrate and are insulated from each other; the orthographic projection of the first sub-gate layer, the first sub-source layer, and the first sub-drain layer on the base substrate respectively covers that of the second sub-gate layer, the second sub-source layer, and the second sub-drain layer on the base substrate, and the orthographic projection of the light shielding layer 20 on the base substrate covers that of the second sub-gate layer, the second sub-source layer, and the second sub-drain layer on the base substrate. In claims 11-12, the first sub-gate layer, the first sub-source layer, the first sub-drain layer, and the light shielding layer are equivalent to at least one functional conductive layer. In claims 13-14, and 18, the first sub-gate layer is equivalent to a first functional conductive layer, and the first sub-source layer and the first sub-drain layer are equivalent to a second functional conductive layer. In claims 6-8 and 16-17, the light shielding layer may be a double-layer material combination, the layer of the light shielding layer close to the base substrate is equivalent to at least one functional conductive layer, and the layer close to the gate is equivalent to at least one metal conductive layer. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. CN 105842904 A discloses (description, paragraphs 39-113, and figures 1a-7) an array substrate, as shown in figure 6, comprising a base substrate, and a gate, a gate insulating layer, a source, and a drain which are sequentially arranged on the base substrate. A light shielding material is respectively provided on the surface of the gate, the source, and the drain close to the base substrate. A pattern of the light shielding material and a pattern of the gate, the source, and the drain coincide with each other in the thickness direction of the base substrate. It is determined according to figure 6 that the source and the drain are provided on the side of the gate away from the base substrate and are insulated from each other; and the orthographic projection of the gate on the base substrate covers that of the source and the drain on the base substrate. Further disclosed is a liquid crystal display device. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. MICHAEL . LEBENTRITT Primary Examiner Art Unit 2893 /MICHAEL LEBENTRITT/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Apr 30, 2024
Application Filed
Jun 03, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Patent 12652915
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2y 7m to grant Granted Jun 09, 2026
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
98%
With Interview (+6.2%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1002 resolved cases by this examiner. Grant probability derived from career allowance rate.

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