Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CN 202110284789.8, filed on 2021-03-17.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/22/2022 in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Please note that foreign patent literature is cited in this action; all paragraph and figure numbers cited from foreign patent literature will hereafter refer to quotations and figures as they appear in the translations thereof attached to this office action.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pu (US 20180033891 A1).
Regarding claim 1, Pu teaches, in FIG. 2, an “oxide layer 41” (paragraph 0015) on a substrate surrounded with “a protection wall 70 extending in the vertical direction D3 and surrounding the oxide semiconductor transistor T1.” Further, paragraph 0014 states: “For example, when the substrate is a semiconductor substrate, a plurality of silicon-based field effect transistors (not shown) may be formed on the semiconductor substrate . . .” Finally, in the “Description of the Prior Art,” Pu teaches “. . . oxide semiconductor materials such as indium gallium zinc oxide (IGZO) are widely applied in thin film transistors (TFTs) of display devices. . .” In this section it is later taught that “accordingly, it is important to effectively block the oxide semiconductor material for improving the electrical stability and the product reliability of the oxide semiconductor device.”
It would have been obvious to one having ordinary skill in the art to combine the invention disclosed by Pu with the teachings disclosed in the “Description of the Prior Art” section also taught by Pu such that the invention comprises a both an LTPO TFT and an LTPS TFT employed in a display device, for the reasons also taught by Pu.
Regarding claim 2, Pu further teaches, in FIG. 2, an insulating layer 31, and that the aforementioned annular retaining wall is disposed in that layer. Further, toward the bottom of paragraph 0019, Pu teaches:
“In some embodiments of the present invention, the protection wall 70 may also be formed by insulation materials, such as aluminum oxide, or the protection wall 70 may also be electrically connected to other circuits according to other considerations. In other words, the protection wall 70 may include an insulation material or may be not electrically floating according to some considerations. For example, when the protection wall 70 is an insulation material, the protection wall 70, the first protection layer 21, the second protection layer 22, and the third protection layer 23 may be formed by one identical insulation material or be formed by different insulation materials.”
It would have been obvious to one having ordinary skill in the art to use a same material as the oxide layer for the annular retaining wall. Pu does not specify a particular material to be used in the annular retaining wall, and it would have been obvious to one having ordinary skill in the art to try using the same material as the oxide layer in the annular retaining wall in order to, for example, reduce the number of materials used in the display panel, thereby reducing manufacturing costs. See KSR International Co. v. Teleflex inc., 82 USPQ2d 1385 (2007).
Regarding claim 3, Pu further teaches that “the shape of the protection wall 70 in the top view diagram of the oxide semiconductor device 102 may include a rectangle, a circle, or other suitable regular or irregular closed patterns” (paragraph 0021).
Regarding claim 4, Pu further teaches, in FIG. 2, that the height of the annular retaining wall is greater than the height of the oxide semiconductor layer.
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pu (US 20180033891 A1) in view of Moon (EP 3174097 A1) and Li (CN 106024639 A).
Regarding claim 5, Pu further teaches “in some embodiments of the present invention, a plurality of the protection walls 70 may be disposed surrounding the oxide semiconductor transistor T1 for further enhancing the ability of blocking the environment substances” (paragraph 0021). In addition, Pu teaches, in FIG. 2, “dielectric layer 11” (paragraph 0015), which can be interpreted by one having ordinary skill in the art to be a buffer layer.
However, Pu does not teach a low-temperature polycrystalline silicon semiconductor layer that is specifically on this buffer layer.
Moon teaches, in FIG. 1, a “thin film transistor T1 having a polycrystalline semiconductor layer A1 and a second thin film transistor T2 having a polycrystalline semiconductor layer (A1) and an oxide semiconductor layer (A2) respectively” (abstract). Further, it can be seen in FIG 1 there is an “buffer layer BUF” on which the polycrystalline silicon layer is disposed.
However, Moon does not specify that this polycrystalline semiconductor layer is a LTPS layer.
Li teaches, in “Background Technology:”
low-temperature polysilicon (Low Temperature Poly-silicon (LTPS) material is preferred, because of the low temperature polycrystalline silicon atoms are regularly arranged, high carrier mobility, for the liquid crystal display device of a voltage drive type, low temperature poly-silicon thin film transistor because it has a higher mobility. It can use small size thin film transistor realizing deflection driving of the liquid crystal molecules, to a great extent reduce the volume occupied by the thin film transistor, to increase the light transmission area, to obtain higher brightness and resolution, for current-driven active matrix type organic electroluminescent display device, a low temperature polysilicon thin film transistor can be better satisfied [can better satisfy] drive current requirements.
It would have been obvious to one having ordinary skill in the art to combine Pu with Moon and Li such that the overall semiconductor device, with multiple annular retaining walls taught by Pu, comprises buffer layer that separates the oxide and polycrystalline layers taught by Moon, and to substitute these polycrystalline layers with LTPS layers as taught by Li. This is amounts to a mere substitution of known elements for others to yield predictable results, as one having ordinary skill in the art is aware of the benefits of utilizing a buffer layer (one of those benefits is, for example, a decrease in manufacturing defect rates) and is taught the benefits of using an LTPS layer by Li. See KSR International Co. v. Teleflex inc., 82 USPQ2d 1385 (2007).
Regarding claim 6, Pu further teaches, in FIG. 2, that the annular retaining wall (of which there may be multiple) is disposed in all layers, which includes layer 21, which, as mentioned above, can be interpreted to be a buffer layer.
It would have been obvious to one having ordinary skill in the art to modify Pu with Moon and Li such that the above annular retaining wall disposed around the LTPS layer is disposed also in the same layer on the buffer layer. One having ordinary skill in the art is motivated to do this because the annular retaining wall is better able to protect the LTPS layer if it is surrounding it (and therefore in the same layer), as is known by one having ordinary skill in the art. Also, one having ordinary skill in the art is motivated to create a second annular retaining wall out of a same material as the LTPS layer for the reasons above.
Allowable Subject Matter
Claims 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Gao (CN 106876386 A) – Annular light blocking layer that comprises the same material as a semiconductor layer, as part of a transistor structure.
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/G.S.M./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897