DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-20 is/are objected to because of the following informalities:
Claims 1, 10, and 19 are objected to because the multiple occurrences of the word “comprising” is unclear as to which elements are part of the claimed device. Also, claiming the subject of the claim in the body of the claim is circular. Further, “plurality of” is missing. Suggested changes are provided below in underlining and strikethrough.
Claims 10 and 19 largely recite the same structural limitations as claim 1 in different statutory form.
The other claims are objected based on their dependency.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3, 12 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. There is no description in the specification as to what constitutes “an integrated structure”.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claims 1, 10, 19, the terminology
“a predetermined angle is unclear as to how the angle is chosen beforehand, and no value or range is recited;
“arranged to be” is unclear as to whether the condition is every satisfied;
“different layers” is unclear as to which element includes layers.
In claim 2, 11, 20, the terminology
“correspondingly passes through” is awkward and unclear.
In claims 3, 12, the terminology
“an integrated structure” is unclear as to what constitutes the limitation.
In claims 5-7, 14-16, the terminology
“close to the fanout area” / “away from the fanout area” is a relative term and the location cannot be determined.
In claims 9, 18, the terminology
“a bending area” is unclear as to its location and which element is bent.
The other claims are rejected as being dependent on an indefinite claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 is/are, to the extent taught and understood, rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication No. 2021/0020724 (Cho).
Cho discloses
[Claim 1] A driver substrate, having a display area DA and a fanout area NDA arranged side by side along a first direction X, comprising:
is aligned with the first direction X at a predetermined angle (90 degrees),
each of the plurality of scan lines Sk-1 / Sk and each of the plurality of data lines DL are located in the display area DA, and one end of each of the plurality of scan lines Sk-1 / Sk close to the fanout area NDA is provided with a scan trace FL extending into the fanout area NDA; and
each of the plurality of data lines DL is connected to a data bridging line CL, the plurality of data lines DL and the data bridging line CL are arranged in different layers, one end of the data bridging line CL is connected to the one of the plurality of data lines DL in the display area DA, and the other end of the data bridging line CL extends into the fanout NDA area along the first direction.
Cho discloses
[Claim 2] The driver substrate according to claim 1,
Cho discloses
[Claim 3] The driver substrate according to claim 2, wherein each of the plurality of scan lines Sk-1 / Sk is arranged on a side of the insulating layer 160 / 150 / 141 / 130 away from the data line DL, and each of the plurality of scan lines Sk-1 / Sk and the data bridging line CL are arranged on a same layer as an integrated structure D1-1 / S1-2 / D5 and ANDE1-3.
Cho discloses
[Claim 4] The driver substrate according to claim 2, further comprising a center line (imaginary middle portion between two sets of 3 dots in at least Fig. 5) parallel to the first direction X, each of the plurality of data lines DL is symmetrically arranged with the center line (imaginary middle portion) as a symmetry axis, the plurality of the data lines DL are divided into a plurality groups of data lines in the first direction X, and each of the plurality groups of data lines comprises at least one of the plurality of data lines DL; and in two adjacent groups of data lines DL, the via hole CT corresponding to one of the plurality groups of data lines DL is located on one side of the center line (imaginary middle portion), and the via hole CT corresponding to the other one of the plurality groups of data lines DL is located on the other side of the center line (imaginary middle portion).
Cho discloses
[Claim 5] The driver substrate according to claim 4, wherein the plurality groups of data lines DL comprise one of the plurality of data lines DL; and among the two adjacent groups of data lines DL, a distance from the via hole CT corresponding to one of the plurality groups of data lines DL close to the fanout area NDA to the center line (imaginary middle portion) is greater than or equal to a distance from the via hole CT corresponding to one of the plurality groups of data lines DL away from the fanout area NDA to the center line (imaginary middle portion).
Cho discloses
[Claim 6] The driver substrate according to claim 4, wherein the plurality groups of data lines DL comprise at least two of the plurality of data lines DL; and among the two adjacent groups of data lines DL, an average distance from each of the plurality of via holes CT corresponding to one of the plurality groups of data lines DL close to the fanout area NDA to the center line (imaginary middle portion) is greater than or equal to an average distance from each of the plurality of via holes CT corresponding to one of the plurality groups of data lines DL away from the fanout area NDA to the center line (imaginary middle portion).
Cho discloses
[Claim 7] The driver substrate according to claim 6, wherein among the two adjacent data lines DL in each of the plurality groups of data lines DL, a distance from one of the plurality of via holes CT corresponding to the data lines DL close to the fanout area NDA to the center line (imaginary middle portion) is greater than a distance from the center line (imaginary middle portion) to one of the plurality of via holes CT corresponding to the data lines DL away from the fanout area NDA.
Cho discloses
[Claim 8] The driver substrate according to claim 1, wherein at least one data bridging line CL is provided between two adjacent scan lines Sk-1 / Sk.
Cho discloses
[Claim 9] The driver substrate according to claim 1, .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 10-20 is/are, to the extent taught and understood, rejected under 35 U.S.C. 103 as being unpatentable over Cho as applied to claims 1-9 above, and further in view of CN Publication No. 106537311 (Morein).
Cho discloses (Claim 10 largely recites the same structural limitations as claim 1 in different statutory form).
[Claim 10] A display module, having a driver substrate SUB1, wherein the driver substrate SUB1 includes a display area DA and a fanout area NDA arranged side by side along a first direction X, comprising:
is aligned with the first direction X at a predetermined angle (90 degrees),
each of the plurality of scan lines Sk-1 / Sk and each of the plurality of data lines DL are located in the display area DA, and one end of each of the plurality of scan lines Sk-1 / Sk close to the fanout area NDA is provided with a scan trace FL extending into the fanout area NDA; and
each of the plurality of data lines DL is connected to a data bridging line CL, the plurality of data lines DL and the data bridging line CL are arranged in different layers, one end of the data bridging line CL is connected to the one of the plurality of data lines DL in the display area DA, and the other end of the data bridging line CL extends into the fanout NDA area along the first direction.
Cho fails to specifically disclose a display module.
Morein teaches
A display module (Fig. 5) having a driver substrate 160.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a display module in Cho. The motivation would be signal integrity, power management, and physical form factor control. It integrates processing hardware directly with the display panel, enabling high-speed data transmission and uniform pixel illumination, which is well-known in the display art. See MPEP 2144.03.
Cho discloses
[Claim 11] The display module according to claim 10, plurality of data lines DL correspondingly passes through one of the plurality of via holes CT and is connected to the data bridging line CL.
Cho discloses
[Claim 12] The display module according to claim 11, wherein each of the plurality of scan lines Sk-1 / Sk is arranged on a side of the insulating layer 160 / 150 / 141 / 130 away from the data line DL, and each of the plurality of scan lines Sk-1 / Sk and the data bridging line CL are arranged on a same layer as an integrated structure D1-1 / S1-2 / D5 and ANDE1-3.
Cho discloses
[Claim 13] The display module according to claim 11, further comprising a center line (imaginary middle portion between two sets of 3 dots in at least Fig. 5) parallel to the first direction X, each of the plurality of data lines DL is symmetrically arranged with the center line (imaginary middle portion) as a symmetry axis, the plurality of the data lines DL are divided into a plurality groups of data lines in the first direction X, and each of the plurality groups of data lines comprises at least one of the plurality of data lines DL; and in two adjacent groups of data lines DL, the via hole CT corresponding to one of the plurality groups of data lines DL is located on one side of the center line (imaginary middle portion), and the via hole CT corresponding to the other one of the plurality groups of data lines DL is located on the other side of the center line (imaginary middle portion).
Cho discloses
[Claim 14] The display module according to claim 13, wherein the plurality groups of data lines DL comprise one of the plurality of data lines DL; and among the two adjacent groups of data lines DL, a distance from the via hole CT corresponding to one of the plurality groups of data lines DL close to the fanout area NDA to the center line (imaginary middle portion) is greater than or equal to a distance from the via hole CT corresponding to one of the plurality groups of data lines DL away from the fanout area NDA to the center line (imaginary middle portion).
Cho discloses
[Claim 15] The display module according to claim 13, wherein the plurality groups of data lines DL comprise at least two of the plurality of data lines DL; and among the two adjacent groups of data lines DL, an average distance from each of the plurality of via holes CT corresponding to one of the plurality groups of data lines DL close to the fanout area NDA to the center line (imaginary middle portion) is greater than or equal to an average distance from each of the plurality of via holes CT corresponding to one of the plurality groups of data lines DL away from the fanout area NDA to the center line (imaginary middle portion).
Cho discloses
[Claim 16] The display module according to claim 15, wherein among the two adjacent data lines DL in each of the plurality groups of data lines DL, a distance from one of the plurality of via holes CT corresponding to the data lines DL close to the fanout area NDA to the center line (imaginary middle portion) is greater than a distance from the center line (imaginary middle portion) to one of the plurality of via holes CT corresponding to the data lines DL away from the fanout area NDA.
Cho discloses
[Claim 17] The display module according to claim 10, wherein at least one data bridging line CL is provided between two adjacent scan lines Sk-1 / Sk.
Cho discloses
[Claim 18] The display module according to claim 10,
Cho discloses (Claim 19 largely recite the same structural limitations as claim 1 in different statutory form).
[Claim 19] A display device, having at least two display modules, wherein the at least two adjacent display modules are arranged side by side along a first direction or a second direction, the at least two display modules having a driver substrate SUB1, wherein the driver substrate SUB1 includes a display area DA and a fanout area NDA arranged side by side along a first direction X, comprising;
is aligned with the first direction X at a predetermined angle (90 degrees),
each of the plurality of scan lines Sk-1 / Sk and each of the plurality of data lines DL are located in the display area DA, and one end of each of the plurality of scan lines Sk-1 / Sk close to the fanout area NDA is provided with a scan trace FL extending into the fanout area NDA; and
each of the plurality of data lines DL is connected to a data bridging line CL, the plurality of data lines DL and the data bridging line CL are arranged in different layers, one end of the data bridging line CL is connected to the one of the plurality of data lines DL in the display area DA, and the other end of the data bridging line CL extends into the fanout NDA area along the first direction.
Cho fails to specifically disclose a display module.
Morein teaches
A display module (Fig. 5) having a driver substrate 160.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a display module in Cho. The motivation would be signal integrity, power management, and physical form factor control. It integrates processing hardware directly with the display panel, enabling high-speed data transmission and uniform pixel illumination, which is well-known in the display art. See MPEP 2144.03. Further, duplication of parts have no patentable significance unless a new and unexpected result is produced. See MPEP 2144.04.
Cho discloses
[Claim 20] The display device according to claim 19, , plurality of data lines DL correspondingly passes through one of the plurality of via holes CT and is connected to the data bridging line CL.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication Nos. 2011/0199348 (Takatani), 2014/0146260 (Lee), 2021/0358357 (Huang) teach a driver substrate used in a display module or display device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893
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