DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 7/6/2026. Claims 1, 3-11, 15, and 23 are pending in this application. Claims 1, 3, and 11 are amended. Claims 2 and 12-14 are canceled. Claim 23 is new.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 7, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Koezuka et al. (US 2018/0254352; hereinafter ‘Koezuka’) in view of Wang et al. (US 2006/0131672; hereinafter ‘Wang’) and Egorov et al. (Physica Status Solidi A 212, 4, 809-816, 2015; hereinafter ‘Egorov’).
Regarding claim 1, Koezuka teaches a transistor structure (100A, FIG. 1B, [0112]) comprising:
a channel material (108, [0116]) comprising a plurality of metals and oxygen (108 includes Al, Ga, Y, Sn, Cu, V, Be, Ti, Fe, Ni, Zr, Mo, La, Ce, Nd, Hf, T, W, Mg, In, and Zn, [0098, 0118]);
a source contact (112a, [0114]) and a drain contact (112b) electrically coupled to the channel material (108, [0113]); and
a gate stack (a gate stack including a gate electrode 104 and a gate dielectric 106, [0114]; hereinafter ‘GS’) comprising a gate electrode (104) and a gate dielectric (106), wherein the gate dielectric (106) is in contact with a portion of the channel material (108) between the source contact (112a) and drain contact (112b, FIG. 1B, [0113-0114]), and wherein:
a first thickness of the gate dielectric (a portion of 106 except 106a; hereinafter ‘106P’) proximal to the gate electrode (106P is located adjacent to and in contact with the gate electrode 104, FIG. 1B) comprises predominantly nitrogen (106P comprises a nitride insulating film containing nitrogen as a main component, [0160]) and a first metal (106 includes an aluminum nitride film, [0222]);
a second thickness of the gate dielectric (106a, FIG. 1B, [0161]) proximal to the channel material (106a is located adjacent to and in contact with the channel material 108, FIG. 1B) comprises predominantly oxygen (106a has a higher oxygen concentration than the other region of 106 and contains a large amount of oxygen, [0161, 0163, 0166]) and the first metal (106 includes an aluminum nitride oxide film, [0222]); and
a third thickness of the gate dielectric (another layer of 106, since 106 have a stacked structure comprising multiple insulating layers and permitting inclusion of an additional dielectric layer within the gate dielectric stack, [0222]) between the channel material (108) and the second thickness of the gate dielectric (106a).
Koezuka does not teach the transistor structure comprising: the third thickness of the dielectric comprises predominantly a second metal and oxygen.
Wang teaches a transistor structure [0009] comprising a multi-stacked gate dielectric structure including nitrogen-containing, oxide-containing, and oxynitride-containing layers, wherein the dielectric includes metals such as Al, Ti, and Hf in combination with oxygen and nitrogen [0009, 0012].
As taught by Wang, one of ordinary skill in the art would utilize and modify the above teaching into Koezuka to obtain and achieve the transistor structure comprising: the gate dielectric structure comprises a metal and oxygen as claimed, because metal-oxide dielectrics provide a higher permittivity, thereby enabling reduced equivalent oxide thickness while maintain electrical insulation and controlling gate leakage [0003, 0025].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Wang in combination with Koezuka due to the above reason.
Koezuka in view of Wang does not teach that the third dielectric layer comprises predominantly a second metal and oxygen distinct from the first metal.
Egorov teaches a dielectric layer (TiON-TiO2-HfO2, Figures 1 and 2, Experimental and 3. Results and discussion), wherein the third thickness of the dielectric (HfO2, Figure 2(b)) comprises predominantly a second metal (Hf) and oxygen (O2) distinct from the first metal (Ti).
As taught by Egorov, one of ordinary skill in the art would utilize and modify the above teaching into Koezuka in view of Wang to obtain and achieve the transistor structure comprising: the third thickness of the dielectric comprises predominantly a second metal and oxygen as claimed, because the TiON-TiO2-HfO2 stacked dielectric structure provides reliable dielectric functionality and contributes to improved electrical characteristics of the device, thereby achieving predictable improvements in dielectric performance, enhanced interface stability, and improved electrical control of semiconductor devices (Abstract and 1. Introduction).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Egorov in combination with Koezuka in view of Wang due to the above reason.
Regarding claim 3, Koezuka in view of Wang and Egorov teaches the transistor structure of claim 1, wherein the first thickness comprises more nitrogen than oxygen (Koezuka: 106P includes aluminum nitride film and does not contain oxygen, [0161, 0222]), and the second thickness comprises more oxygen than nitrogen (106a includes aluminum nitride oxide with a higher oxygen concentration).
Regarding claim 4, Koezuka in view of Wang and Egorov teaches the transistor structure of claim 3, Koezuka in view of Wang does not teach the transistor structure wherein the second metal is Hf.
Egorov teaches that the second metal is Hf (the second metal is Hf, Figure 2(b)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Egorov to obtain and achieve the transistor structure wherein the second metal is Hf as claimed, because hafnium oxide is a well-known material and widely used as a gate insulating layer in the art. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 7, Koezuka in view of Wang and Egorov teaches the transistor structure of claim 1, wherein the first thickness of the gate dielectric is proximal to the gate electrode (Koezuka: 160P is proximal to 104, FIG. 1B) and the second thickness of the gate dielectric is proximal to the channel material (106a is proximal to 108).
Regarding claim 10, Koezuka in view of Wang and Egorov teaches the transistor structure of claim 1, wherein the plurality of metals of the channel material comprises In, Ga and Zn (Koezuka: 180 includes Ga, In, and Zn, [0098, 0118]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Koezuka (US 2018/0254352) in view of Wang (US 2006/0131672) and Egorov (Physica Status Solidi A, 212, 4, 809-816, 2015) as applied to claim 4 above, and further in view of Pandey et al. (Journal of Applied Physics, 114, 034505, 2013; hereinafter ‘Pandey’).
Regarding claim 5, Koezuka in view of Wang and Egorov teaches the transistor structure of claim 4, Koezuka in view of Wang does not teach the transistor structure wherein: the first metal is Ti; the first thickness comprises TiOxNy and y is at least 0.5; the second thickness comprises TiOxNy and x is at least 0.5; and the second metal is Hf.
Egorov teaches the dielectric layer (TiON-TiO2-HfO2, Figure 2(b)), wherein:
the first metal is Ti (the first metal is Ti);
the first thickness comprises TiOxNy (the first thickness comprises TiON);
the second thickness comprises TiOxNy and x is at least 0.5 (the second thickness comprises TiO2 and x is 2); and
the second metal is Hf (the second metal is Hf).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Egorov to obtain and the transistor structure wherein: the first metal is Ti; the first thickness comprises TiOxNy; the second thickness comprises TiOxNy and x is at least 0.5; and the second metal is Hf as claimed, because the TiON-TiO2-HfO2 stacked dielectric structure provides reliable dielectric functionality and contributes to improved electrical characteristics of the device, thereby achieving predictable improvements in dielectric performance, enhanced interface stability, and improved electrical control of semiconductor devices (Abstract and 1. Introduction).
Koezuka in view of Wang and Egorov does not teach that the dielectric layer comprises TiOxNy and y is at least 0.5.
Pandey teaches a dielectric interface region (HfO2/TiN interface region, Table III) comprising TiOxNy with nitrogen-dominant composition.
Pandey does not explicitly disclose TiOxNy where y is at least 0.5.
Pandey, however, teaches nitrogen-rich Ti-O-N compositions suggests TiOxNy composition in which nitrogen is present in an amount equal to or greater than oxygen, including compositions where y is at least (III. RESULTS, C. Effective work function engineering, Table III).
As taught by Pandey, one of ordinary skill in the art would utilize and modify the above teaching into Koezuka in view of Wang and Egorov to obtain and achieve the transistor structure wherein: the first thickness comprises TiOxNy and y is at least 0.5 as claimed, because nitrogen-rich or oxygen-rich interface compositions significantly affect effective work function and threshold voltage, thereby improving electrical performance of semiconductor devices (Abstract and Introduction).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Pandey in combination with Koezuka in view of Wang and Egorov due to the above reason.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Koezuka (US 2018/0254352) in view of Wang (US 2006/0131672), Egorov (Physica Status Solidi A, 212, 4, 809-816, 2015), and Pandey (Journal of Applied Physics, 114, 034505, 2013) as applied to claim 5 above, and further in view of Wu et.al. (US 2020/0258893; hereinafter ‘Wu’).
Regarding claim 6, Koezuka in view of Wang, Egorov, and Pandey teaches the transistor structure of claim 5, wherein the second thickness is 1-5 nm (Koezuka: 106a has a thickness 1 to 10 nm, [0162])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify thickness of the insulating layer of Koezuka to obtain the transistor structure wherein the second thickness is 1-5 nm as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Koezuka in view of Wang and Pandey does not teach the transistor structure wherein the first thickness is 1-2 nm and the third thickness is at least 3 nm.
Egorov teaches the dielectric layer wherein the third thickness is at least 3 nm (HfO2 has 3 nm thickness, 2 Experimental).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify thickness of the insulating layer of Egorov to obtain the transistor structure wherein third thickness is at least 3 nm as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Koezuka in view of Wang, Egorov, and Pandey does not teach the transistor structure wherein the first thickness is 1-2 nm.
Wu teaches a transistor structure [0010], wherein the first thickness is 1-2 nm (thickness of the gate dielectric layer is 0.5 nm to 5 nm, [0043]).
As taught by Wu, one of ordinary skill in the art would utilize and modify the above teaching into Koezuka in view of Wang, Egorov, and Pandey to obtain and achieve the transistor structure wherein the first thickness is 1-2 nm as claimed, because it aids in effectively providing insulation maintaining the thickness at a scale of several nanometers is essential to effectively match with the size of other semiconductor layers [0042-0044, 0085]. Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Wu in combination with Koezuka in view of Wang, Egorov, and Pandey due to the above reason.
Claim 8 is rejected under 35 U.S.C. 1, 03 as being unpatentable over Koezuka (US 2018/0254352) in view of Wang (US 2006/0131672) and Egorov (Physica Status Solidi A, 212, 4, 809-816, 2015) as applied to claim 7 above, and further in view of Liu et al. (Applied Physics Letters, 88, 192904, 2006; hereinafter ‘Liu’).
Regarding claim 8, Koezuka in view of Wang and Egorov teaches the transistor structure of claim 7, but does not teach the transistor structure wherein the second thickness comprises HfOx, the first thickness comprises HfOxNy, and y is at least 0.5.
Liu teaches a gate dielectric layer (abstract) wherein the second thickness comprises HfOx (the second thickness comprises HfO, 192904-2), the first thickness comprises HfOxNy, and y is at least 0.5 (the first thickness comprises HfO0.59N0.55, 192904-1).
As taught by Liu, one of ordinary skill in the art would utilize and modify the above teaching into Koezuka in view of Wang and Egorov to obtain and achieve the transistor structure wherein the second thickness comprises HfOx, the first thickness comprises HfOxNy, and y is at least 0.5 as claimed, because the dielectric function and electrical characteristics of HfON-based gate dielectrics depend on nitrogen and oxygen composition, and oxygen-rich and nitrogen-containing regions provide controllable electrical and interface properties (192904-1).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Liu in combination with Koezuka in view of Wang and Egorov due to the above reason.
Claim 9 is rejected under 35 U.S.C. 1, 03 as being unpatentable over Koezuka (US 2018/0254352) in view of Wang (US 2006/0131672) and Egorov (Physica Status Solidi A, 212, 4, 809-816, 2015) as applied to claim 7 above, and further in view of Wu (US 2020/0258893).
Regarding claim 9, Koezuka in view of Wang and Egorov teaches the transistor structure of claim 7, but does not teach the transistor structure wherein the second thickness is no more than 1 nm, and a sum of the first and second thicknesses is at least 3 nm.
Wu teaches a transistor structure [0010], wherein the second thickness is no more than 1 nm (thickness of the gate dielectric layer is 0.5 nm to 5 nm, [0043]), and a sum of the first and second thicknesses is at least 3 nm (thickness of two gate dielectric layer is 1 nm to 10 nm).
As taught by Wu, one of ordinary skill in the art would utilize and modify the above teaching into Koezuka in view of Wang and Egorov to obtain and achieve the transistor structure wherein the second thickness is no more than 1 nm, and a sum of the first and second thicknesses is at least 3 nm as claimed, because it aids in effectively providing insulation maintaining the thickness at a scale of several nanometers is essential to effectively match with the size of other semiconductor layers [0042-0044, 0085]. Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Wu in combination with Koezuka in view of Wang and Egorov due to the above reason.
Claim 11 is rejected under 35 U.S.C. 1, 03 as being unpatentable over Pan et al. (RSC Advances, 5, 51286, 2015; hereinafter ‘Pan’) in view of Chen et al. (CN 112750828A, equivalent to US 2022/0320284 as English translation; hereinafter ‘Chen’).
Regarding claim 11, Pan teaches a transistor structure (Fig. 1, Experimental) comprising:
a channel material (IGZO) comprising a plurality of metals and oxygen (IGZO is InGaZnO);
a source contact (Source) and a drain contact (Drain) electrically coupled to the channel material (IGZO); and
a gate stack (a gate stack including a gate electrode TaN and a gate dielectric HfO2/Er2O3/HfO2, FIG. 1; hereinafter ‘GS’) comprising a gate electrode (TaN) and a gate dielectric (HfO2/Er2O3/HfO2), wherein the gate dielectric (HfO2/Er2O3/HfO2) is in contact with a portion of the channel material (IGZO) between the source contact (Source) and drain contact (Drain), and wherein:
a first thickness of the gate dielectric (HfO2 adjacent to TaN; hereinafter ‘HfO1’), proximal to the gate electrode (TaN), comprises predominantly oxygen (O2) and Hf (Hf);
a second thickness of the gate dielectric (HfO2 adjacent to IGZO; hereinafter ‘HfO2’), proximate to the channel material (IGZO), comprises predominantly oxygen (O2) and Hf (Hf); and
a third thickness of the gate dielectric (Er2O3) between the first (HfO1) and second thicknesses (HfO2), comprises a second metal (Er) and oxygen (O2).
Pan does not teach that the second metal is Mg.
Chen teaches a transistor structure [0021] wherein the second metal is Mg (gate dielectric layers have oxides of Mg, [0034]).
As taught by Chen, one of ordinary skill in the art would utilize and modify the above teaching into Pan to obtain and achieve the transistor structure wherein the second metal is Mg as claimed, because MgO is a known material and widely used as a gate dielectric material in the art. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Chen in combination with Pan due to the above reason.
Claim 15 is rejected under 35 U.S.C. 1, 03 as being unpatentable over Pan (RSC Advances, 5, 51286, 2015) in view of Chen (CN 112750828A) as applied to claim 11, and further in view of Wu (US 2020/0258893).
Regarding claim 15, Pan in view of Chen teaches a transistor structure of claim 11, but does not teach the transistor structure wherein: the first thickness is 1-3 nm; the second thickness is 1-3 nm; and the third thickness is less than 1 nm.
Wu teaches a transistor structure [0010], wherein the first thickness is 1-3 nm; the second thickness is 1-3 nm; and the third thickness is less than 1 nm (thickness of the gate dielectric layer is 0.5 nm to 5 nm, [0043]).
As taught by Wu, one of ordinary skill in the art would utilize and modify the above teaching into Pan in view of Chen to obtain and achieve the transistor structure wherein: the first thickness is 1-3 nm; the second thickness is 1-3 nm; and the third thickness is less than 1 nm as claimed, because it aids in effectively providing insulation maintaining the thickness at a scale of several nanometers is essential to effectively match with the size of other semiconductor layers [0042-0044, 0085]. Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Wu in combination with Pan in view of Chen due to the above reason.
Claim 23 is rejected under 35 U.S.C. 1, 03 as being unpatentable over Pan (RSC Advances, 5, 51286, 2015) in view of Chen (CN 112750828A) as applied to claim 11, and further in view of Koezuka (US 2018/0254352).
Regarding claim 23, Pan in view of Chen teaches a transistor structure of claim 11, but does not teach the transistor structure wherein the plurality of metals of the channel material comprises In, Ga and Zn.
Koezuka teaches a transistor structure [0010] wherein the plurality of metals of the channel material comprises In, Ga and Zn (Koezuka: 180 includes Ga, In, and Zn, [0098, 0118]).
As taught by Koezuka, one of ordinary skill in the art would utilize and modify the above teaching into Pan in view of Chen to obtain and achieve the transistor structure wherein the plurality of metals of the channel material comprises In, Ga and Zn as claimed, because In-Ga-Zn oxide channel provides increased field-effect mobility and favorable electrical characteristics, thereby enabling a high-performance and reliable transistor [0118].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Koezuka in combination with Pan in view of Chen due to the above reason.
Response to Arguments
Applicant's arguments have been fully considered but are not persuasive for the reason discussed below.
Applicant submits, on page 7 of Remarks, that “There is no rational basis for one of ordinary skill to seek to enlist materials taught by Egorov as being suitable in a resistive memory stack for the wholly different purpose as a gate dielectric of any of the transistors of Koezuka or Wang”.
The examiner respectfully disagrees.
The rejection does not rely on Egorov alone to teach the claimed transistor structure. Koezuka teaches the transistor structure, including the channel material, source and drain contacts, gate electrode, and gate dielectric, while Wang and Egorov are relied upon for their respective teachings concerning multilayer dielectric structures and metal oxide and oxynitride dielectric materials. The fact that Egorov employs its dielectric stack in a resistive memory device does not render its teaching inapplicable to a transistor gate dielectric. Egorov’s TiON, TiO2, and HfO2 materials retain their dielectric and interfacial properties regardless of the particular semiconductor device in which they are employed. Moreover, Wang expressly teaches the use of corresponding Ti-, Hf-, oxygen-, and nitrogen-containing materials in multilayer transistor gate dielectrics. Accordingly, one of ordinary skill in the art would have had a rational basis to apply Egorov’s dielectric-material teaching when implementing Wang’s multilayer dielectric structure in Koezuka’s transistor.
Applicant submits, on page 7 of Remarks, that “since Egorov’s ReRAM device has no gate electrode and no channel material, there is no guidance as to where within a transistor gate dielectric comprising multiple materials one or ordinary skill should position Egorov’s TiN, HfO2, and TiO relative to the gate electrode and channel material in the transistors of either Koezuka or Wang”.
The examiner respectfully disagrees.
This argument considers Egorov individually rather than the combined teachings of the cited references. Koezuka teaches insulating layer 106 disposed between gate electrode 104 and channel material 108, including a first thickness proximal to and in contact with gate electrode 104 and a second thickness 106a proximal to and in contact with channel material 108 (FIG. 1B, [0113-0114, 0160-0161]). Koezuka further teaches that insulating layer 106 may comprise a stacked structure of two or more insulating layers [0222]. Wang teaches the incorporation of metal oxide and oxynitride materials into a multilayer gate dielectric, and Egorov teaches a stacked dielectric arrangement including TiON, TiO2, and HfO2. When these teachings are combined as set forth in the rejection, the HfO2 layer constitutes the claimed third thickness between channel material 108 and second thickness 106a. Accordingly, the combined teachings provide the claimed relative positions of the dielectric thicknesses.
Applicant submits, on page 9 of Remarks, that “The examiner therefore appears to have employed impermissible hindsight in combining Pan with Chen. Use of impermissible hindsight is evidenced by the fact that Chen is art particular to Group IV FETs with pure Si or SiGe channel material instead of the metal oxide channel material of Pan” and “Since Pan’s channel material is not silicon-based, it is unclear that Pan’s TFT has the compositional flexibility of Chen’s gate dielectric since there is no clear analog to Chen’s interfacial oxide layers 127”.
The examiner respectfully disagrees.
The rejection does not incorporate Chen’s entire FET structure, channel material, or interfacial oxide layer 127 into Pan. Rather, Chen is relied upon for its teaching that Mg oxide and Er oxide are alternative high-k gate dielectric materials suitable for use in a transistor gate structure [0034]. Pan already teaches an IGZO TFT having a HfO2/Er2O3/HfO2 stacked gate dielectric. Accordingly, the proposed modification merely replaces Pan’s central Er2O3 gate dielectric material with MgO, which Chen identifies as another suitable high-k gate dielectric material.
Chen’s interfacial oxide layer 127 is separate from high-k gate dielectric layer 128, and Chen does not condition the suitability of Mg oxide as a high-k gate dielectric material upon the presence of interfacial oxide layer 127 or upon the use of a Si or SiGe channel. Moreover, claim 11 does not require or exclude an interfacial oxide layer. Accordingly, the difference between the channel materials of Pan and Chen does not render Chen’s teaching concerning the selection of Mg oxide as a gate dielectric material inapplicable to Pan.
Applicant submits, on page 9 of Remarks, that “one of ordinary skill would not reasonably seek to employ materials taught by Chen as being suitable in a gate dielectric stack of a silicon FET for the wholly different purpose of a gate dielectric in Pan’s metal-oxide channeled TFT without some basis of a reasonable expectation despite the absence of an analog to Chen’s interfacial oxide. Accordingly, without some further justification bridging this logical gap, the combination of Chen with Pan appears to be a result of improper hindsight bias as including a reference from an art unrelated to the TFT of Pan”.
The examiner respectfully disagrees.
Pan and Chen both concern transistor gate structures employing high-k metal oxide dielectric materials. Pan expressly demonstrates the use of an Er2O3-containing stacked gate dielectric in an IGZO TFT, while Chen identifies both Er oxide and Mg oxide as suitable alternative high-k gate dielectric materials [0034]. One of ordinary skill in the art therefore would have reasonably selected MgO in place of Pan’s Er2O3 layer because both materials were known for the same gate dielectric function. Such a substitution would have been a predictable use of a known high-k gate dielectric material according to its established function and would not have required incorporation of Chen’s silicon channel or interfacial oxide layer into Pan. Accordingly, the proposed combination is supported by the express teachings of the references and is not based on impermissible hindsight.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure in that Doyle et al. (US 2020/0388711) and Agrawal et al. (US 2021/0036023) as a thin film transistor employing oxide-semiconductor channel materials and metal-oxide gate dielectric structures.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 9/8/26
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