DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/15/2025 has been entered.
Status of the Application
Acknowledgement is made of the amendment received on 11/14/2025. Claims 1-15 are pending in this application. Claims 1, 7, 11, and 14 are amended.
Claim Objections
Claim 11 is objected to because of the following informalities:
In claim 11, line 4, “a gate electrode material” should read --a gate electrode -- (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “a first thickness of the gate dielectric comprises predominantly nitrogen and a first metal; a second thickness of the gate dielectric comprises predominantly oxygen and the first metal; and a third thickness of the gate dielectric between the channel material and the second thickness of the gate dielectric comprises predominantly a second metal and oxygen” in lines 7-13. However, the claim uses the term “thickness” as though it defines three distinct structural portions of the gate dielectric, while simultaneously using “thickness” in its ordinary sense as a dimensional property.
The claim does not clearly recite:
(a) that the first, second, and third thicknesses correspond to three distinct layers or regions, nor
(b) where one thickness ends and another begins.
Although the specification describes different layers within the gate dielectric (e.g., metal oxide layers, oxynitride layers, interlayers), the claim does not recite the term “layer” or “region”, and instead defines the structure solely in terms of “thickness”.
Because a “thickness” is ordinarily understood as a measurement rather than a structural component, it is under whether:
(a) the claim is directed to three discrete layers, or
(b) compositional gradients within a single continuous layer.
Accordingly, the structural boundaries of the recited “first thickness”, “second thickness”, and “third thickness” are not reasonably certain.
For best understand and examination purpose, the claim will be best considered based on drawings, disclosure, and/or any applicable prior arts; and the claim limitation “a first thickness of the gate dielectric comprises predominantly nitrogen and a first metal; a second thickness of the gate dielectric comprises predominantly oxygen and the first metal; and a third thickness of the gate dielectric between the channel material and the second thickness of the gate dielectric comprises predominantly a second metal and oxygen” will be interpreted as --a first layer of the gate dielectric comprises predominantly nitrogen and a first metal and having a first thickness; a second layer of the gate dielectric comprises predominantly oxygen and the first metal and having a second thickness; and a third layer of the gate dielectric between the channel material and the second thickness of the gate dielectric comprises predominantly a second metal and oxygen and having a third thickness-- in the instant Office Action.
Claim 6 recites the limitation “the first thickness is 1-2 nm; the second thickness is 1-5 nm; and the third thickness is at least 3 nm” in lines 2-4. Here, “thickness” is used in its conventional dimensional sense.
Because claim 1 already defines “thickness” as though it were a structural portion of the dielectric, and claim 6 then assigns numerical dimensions to those thickness”, the claim set conflates:
(a) a structural element, and
(b) a dimensional property of that element.
The claim language therefore fails to clearly distinguish whether:
(a) each “thickness” is itself a structural layer having a thickness, or
(b) the term “thickness” merely refers to a measurement within a continuous dielectric material.
This internal inconsistency renders the metes and bounds of the claimed structure unclear.
For best understand and examination purpose, the claim will be best considered based on drawings, disclosure, and/or any applicable prior arts; and the claim limitation “the first thickness is 1-2 nm; the second thickness is 1-5 nm; and the third thickness is at least 3 nm” will be interpreted as --the first layer has a thickness of 1-2 nm; the second layer has a thickness of 1-5 nm; and the third layer has a thickness of at least 3 nm-- in the instant Office Action.
Claims 2-5 and 7-10 are rejected due to their dependency
Claim 11 recites the limitation “a first thickness of the gate dielectric, proximal to the gate electrode, comprises predominantly oxygen and a first metal; a second thickness of the gate dielectric, proximate to the channel material, comprises predominantly oxygen and the first metal; and a third thickness of the gate dielectric, between the first and second thicknesses, comprises a second metal and oxygen, or is substantially silicon” in lines 7-12. However, similar to claim 1, the claim does not clearly define these thicknesses as discrete structural layers.
The term “thickness” is used as though it defines structural components of the dielectric, but the claim fails to define the structural boundaries between the recited thickness portions. It is therefore unclear whether the claim requires separate dielectric layers or merely compositional regions within a continuous dielectric body.
Accordingly, the scope of claim 11 is not reasonably certain.
Claim 15 recites the limitation “the first thickness is 1-3 nm; the second thickness is 1-3 nm; and the third thickness is less than 1 nm” in lines 2-4. However, claim 11 does not clearly define these thicknesses as structural layers, claim 15 introduces dimensional limitations without clearly identifying the structural elements to which the thicknesses correspond.
As a result, the metes and bounds of the claimed invention are unclear, and claim 15 is indefinite.
Claims 12-14 are rejected due to their dependency
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pan et al. (RSC Advances, 5, 51286, 2015; hereinafter ‘Pan’).
Regarding claim 11, Pan teaches a transistor structure (Fig. 1, Experimental) comprising:
a channel material (IGZO) comprising a plurality of metals and oxygen (IGZO is InGaZnO);
a source contact (Source) and a drain contact (Drain) electrically coupled to the channel material (IGZO); and
a gate stack (104 and 106, [0114]; hereinafter ‘GS’) comprising a gate electrode material (TaN) and a gate dielectric (HfO2/Er2O3/HfO2), wherein the gate dielectric (HfO2/Er2O3/HfO2) is in contact with a portion of the channel material (IGZO) between the source contact (Source) and drain contact (Drain), and wherein:
a first thickness of the gate dielectric (HfO2 adjacent to TaN; hereinafter ‘HfO1’), proximal to the gate electrode (TaN), comprises predominantly oxygen (O2) and a first metal (Hf);
a second thickness of the gate dielectric (HfO2 adjacent to IGZO; hereinafter ‘HfO2’), proximate to the channel material (IGZO), comprises predominantly oxygen (O2) and the first metal (Hf); and
a third thickness of the gate dielectric (Er2O3) between the first (HfO1) and second thicknesses (HfO2), comprises a second metal (Er) and oxygen (O2), or is substantially silicon.
Regarding claim 12, Pan teaches a transistor structure of claim 11, wherein the first metal is Hf (Hf, Fig. 1, Experimental).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Koezuka et al. (US 2018/0254352; hereinafter ‘Koezuka’) in view of Wang et al. (US 2006/0131672; hereinafter ‘Wang’) and Egorov et al. (Physica Status Solidi A 212, 4, 809-816, 2015; hereinafter ‘Egorov’).
Regarding claim 1, Koezuka teaches a transistor structure (100A, FIG. 1B, [0112]) comprising:
a channel material (108, [0116]) comprising a plurality of metals and oxygen (108 includes Al, Ga, Y, Sn, Cu, V, Be, Ti, Fe, Ni, Zr, Mo, La, Ce, Nd, Hf, T, W, Mg, In, and Zn, [0098, 0118]);
a source contact (112a, [0114]) and a drain contact (112b) electrically coupled to the channel material (108, [0113]); and
a gate stack (104 and 106, [0114]; hereinafter ‘GS’) comprising a gate electrode (104) and a gate dielectric (106), wherein the gate dielectric (106) is in contact with a portion of the channel material (108) between the source contact (112a) and drain contact (112b), and wherein:
a first thickness of the gate dielectric (a portion of 106 except 106a; hereinafter ‘106P’) comprises predominantly nitrogen (106P does not contain oxygen as a main component, [0161]) and a first metal (106 includes an aluminum nitride film, [0222]);
a second thickness of the gate dielectric (106a) comprises predominantly oxygen (106a containing a large amount of oxygen, [0163]) and the first metal (106 includes an aluminum nitride oxide film, [0222]); and
a third thickness of the gate dielectric (another layer of 106, since 106 have a stacked structure comprising multiple insulating layers and permitting inclusion of an additional dielectric layer within the gate dielectric stack, [0222]) between the channel material (108) and the second thickness of the gate dielectric (106a).
Koezuka does not teach the transistor structure comprising: the third thickness of the dielectric comprises predominantly a second metal and oxygen.
Wang teaches a transistor structure [0009] comprising a multi-stacked gate dielectric structure including nitrogen-containing, oxide-containing, and oxynitride-containing layers, wherein the dielectric includes metals such as Al, Ti, and Hf in combination with oxygen and nitrogen [0009, 0012].
As taught by Wang, one of ordinary skill in the art would utilize and modify the above teaching into Koezuka to obtain and achieve the transistor structure comprising: the gate dielectric structure comprises a metal and oxygen as claimed, because metal-oxide dielectrics provide a higher permittivity, thereby enabling reduced equivalent oxide thickness while maintain electrical insulation and controlling gate leakage [0003, 0025].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Wang in combination with Koezuka due to above reason.
Koezuka in view of Wang does not teach that the third dielectric layer comprises predominantly a second metal and oxygen distinct from the first metal.
Egorov teaches a dielectric layer (TiON-TiO2-HfO2, Figures 1 and 2, Experimental and 3. Results and discussion), wherein the third thickness of the dielectric (HfO2, Figure 2(b)) comprises predominantly a second metal (Hf) and oxygen (O2) distinct from the first metal (Ti).
As taught by Egorov, one of ordinary skill in the art would utilize and modify the above teaching into Koezuka in view of Wang to obtain and achieve the transistor structure comprising: the third thickness of the dielectric comprises predominantly a second metal and oxygen as claimed, because the TiON-TiO2-HfO2 stacked dielectric structure provides reliable dielectric functionality and contributes to improved electrical characteristics of the device, thereby achieving predictable improvements in dielectric performance, enhanced interface stability, and improved electrical control of semiconductor devices (Abstract and 1. Introduction).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Egorov in combination with Koezuka in view of Wang due to above reason.
Regarding claim 2, Koezuka in view of Wang and Egorov teaches the transistor structure of claim 1, wherein the first thickness is proximal to the gate electrode (Koezuka: 106P is proximal to 104, FIG. 1B) and the second thickness is proximal to the channel material (106a is proximal to 108).
Regarding claim 3, Koezuka in view of Wang and Egorov teaches the transistor structure of claim 2, wherein the first thickness comprises more nitrogen than oxygen (Koezuka: 106P includes aluminum nitride film and does not contain oxygen, [0161, 0222]), and the second thickness comprises more oxygen than nitrogen (106a includes aluminum nitride oxide with a higher oxygen concentration).
Regarding claim 4, Koezuka in view of Wang and Egorov teaches the transistor structure of claim 3, Koezuka in view of Wang does not teach the transistor structure wherein the second metal is Hf.
Egorov teaches that the second metal is Hf (the second metal is Hf, Figure 2(b)).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Egorov to obtain and achieve the transistor structure wherein the second metal is Hf as claimed, because hafnium oxide is a well-known material and widely used as a gate insulating layer in the art. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 7, Koezuka in view of Wang and Egorov teaches the transistor structure of claim 1, wherein the first thickness of the gate dielectric is proximal to the gate electrode (Koezuka: 160P is proximal to 104, FIG. 1B) and the second thickness of the gate dielectric is proximal to the channel material (106a is proximal to 108).
Regarding claim 10, Koezuka in view of Wang and Egorov teaches the transistor structure of claim 1, wherein the plurality of metals of the channel material comprises In, Ga and Zn (Koezuka: 180 includes Ga, In, and Zn, [0098, 0118]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Koezuka (US 2018/0254352) in view of Wang (US 2006/0131672) and Egorov (Physica Status Solidi A, 212, 4, 809-816, 2015), and further in view of Pandey et al. (Journal of Applied Physics, 114, 034505, 2013; hereinafter ‘Pandey’).
Regarding claim 5, Koezuka in view of Wang and Egorov teaches the transistor structure of claim 4, Koezuka in view of Wang does not teach the transistor structure wherein: the first metal is Ti; the first thickness comprises TiOxNy and y is at least 0.5; the second thickness comprises TiOxNy and x is at least 0.5; and the second metal is Hf.
Egorov teaches the dielectric layer (TiON-TiO2-HfO2, Figure 2(b)), wherein:
the first metal is Ti (the first metal is Ti);
the first thickness comprises TiOxNy (the first thickness comprises TiON);
the second thickness comprises TiOxNy and x is at least 0.5 (the second thickness comprises TiO2 and x is 2); and
the second metal is Hf (the second metal is Hf).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Egorov to obtain and the transistor structure wherein: the first metal is Ti; the first thickness comprises TiOxNy; the second thickness comprises TiOxNy and x is at least 0.5; and the second metal is Hf as claimed, because the TiON-TiO2-HfO2 stacked dielectric structure provides reliable dielectric functionality and contributes to improved electrical characteristics of the device, thereby achieving predictable improvements in dielectric performance, enhanced interface stability, and improved electrical control of semiconductor devices (Abstract and 1. Introduction).
Koezuka in view of Wang and Egorov does not teach that the dielectric layer comprises TiOxNy and y is at least 0.5.
Pandey teaches a dielectric interface region (HfO2/TiN interface region, Table III) comprising TiOxNy with nitrogen-dominant composition.
Pandey does not explicitly disclose TiOxNy where y is at least 0.5.
Pandey, however, teaches nitrogen-rich Ti-O-N compositions suggests TiOxNy composition in which nitrogen is present in an amount equal to or greater than oxygen, including compositions where y is at least (III. RESULTS, C. Effective work function engineering, Table III).
As taught by Pandey, one of ordinary skill in the art would utilize and modify the above teaching into Koezuka in view of Wang and Egorov to obtain and achieve the transistor structure wherein: the first thickness comprises TiOxNy and y is at least 0.5 as claimed, because nitrogen-rich or oxygen-rich interface compositions significantly affect effective work function and threshold voltage, thereby improving electrical performance of semiconductor devices (Abstract and Introduction).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Pandey in combination with Koezuka in view of Wang and Egorov due to above reason.
Claims 6 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Koezuka (US 2018/0254352) in view of Wang (US 2006/0131672), Egorov (Physica Status Solidi A, 212, 4, 809-816, 2015), and Pandey (Journal of Applied Physics, 114, 034505, 2013), and further in view of Wu et.al. (US 2020/0258893; hereinafter ‘Wu’).
Regarding claim 6, Koezuka in view of Wang, Egorov, and Pandey teaches the transistor structure of claim 5, wherein the second thickness is 1-5 nm (Koezuka: 106a has a thickness 1 to 10 nm, [0162])
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify thickness of the insulating layer of Koezuka to obtain the transistor structure wherein the second thickness is 1-5 nm as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Koezuka in view of Wang and Pandey does not teach the transistor structure wherein the first thickness is 1-2 nm and the third thickness is at least 3 nm.
Egorov teaches the dielectric layer wherein the third thickness is at least 3 nm (HfO2 has 3 nm thickness, 2 Experimental).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify thickness of the insulating layer of Egorov to obtain the transistor structure wherein third thickness is at least 3 nm as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Koezuka in view of Wang, Egorov, and Pandey does not teach the transistor structure wherein the first thickness is 1-2 nm.
Wu teaches a transistor structure [0010], wherein the first thickness is 1-2 nm (thickness of the gate dielectric layer is 0.5 nm to 5 nm, [0043]).
As taught by Wu, one of ordinary skill in the art would utilize and modify the above teaching into Koezuka in view of Wang, Egorov, and Pandey to obtain and achieve the transistor structure wherein the first thickness is 1-2 nm as claimed, because it aids in effectively providing insulation maintaining the thickness at a scale of several nanometers is essential to effectively match with the size of other semiconductor layers [0042-0044, 0085]. Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Wu in combination with Koezuka in view of Wang, Egorov, and Pandey due to above reason.
Claim 8 is rejected under 35 U.S.C. 1, 03 as being unpatentable over Koezuka (US 2018/0254352) in view of Wang (US 2006/0131672) and Egorov (Physica Status Solidi A, 212, 4, 809-816, 2015), and further in view of Liu et al. (Applied Physics Letters, 88, 192904, 2006; hereinafter ‘Liu’).
Regarding claim 8, Koezuka in view of Wang and Egorov teaches the transistor structure of claim 7, but does not teach the transistor structure wherein the second thickness comprises HfOx, the first thickness comprises HfOxNy, and y is at least 0.5.
Liu teaches a gate dielectric layer (abstract) wherein the second thickness comprises HfOx (the second thickness comprises HfO, 192904-2), the first thickness comprises HfOxNy, and y is at least 0.5 (the first thickness comprises HfO0.59N0.55, 192904-1).
As taught by Liu, one of ordinary skill in the art would utilize and modify the above teaching into Koezuka in view of Wang and Egorov to obtain and achieve the transistor structure wherein the second thickness comprises HfOx, the first thickness comprises HfOxNy, and y is at least 0.5 as claimed, because the dielectric function and electrical characteristics of HfON-based gate dielectrics depend on nitrogen and oxygen composition, and oxygen-rich and nitrogen-containing regions provide controllable electrical and interface properties (192904-1).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Liu in combination with Koezuka in view of Wang and Egorov due to above reason.
Claim 9 is rejected under 35 U.S.C. 1, 03 as being unpatentable over Koezuka (US 2018/0254352) in view of Wang (US 2006/0131672) and Egorov (Physica Status Solidi A, 212, 4, 809-816, 2015), and further in view of Wu (US 2020/0258893).
Regarding claim 9, Koezuka in view of Wang and Egorov teaches the transistor structure of claim 7, but does not teach the transistor structure wherein the second thickness is no more than 1 nm, and a sum of the first and second thicknesses is at least 3 nm.
Wu teaches a transistor structure [0010], wherein the second thickness is no more than 1 nm (thickness of the gate dielectric layer is 0.5 nm to 5 nm, [0043]), and a sum of the first and second thicknesses is at least 3 nm (thickness of two gate dielectric layer is 1 nm to 10 nm).
As taught by Wu, one of ordinary skill in the art would utilize and modify the above teaching into Koezuka in view of Wang and Egorov to obtain and achieve the transistor structure wherein the second thickness is no more than 1 nm, and a sum of the first and second thicknesses is at least 3 nm as claimed, because it aids in effectively providing insulation maintaining the thickness at a scale of several nanometers is essential to effectively match with the size of other semiconductor layers [0042-0044, 0085]. Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Wu in combination with Koezuka in view of Wang and Egorov due to above reason.
Claim 13 is rejected under 35 U.S.C. 1, 03 as being unpatentable over Pan (RSC Advances, 5, 51286, 2015) in view of Chen et al (CN 112750828A, equivalent to US 2022/0320284 as English translation; hereinafter ‘Chen’).
Regarding claim 13, Pan teaches a transistor structure of claim 12, but does not teach the transistor structure wherein the second metal is Mg.
Chen teaches a transistor structure [0021] wherein the second metal is Mg (gate dielectric layers have oxides of Mg, [0034]).
As taught by Chen, one of ordinary skill in the art would utilize and modify the above teaching into Pan to obtain and achieve the transistor structure wherein the second metal is Mg as claimed, because MgO is a known (well-known) material and widely used as a gate dielectric material in the art. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chen in combination with Pan due to above reason.
Claim 14 is rejected under 35 U.S.C. 1, 03 as being unpatentable over Pan (RSC Advances, 5, 51286, 2015) in view of Arghavani et al (US 2003/0124871; hereinafter ‘Arghavani’).
Regarding claim 14, Pan teaches a transistor structure of claim 12, but does not teach the transistor structure wherein the third thickness of the gate dielectric is substantially Si.
Arghavani teaches a transistor structure (FIG. 3, [0030]) wherein the third thickness of the gate dielectric is substantially Si (214 is silicon interfacial layer).
As taught by Arghavani, one of ordinary skill in the art would utilize and modify the above teaching into Pan to obtain and achieve the transistor structure wherein the third thickness of the gate dielectric is substantially Si as claimed, because it provides to preserve the dielectric integrity of the high-k layer and maintain desired gate insulation characteristics [0033-0034, 0051].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Arghavani in combination with Pan due to above reason.
Claim 15 is rejected under 35 U.S.C. 1, 03 as being unpatentable over Pan (RSC Advances, 5, 51286, 2015) in view of Wu (US 2020/0258893).
Regarding claim 15, Pan teaches a transistor structure of claim 11, but does not teach the transistor structure wherein: the first thickness is 1-3 nm; the second thickness is 1-3 nm; and the third thickness is less than 1 nm.
Wu teaches a transistor structure [0010], wherein the first thickness is 1-3 nm; the second thickness is 1-3 nm; and the third thickness is less than 1 nm (thickness of the gate dielectric layer is 0.5 nm to 5 nm, [0043]).
As taught by Wu, one of ordinary skill in the art would utilize and modify the above teaching into Koezuka to obtain and achieve the transistor structure wherein: the first thickness is 1-3 nm; the second thickness is 1-3 nm; and the third thickness is less than 1 nm as claimed, because it aids in effectively providing insulation maintaining the thickness at a scale of several nanometers is essential to effectively match with the size of other semiconductor layers [0042-0044, 0085]. Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Wu in combination with Pan due to above reason.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/27/26