Attorney’s Docket Number: 00158.0767.00US
Filing Date: 5/10/2021
Inventor: Wang
Examiner: Marcos D. Pizarro
DETAILED ACTION
This Office action responds to the amendment filed on 7/17/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 7/17/2025 in reply to the previous Office action in paper no. 17, mailed on 2/20/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1, 4-6 and 8-23.
Claim Rejections - 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1, 4-6, 8-10, 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Colombeau (US 2021/0119021) in view of Chang (US 2021/0343578).
Regarding claim 1, Colombeau (see, e.g., figs. 1-13) shows all aspects of the instant invention including a semiconductor device 1150 comprising:
A substrate
A fin 110 on the substrate
A gate structure on the substrate and across the fin 110
A sidewall spacer 302, and
A barrier layer 116
wherein:
The fin includes a first region that includes a plurality of gate grooves 900 and a channel layer 112 between adjacent grooves
The gate structure fills the grooves 900, surrounds the channel 112, and covers a sidewall and a top of the first region, and
A first width of the gate structure in the grooves 900 is smaller than a second width of the gate structure on top of the first region
Both the gate structures in the grooves 900 and on top of the first region include a gate dielectric layer 1310 on a surface of the channel 112, a work function layer 1320 on the gate dielectric, and a gate electrode 1330 on the work function layer
The barrier layer 116 is located on a sidewall of the gate structure in the grooves
The sidewall spacer 302 is on a sidewall of the gate structure on top of the first region
A sidewall of the barrier layer 116 contacting the gate structure is closer to the center of the gate structure than a sidewall of the spacer 302 contacting the gate structure, along a horizontal direction
Colombeau teaches that the sidewall spacer may be formed of any suitable material known to those of ordinary skill in the art and further teaches the use of a low-k dielectric material for the spacer (see, e.g., par.0032/ll.9-12). However, Colombeau does not explicitly disclose the spacer comprising a stacked structure including first and second sidewall spacers formed of different materials.
Chang shows a semiconductor device 100 similar to that of Colombeau, likewise including sidewall spacers 160 formed adjacent to a gate structure 220 (see, e.g., Chang, fig. 14A). Chang teaches that the spacer may include a stacked structure 160 comprising first 162 and second 164 sidewall spacers of different dielectric materials and illustrates such a stacked structure 160 in figure 5B. Chang teaches that the materials for the sidewall spacers include silicon oxide, silicon nitride, silicon oxynitride, SiCN films, SiOCN films, and/or combinations thereof (see, e.g., par.0031).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the sidewall spacer of Colombeau to include the stacked sidewall spacer structure taught by Chang. Both references are directed to similar semiconductor devices and fabrication techniques, and the sidewall spacers in both references serve similar purposes, including defining gate electrode openings and controlling critical dimensions during subsequent processing steps. Incorporating Chang’s stacked spacer structure into Colombeau’s device would have been a predictable variation yielding known benefits such as improved process control and spacer functionality.
Regarding claim 4, Colombeau (see, e.g., fig. 12F) shows the device wherein:
A sidewall of the barrier layer 116, which is away from the gate structure, is closer to the center of the gate structure than a sidewall of the spacer 302, or
The sidewall of the barrier layer 116, which is away from the gate structure, is flush with the sidewall of the spacer
Regarding claim 5, Colombeau (see, e.g., fig. 12F) shows the device wherein:
The fin includes a second region
A source/drain doped layer 420 is in the second region, and
The fin of the second region 420 is on two sides of the gate structure
Regarding claim 10, Colombeau (see, e.g., fig. 12F) shows the device further comprises a dielectric layer 500 on top of the source/drain 420 and covering the sidewall of the gate structure.
Regarding claim 6, Colombeau (see, e.g., par. 0037/ll.15-16) shows the channel layer is monocrystalline silicon.
Regarding claim 8, Colombeau (see, e.g., par. 0044) shows the device wherein:
The gate dielectric 1310 is a high-k dielectric material with k greater than 3.9
The high-k material includes at least one or a combination of hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide
Regarding claim 9, Colombeau (see, e.g., par. 0045) teaches that the work function layer can be any suitable material known to the skilled artisan. Chang (see, e.g., par.0056), on the other hand, teaches that suitable work function materials include titanium nitride, aluminum titanium or tantalum nitride.
Regarding claim 21, Colombeau (see, e.g., fig. 12B) shows that the gate structure on top of the first region and the gate structure in the grooves 900 are in contact with each other without a channel layer 112 between them.
Regarding claim 22, Colombeau (see, e.g., fig. 12F) shows the device wherein:
A source/drain layer 420 covers an entire sidewall of the channel 112, an entire sidewall of the barrier layer 116 and a first part of a sidewall of the spacer 302
A top surface of the source/drain 420 is higher than a top surface of the barrier layer 116
A dielectric layer 500 is on top of the source/drain 420 and covers a second part of the sidewall of the spacer 302
A top surface of the dielectric layer 500 is coplanar with a top surface of the gate structure
Regarding claim 23, Chang shows that the material of the first spacer is silicon nitride, the material of the second spacer is silicon oxide, and the barrier layer is made of at least one of SiOCN, SiOC and SiON. See, e.g., Chang: par.0031/l.10-17 and par.0034/l.8-11.
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Marcos D. Pizarro/Primary Examiner, Art Unit 2814
MDP/mdp
January 14, 2026
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